CN114253332A - Anti-interference band-gap reference source circuit - Google Patents
Anti-interference band-gap reference source circuit Download PDFInfo
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- CN114253332A CN114253332A CN202111541449.5A CN202111541449A CN114253332A CN 114253332 A CN114253332 A CN 114253332A CN 202111541449 A CN202111541449 A CN 202111541449A CN 114253332 A CN114253332 A CN 114253332A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an anti-interference band-gap reference source circuit. The anti-interference band-gap reference source circuit comprises: the band-gap reference source circuit comprises a power supply end and an output end, wherein the power supply end is connected with a power supply signal; the band-gap reference source circuit is used for forming a reference voltage with a zero temperature coefficient at the output end based on the power supply signal; the anti-interference circuit is connected with an external power supply and the power end of the band-gap reference source circuit and used for isolating the jitter of the external power supply and forming the power supply signal to the power end of the band-gap reference source circuit. The anti-interference band-gap reference source circuit can solve the problem that in the prior art, when an external power supply generates interference such as jump and the like, the reference voltage output by the reference source circuit also generates jump to interfere the output of the reference source circuit.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an anti-interference band-gap reference source circuit.
Background
The reference source circuit generates a reference voltage and a reference current along with a starting signal of the power starting circuit, and can provide stable reference voltage and reference current for other modules, so that the reference source circuit is widely applied to integrated circuits.
However, in the related art, the external power supply directly supplies power to the reference source circuit, and when the external power supply generates interference such as a jump, the reference voltage output by the reference source circuit in the related art is also interfered by the external power supply, that is, when the external power supply generates interference such as a jump, the reference voltage output by the reference source circuit in the related art also generates a jump, and the output of the reference source circuit is interfered.
Disclosure of Invention
The application provides an anti-interference band-gap reference source circuit, which can solve the problem that in the prior art, when an external power supply generates interference such as jump and the like, the reference voltage output by the reference source circuit also generates jump to interfere the output of the reference source circuit.
In order to solve the technical problem in the prior art, the present application provides an anti-interference bandgap reference source circuit, the anti-interference bandgap reference source circuit includes:
the band-gap reference source circuit comprises a power supply end and an output end, wherein the power supply end is connected with a power supply signal; the band-gap reference source circuit is used for forming a reference voltage with a zero temperature coefficient at the output end based on the power supply signal;
the anti-interference circuit is connected with an external power supply and the power end of the band-gap reference source circuit and used for isolating the jitter of the external power supply and forming the power supply signal to the power end of the band-gap reference source circuit.
Optionally, the interference rejection circuit includes a first MOS transistor M1, a second MOS transistor M2, a first capacitor C1, a first resistor R1, and a first transistor Q1;
the grid electrode of the first MOS transistor M1 is connected with the drain electrode of the first MOS transistor M1;
the drain of the first MOS transistor M1 is further connected to the emitter of the first transistor Q1, the collector of the first transistor Q1 is grounded, and the base of the first transistor Q1 is connected to the first end of the first capacitor C1 and is grounded;
a second end of the first capacitor C1 is connected to the gate of the second MOS transistor M2, the source of the first MOS transistor M1, and a first end of the first resistor R1 to form a first connection node P1;
the second end of the first resistor R1 is connected with the power supply end of the band-gap reference source circuit.
The drain of the second MOS transistor M2 is connected to the external power supply VDD, and the source of the second MOS transistor M2 is connected to the power supply terminal of the bandgap reference source circuit.
Optionally, the voltage VNG of the first connected node P1 is equal to: VNG VGS1+ VNG 1;
VGS1 is the voltage between the gate and the source of the first MOS transistor M1; VNG1 is the voltage between the base and emitter of the first transistor Q1.
Optionally, the second MOS transistor M2 is an intrinsic NMOS with zero threshold voltage.
Optionally, the voltage at the source of the second MOS transistor M2 is the same as the voltage VNG of the first connected node P1.
Optionally, the bandgap reference source circuit includes: the circuit comprises a first current branch, a second current branch, a third current branch and an operational amplifier OPA;
the first current branch comprises a third MOS transistor M3 and a second triode Q2, the source electrode of the third MOS transistor M3 is connected with the power supply end, the drain electrode of the third MOS transistor M3 is connected with the emitter electrode of the second triode Q2, and the collector electrode of the second triode Q2 is grounded;
the second current branch comprises a fourth MOS transistor M4, a third transistor Q3 and a second resistor R2, the source of the fourth MOS transistor M4 is connected to the power supply terminal, the drain of the fourth MOS transistor M4 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the emitter of the third transistor Q3, and the collector of the third transistor Q3 is grounded;
the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and is connected to the output terminal of the operational amplifier OPA, the inverting input terminal of the operational amplifier OPA is connected to the drain of the third MOS transistor M3 to form a second connection node P2, and the non-inverting input terminal of the operational amplifier OPA is connected to the drain of the fourth MOS transistor M4 to form a third connection node P3;
the third current branch comprises a source electrode of a fifth MOS transistor M5 connected with the power supply end, a drain electrode of the fifth MOS transistor M5 is the output end of the band-gap reference source circuit, and a grid electrode of the fifth MOS transistor M5 is connected with the output end of the operational amplifier OPA.
Optionally, the bandgap reference source circuit further includes a second capacitor C2, a third resistor R3 and a fourth resistor R4;
a first end of the third resistor R3 is connected to the third connection node P3, and a second end of the third resistor R3 is grounded;
a first end of the fourth resistor R4 is connected with the drain of the fifth MOS transistor M5, and a second end of the fourth resistor R4 is grounded;
the first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is connected to the first end of the fourth resistor R4.
The technical scheme at least comprises the following advantages: the jitter of an external power supply can be isolated through the anti-interference circuit, and a jitter-free power supply signal is formed, so that the band-gap reference source circuit has a good anti-interference effect.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a block diagram illustrating a structure of a bandgap reference source circuit with immunity to interference provided by an embodiment of the present application;
fig. 2 shows a circuit schematic of the tamper resistant bandgap reference source circuit of fig. 1.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a block diagram of a structure of a tamper-resistant bandgap reference source circuit according to an embodiment of the present application, and as can be seen from fig. 1, the tamper-resistant bandgap reference source circuit includes: a bandgap reference source circuit 110 and an immunity circuit 120.
The bandgap reference source circuit 110 includes a power supply terminal connected to a power supply signal VCORE and an output terminal OUT; the bandgap reference source circuit 110 is configured to form a reference voltage with zero temperature coefficient at the output terminal OUT based on the power supply signal VCORE.
The anti-jamming circuit 120 is connected to an external power supply VDD and the power supply terminal of the bandgap reference source circuit 110, and is configured to isolate jitter of the external power supply VDD and form the power supply signal VCORE to the power supply terminal of the bandgap reference source circuit 110.
Referring to fig. 2, which shows a schematic circuit diagram of the tamper resistant bandgap reference source circuit shown in fig. 1, as can be seen from fig. 2, the tamper resistant circuit 120 includes a first MOS transistor M1, a second MOS transistor M2, a first capacitor C1, a first resistor R1, and a first transistor Q1.
The gate of the first MOS transistor M1 is connected to the drain of the first MOS transistor M1.
The drain of the first MOS transistor M1 is further connected to the emitter of the first transistor Q1, the collector of the first transistor Q1 is grounded, and the base of the first transistor Q1 is connected to the first end of the first capacitor C1 and is grounded;
the second end of the first capacitor C1 is connected to the gate of the second MOS transistor M2, the source of the first MOS transistor M1, and the first end of the first resistor R1, forming a first connection node P1.
The second end of the first resistor R1 is connected to the power supply end of the bandgap reference source circuit 110.
Illustratively, the drain of the second MOS transistor M2 is connected to the external power supply VDD, and the source of the second MOS transistor M2 is connected to the power supply terminal of the bandgap reference source circuit.
The voltage VNG of the first connected node P1 is equal to: VNG VGS1+ VNG 1.
VGS1 is the voltage between the gate and the source of the first MOS transistor M1; VNG1 is the voltage between the base and emitter of the first transistor Q1.
The voltage at the source of the second MOS transistor M2 is the same as the voltage VNG at the first node P1.
In this embodiment, the anti-interference circuit can isolate the jitter of the external power supply to form a jitter-free power supply signal, so that the band-gap reference source circuit has a good anti-interference effect.
With continued reference to fig. 2, the bandgap reference source circuit 10 includes: the circuit comprises a first current branch, a second current branch, a third current branch and an operational amplifier OPA.
The first current branch comprises a third MOS tube M3 and a second triode Q2, the source electrode of the third MOS tube M3 is connected with the power supply end, the drain electrode of the third MOS tube M3 is connected with the emitter electrode of the second triode Q2, and the collector electrode of the second triode Q2 is grounded.
The second current branch comprises a fourth MOS tube M4, a third triode Q3 and a second resistor R2, the source electrode of the fourth MOS tube M4 is connected with the power supply end, the drain electrode of the fourth MOS tube M4 is connected with the first end of the second resistor R2, the second end of the second resistor R2 is connected with the emitter electrode of the third triode Q3, and the collector electrode of the third triode Q3 is grounded.
The gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and connected to the output terminal of the operational amplifier OPA, the inverting input terminal of the operational amplifier OPA is connected to the drain of the third MOS transistor M3 to form a second connection node P2, and the non-inverting input terminal of the operational amplifier OPA is connected to the drain of the fourth MOS transistor M4 to form a third connection node P3.
The third current branch comprises a fifth MOS transistor M5, the source of which is connected to the power supply terminal, the drain of which is the output terminal OUT of the bandgap reference source circuit 110, and the gate of which is connected to the output terminal of the operational amplifier OPA.
The bandgap reference source circuit 110 further includes a second capacitor C2, a third resistor R3 and a fourth resistor R4.
The first end of the third resistor R3 is connected to the third connecting node P3, and the second end of the third resistor R3 is grounded.
A first end of the fourth resistor R4 is connected to the drain of the fifth MOS transistor M5, and a second end of the fourth resistor R4 is grounded.
The first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is connected to the first end of the fourth resistor R4.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. An anti-jamming bandgap reference source circuit, comprising:
the band-gap reference source circuit comprises a power supply end and an output end, wherein the power supply end is connected with a power supply signal; the band-gap reference source circuit is used for forming a reference voltage with a zero temperature coefficient at the output end based on the power supply signal;
the anti-interference circuit is connected with an external power supply and the power end of the band-gap reference source circuit and used for isolating the jitter of the external power supply and forming the power supply signal to the power end of the band-gap reference source circuit.
2. The tamper-resistant bandgap reference source circuit of claim 1, wherein the tamper-resistant circuit comprises a first MOS transistor M1, a second MOS transistor M2, a first capacitor C1, a first resistor R1, and a first transistor Q1;
the grid electrode of the first MOS transistor M1 is connected with the drain electrode of the first MOS transistor M1;
the drain of the first MOS transistor M1 is further connected to the emitter of the first transistor Q1, the collector of the first transistor Q1 is grounded, and the base of the first transistor Q1 is connected to the first end of the first capacitor C1 and is grounded;
a second end of the first capacitor C1 is connected to the gate of the second MOS transistor M2, the source of the first MOS transistor M1, and a first end of the first resistor R1 to form a first connection node P1;
the second end of the first resistor R1 is connected with the power supply end of the band-gap reference source circuit;
the drain of the second MOS transistor M2 is connected to the external power supply VDD, and the source of the second MOS transistor M2 is connected to the power supply terminal of the bandgap reference source circuit.
3. The tamper-resistant bandgap reference source circuit of claim 2, wherein the voltage VNG of said first connecting node P1 is equal to: VNG VGS1+ VNG 1;
VGS1 is the voltage between the gate and the source of the first MOS transistor M1; VNG1 is the voltage between the base and emitter of the first transistor Q1.
4. The tamper resistant bandgap reference source circuit of claim 2, wherein said second MOS transistor M2 is an intrinsic NMOS with zero threshold voltage.
5. The tamper-resistant bandgap reference source circuit of claim 2, wherein the voltage at the source of said second MOS transistor M2 is substantially the same as the voltage VNG of said first connected node P1.
6. The tamper resistant bandgap reference source circuit of claim 1, wherein said bandgap reference source circuit comprises: the circuit comprises a first current branch, a second current branch, a third current branch and an operational amplifier OPA;
the first current branch comprises a third MOS transistor M3 and a second triode Q2, the source electrode of the third MOS transistor M3 is connected with the power supply end, the drain electrode of the third MOS transistor M3 is connected with the emitter electrode of the second triode Q2, and the collector electrode of the second triode Q2 is grounded;
the second current branch comprises a fourth MOS transistor M4, a third transistor Q3 and a second resistor R2, the source of the fourth MOS transistor M4 is connected to the power supply terminal, the drain of the fourth MOS transistor M4 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the emitter of the third transistor Q3, and the collector of the third transistor Q3 is grounded;
the gate of the third MOS transistor M3 is connected to the gate of the fourth MOS transistor M4 and is connected to the output terminal of the operational amplifier OPA, the inverting input terminal of the operational amplifier OPA is connected to the drain of the third MOS transistor M3 to form a second connection node P2, and the non-inverting input terminal of the operational amplifier OPA is connected to the drain of the fourth MOS transistor M4 to form a third connection node P3;
the third current branch comprises a source electrode of a fifth MOS transistor M5 connected with the power supply end, a drain electrode of the fifth MOS transistor M5 is the output end of the band-gap reference source circuit, and a grid electrode of the fifth MOS transistor M5 is connected with the output end of the operational amplifier OPA.
7. The tamper resistant bandgap reference source circuit of claim 6, further comprising a second capacitor C2, a third resistor R3 and a fourth resistor R4;
a first end of the third resistor R3 is connected to the third connection node P3, and a second end of the third resistor R3 is grounded;
a first end of the fourth resistor R4 is connected with the drain of the fifth MOS transistor M5, and a second end of the fourth resistor R4 is grounded;
the first end of the second capacitor C2 is grounded, and the second end of the second capacitor C2 is connected to the first end of the fourth resistor R4.
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| CN202111541449.5A CN114253332B (en) | 2021-12-16 | 2021-12-16 | Anti-interference band-gap reference source circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111541449.5A CN114253332B (en) | 2021-12-16 | 2021-12-16 | Anti-interference band-gap reference source circuit |
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| CN114253332A true CN114253332A (en) | 2022-03-29 |
| CN114253332B CN114253332B (en) | 2023-03-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114688961A (en) * | 2022-04-02 | 2022-07-01 | 南通四建集团有限公司 | Scaffold frame warp detecting system device |
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2021
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| CN106155152A (en) * | 2015-03-31 | 2016-11-23 | 成都锐成芯微科技有限责任公司 | A kind of band-gap reference circuit with high PSRR characteristic |
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| CN114688961A (en) * | 2022-04-02 | 2022-07-01 | 南通四建集团有限公司 | Scaffold frame warp detecting system device |
| CN114688961B (en) * | 2022-04-02 | 2024-01-26 | 南通四建集团有限公司 | Scaffold deformation detection system device |
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| CN114253332B (en) | 2023-03-07 |
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