CN114236925B - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN114236925B CN114236925B CN202111560939.XA CN202111560939A CN114236925B CN 114236925 B CN114236925 B CN 114236925B CN 202111560939 A CN202111560939 A CN 202111560939A CN 114236925 B CN114236925 B CN 114236925B
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- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 29
- 239000010409 thin film Substances 0.000 claims abstract description 71
- 239000010408 film Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 142
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 239000012044 organic layer Substances 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 3
- 230000035515 penetration Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 18
- 238000003860 storage Methods 0.000 description 10
- 238000002161 passivation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 101100006548 Mus musculus Clcn2 gene Proteins 0.000 description 2
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Geometry (AREA)
Abstract
The invention relates to an array substrate and a liquid crystal display panel, wherein a shared common electrode and a grid scanning line are arranged on the same layer, a first through hole is formed to expose part of the shared common electrode and part of a drain electrode of a third thin film transistor, and the drain electrode of the third thin film transistor is electrically connected with the shared common electrode through a conductive film layer, so that the shared common electrode only exists in a non-display area between a main pixel electrode and a secondary pixel electrode, the shared common electrode does not need to penetrate through the main pixel electrode and the secondary pixel electrode, the aperture ratio of the pixel electrode is increased, and the penetration rate is increased.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a liquid crystal display panel.
Background
The 8-domain pixel architecture realizes the visual angle optimization of a VA (vertical alignment) display mode on the premise of keeping the quantity of the original COF (chip on film). The existing 8-domain pixel architectures of mass production are divided into a 3T pixel architecture (fig. 1) and a 3T Plus pixel architecture (fig. 2 and 3), and in the early stage of development of the 8-domain pixel architectures, the pixel architectures used by the liquid crystal display panel are all 3T pixel architectures, referring to fig. 1, a main-region thin film transistor T main The grid electrode of the grid electrode is connected with the scanning line Gate, the source electrode is connected with the Data line Data, and the drain electrodes are respectively connected with the main area storage capacitor C st_main One terminal of (1) and a main area liquid crystal capacitor C lc_main One terminal, main region storage capacitor C st_main The other end of the first electrode is connected with an array common electrode Acom, and a main area liquid crystal capacitor C lc_main The other end of the CF common electrode is connected with the CF common electrode CFcom; sub-region thin film transistor T sub The grid electrode of the grid electrode is connected with a scanning line Gate, the source electrode is connected with a Data line Data, and the drain electrodes are respectively connected with a sub-area storage capacitor C st_sub One terminal of (1) and a sub-area liquid crystal capacitor C lc_sub One terminal of (A), a sub-area storage capacitor C st_sub The other end of the array is connected with an array common electrode Acom and a sub-area liquid crystal capacitor C lc_sub The other end of the CF common electrode is connected with the CF common electrode CFcom; shared thin film transistor T cs The grid electrode of the first transistor is connected with the data line Gate, and the source electrode of the first transistor is connected with the sub-area thin film transistor T sub And the drain electrode is connected with the array common electrode Acom.
But the main means to improve the viewing angle due to the 3T pixel architecture is to pass the voltage of the sub-pixel electrode (sub-pixel) through the shared thin film transistor T cs Share to the array common electrode Acom because the array common electrode Acom and the sub-pixel electrode exist one sub-timeZone storage capacitor C st_sub Therefore, a problem of lateral crosstalk may be caused due to instability of the array common electrode Acom voltage.
In order to solve the problem of crosstalk, a 3T Plus pixel architecture is developed, and in the 3T Plus pixel architecture, a sub-area storage capacitor C is mainly arranged between a holding array common electrode Acom and a sub-pixel electrode st_sub The second array common electrode Acom2 (shared bar, shared common electrode) is arranged under the unchanged condition, and the voltage of the sub-pixel electrode is shared on Acom2, but because Acom2 in the existing 3T Plus pixel architecture longitudinally passes through the display area (refer to fig. 3 and 3 a), that is, acom2 passes through the main pixel electrode (main pixel) and the sub-pixel electrode, that is, passes through the display area, the aperture ratio of the pixel electrode is reduced, and further the penetration ratio is reduced.
Disclosure of Invention
The invention aims to solve the problem that the aperture opening ratio of a pixel electrode is reduced due to the conventional 3T Plus pixel structure.
In order to achieve the above object, the present invention provides an array substrate, including: a base plate; a first metal layer disposed on the base plate, the first metal layer comprising: the grid scanning line, the array common electrode and the shared common electrode are arranged in parallel at intervals; the pixel electrode layer and the first metal layer are arranged on the bottom plate in different layers, the pixel electrode layer comprises a plurality of sub-pixel electrodes which are arranged in an array mode, and the sub-pixel electrodes comprise main pixel electrodes and sub-pixel electrodes; a first thin film transistor having a drain electrode electrically connected to the main pixel electrode; a second thin film transistor, a drain of which is electrically connected to the sub-pixel electrode; and a source of the third thin film transistor is electrically connected with the drain of the second thin film transistor, and a drain of the third thin film transistor is electrically connected with the shared common electrode.
Optionally, the array substrate further includes: the grid insulating layer is arranged on the bottom plate and covers the first metal layer; a second metal layer disposed on the gate insulating layer, the second metal layer including a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and a source and a drain of the third thin film transistor; the organic layer is arranged on the second metal layer, a first through hole which exposes a part of the shared common electrode and exposes a part of the source electrode or the drain electrode of the third thin film transistor is formed in the surface of the organic layer, and the pixel electrode layer is arranged on the organic layer outside the first through hole; and the conductive film layer is deposited on the first via hole, at least covers the shared common electrode and part of the source electrode or part of the drain electrode of the third thin film transistor, and the drain electrode of the third thin film transistor is electrically connected with the shared common electrode through the conductive film layer.
Optionally, the first via hole is opened on the surface of the organic layer between the main pixel electrode and the sub-pixel electrode.
Optionally, an inner diameter of the first via hole near the shared common electrode is smaller than an inner diameter of the first via hole near the organic layer.
Optionally, the first via hole exposes a sidewall of the drain of the third thin film transistor.
Optionally, the first via hole exposes a sidewall of the drain electrode of the third thin film transistor and a part of a surface of the drain electrode facing away from the shared common electrode.
Optionally, the array substrate further includes: the grid insulation layer is arranged on the bottom plate and covers the first metal layer, and a second through hole for exposing part of the shared common electrode is formed in the surface of the grid insulation layer; the drain of the third thin film transistor is electrically connected to the shared common electrode through the second via hole.
Optionally, the shared common electrode is located between the gate scan line and the array common electrode corresponding to the sub-pixel electrode.
The present invention also provides a liquid crystal display panel, comprising: an array substrate as hereinbefore described; the color film substrate is arranged opposite to the array substrate; and the liquid crystal layer is arranged between the array substrate and the color film substrate.
The array substrate and the liquid crystal display panel have the advantages that the shared common electrode and the grid scanning line are arranged on the same layer, the first through hole is formed to expose part of the shared common electrode and part of the drain electrode of the third thin film transistor, and the drain electrode of the third thin film transistor is electrically connected with the shared common electrode through the conductive film layer, so that the shared common electrode only exists in the non-display area between the main pixel electrode and the sub-pixel electrode, the shared common electrode does not need to penetrate through the main pixel electrode and the sub-pixel electrode, the aperture ratio of the pixel electrode is increased, and the penetration rate is increased.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIG. 1 is a circuit diagram of a conventional 3T pixel architecture;
FIG. 2 is a circuit schematic of a conventional 3T Plus pixel architecture;
FIG. 3 is a top view of a sub-pixel of a conventional 3T Plus pixel architecture;
FIG. 3a is a schematic view of a portion of the structure of FIG. 3;
fig. 4 is a top view of a sub-pixel of an array substrate according to an exemplary embodiment of the present invention;
FIG. 4a is a schematic view of a portion of the structure of FIG. 4;
fig. 5 is a circuit diagram of a pixel architecture in an array substrate according to an exemplary embodiment of the invention;
FIG. 6 isbase:Sub>A sectional view taken along line A-A of FIG. 4base:Sub>A;
fig. 7 is a schematic structural diagram of a liquid crystal display panel according to an exemplary embodiment of the present invention;
fig. 8 is a schematic structural view of an array substrate according to another exemplary embodiment of the present invention;
fig. 9 is a plan view of a sub-pixel of an array substrate according to still another exemplary embodiment of the present invention;
FIG. 9a is a partial schematic view of FIG. 9;
fig. 10 is a sectional view taken along line B-B of fig. 9 a.
In fig. 6 and 10, the data line is not shown.
The parts in the figure are numbered as follows:
1. the liquid crystal display panel comprises a liquid crystal display panel body 100, 100', an array substrate body 110, a base plate 120, a gate scanning line 121, a shared common electrode 130, a gate insulating layer 131, a first opening 140, a data line 150, a passivation layer 151, 151', a second opening 160, an organic layer 161, a color resistance layer 1611, 1611', a third opening 162, a planarization layer 1621, a fourth opening 163, a connecting hole 170, a sub-pixel 171, a main pixel electrode 172, a sub-pixel electrode 181, 181', a first via hole 182, a second via hole 191, a connecting film layer 192, a conductive film layer 200, a color film substrate 210, a substrate 220, a black matrix layer 230, a color film layer 300 and a liquid crystal layer.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
According to the array substrate provided by the invention, the shared common electrode and the scanning line are arranged on the same layer, the first through hole is formed to expose part of the shared common electrode and part of the drain electrode of the third thin film transistor, and the drain electrode of the third thin film transistor is electrically connected with the shared common electrode through the conductive film layer, so that the shared common electrode only exists in the non-display area between the main pixel electrode and the sub-pixel electrode, the shared common electrode does not need to penetrate through the main pixel electrode and the sub-pixel electrode, the aperture ratio of the pixel electrode is increased, and the penetration rate is increased. As a typical application, the array substrate may be used on a liquid crystal display panel, which may be applied on a display terminal, such as a thin film transistor-liquid crystal display (TFT-LCD).
In an embodiment of the invention, referring to fig. 4 to 6 and 4a, the array substrate 100 includes a bottom plate 110, a first metal layer M1 (not shown), a gate insulating layer 130, a second metal layer M2 (not shown), a passivation layer 150, an organic layer 160, and a pixel electrode layer (not shown) which are stacked. The organic layer 160 includes a color resist layer 161 and a planarization layer 162 that are stacked. The passivation layer 150 is disposed on the gate insulating layer 130 and covers the second metal layer M2. The pixel electrode layer includes a plurality of sub-pixels 170 arranged in an array, and each sub-pixel 170 includes a main pixel electrode 171 and a sub-pixel electrode 172. In the sub-pixel array, each row of sub-pixels 170 is correspondingly provided with a gate scanning line 120, the gate scanning line 120 is located between a main pixel electrode 171 and a sub-pixel electrode 172, one column of sub-pixels corresponds to a data line 140, the main pixel electrode 171 is electrically connected with the drain electrode of the first thin film transistor T1, and the sub-pixel electrode 172 is electrically connected with the drain electrode of the second thin film transistor T2. The main pixel electrode 171 and the sub pixel electrode 172 correspond to liquid crystal molecules of 4 domains, respectively, to form an 8-domain pixel structure of the sub pixel 170.
Referring to fig. 4, in the present embodiment, the first thin film transistor T1 is a U-type (U-type) thin film transistor, and the second thin film transistor T2 and the third thin film transistor T3 are I-type (I-type) thin film transistors, respectively.
Referring to fig. 5, the first thin film transistor T1 has a gate connected to the gate scan line 120, a source connected to the data line 140, and a drain connected to one end of the main region storage capacitor Cst1 and one end of the main region liquid crystal capacitor Clc1, respectively, the other end of the main region storage capacitor Cst1 is connected to the array common electrode Acom, and the other end of the main region liquid crystal capacitor Clc1 is connected to the CF common electrode CFcom; the gate of the second thin film transistor T2 is connected to the gate scan line 120, the source thereof is connected to the data line 140, the drain thereof is connected to the source of the third thin film transistor T3, the drain of the second thin film transistor T2 is respectively connected to one end of the sub-area storage capacitor Cst2 and one end of the sub-area liquid crystal capacitor Clc2, the other end of the sub-area storage capacitor Cst2 is connected to the array common electrode Acom, and the other end of the sub-area liquid crystal capacitor Clc2 is connected to the CF common electrode CFcom; the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2, the gate of the third thin film transistor T3 is connected to the gate scan line 120, and the drain T3d thereof is electrically connected to the common electrode 121.
The organic layer 160 is further provided with a connection hole 163, the surface of the organic layer 160 is provided with a connection film layer 191, the connection film layer 191 and the pixel electrode layer are arranged on the surface of the organic layer 160 at the same layer, one end of the connection film layer 191 is electrically connected with the drain electrode of the second thin film transistor T2 through the connection hole 163, and the other end of the connection film layer 191 is electrically connected with the sub-pixel electrode 172.
In this embodiment, the gate electrode of the first thin film transistor T1, the gate electrode of the second thin film transistor T2, the gate electrode of the third thin film transistor T3, the gate scan line 120, and the shared common electrode 121 are disposed in the same layer to form the first metal layer M1, and referring to fig. 4a, the shared common electrode 121 and the gate scan line 120 are arranged in parallel at an interval, an orthographic projection of the shared common electrode 121 on the bottom plate 110 is closely located outside an orthographic projection of the subpixel electrode 172 on the bottom plate 110, specifically, the orthographic projection of the shared common electrode 121 on the bottom plate 110 is located between an orthographic projection of the gate scan line 120 on the bottom plate 110 and an orthographic projection of the subpixel electrode 172 on the bottom plate 110, and it can also be seen that the shared common electrode 121 is located in a region between the gate scan line 120 and the array common electrode corresponding to the subpixel electrode 172. The first metal layer M1 is disposed on the bottom plate 110, the gate insulating layer 130 covers the first metal layer M1, and referring to fig. 6, a first opening 131 exposing a portion of the common electrode 121 is formed on the surface of the gate insulating layer 130 near the drain T3d of the third tft T3.
The data line 140, the source and the drain of the first thin film transistor T1, the source and the drain of the second thin film transistor T2, and the source and the drain of the third thin film transistor T3 are disposed in the same layer to form the second metal layer M2, the second metal layer M2 is disposed on the gate insulating layer 130, the organic layer 160 is disposed on the passivation layer 150, and specifically, the color-resist layer 161 of the organic layer 160 is disposed on the passivation layer 150, referring to fig. 6, the surface of the passivation layer 150 is opened with a second opening 151 communicated with the first opening 131, the color-resist layer 161 is opened with a third opening 1611 communicated with the second opening 151, the second opening 151 exposes a sidewall of a drain T3d of the third thin film transistor T3, correspondingly, the third opening 1611 exposes a sidewall of the drain T3d of the third thin film transistor T3, the planarization layer 162 is opened with a fourth opening 1621 communicated with the third opening 1621, the first opening 131, the second opening 151, the third opening 1611 and the fourth opening 1611 are sequentially communicated to form a fourth opening 1621, and an inner diameter of the first opening 1611 is smaller than an inner diameter of the third opening 1621.
A conductive film layer 192 is disposed in the first via hole 181, and the conductive film layer 192 covers the common electrode 121 exposed to the first opening 131 and the drain T3d of the third tft T3 exposed to the third opening 1611 to form an electrical connection between the common electrode 121 and the drain T3d of the third tft T3. Referring to fig. 6, the conductive film 192 covers the common electrode 121 exposed to the first opening 131 and the drain T3d of the third tft T3 exposed to the third opening 1611 through the first via 181, and forms an electrical connection between the common electrode 121 and the drain T3d of the third tft T3, and since the first metal layer M1 where the common electrode 121 is located and the second metal layer M2 where the drain T3d of the third tft T3 is located are disposed in different layers, specifically, the second metal layer M2 is above the first metal layer M1, such a connection is called a deep-shallow hole connection.
The connection film layer 191, the upper end plane of the conductive film layer 192, and the pixel electrode layer are disposed on the surface of the organic layer 160 at the same layer, and the connection film layer 191, the conductive film layer 192, and the pixel electrode layer are formed by patterning an ITO (indium tin oxide) film layer, respectively.
In this embodiment, the shared common electrode 121 is transferred from the second metal layer M2 to the first metal layer M1, and is arranged in parallel with the gate scan line 120 and the array common electrode Acom at an interval, and the shared common electrode 121 is electrically connected to the drain T3d of the third tft T3 through the conductive film 192, so as to prevent the shared common electrode 121 from passing through the display region where the main pixel electrode 171 and the sub-pixel electrode 172 are located, the shared common electrode 121 is electrically connected to the drain T3d of the third tft T3 in the non-display region (between the main pixel electrode 171 and the sub-pixel electrode 172), and the voltage of the sub-pixel electrode 172 is shared (share) to the shared common electrode 121, and the shared common electrode 121 and the sub-pixel electrode 172 are arranged in different layers and in parallel at an interval, specifically, the forward projection of the shared common electrode 121 on the bottom plate 110 is located outside the forward projection of the sub-pixel electrode 172 on the bottom plate 110, so that no capacitance is formed between the shared common electrode 121 and the sub-pixel electrode 172, thereby solving the problem of the lateral crosstalk, and the crosstalk between the non-pixel electrode 121 and the sub-pixel electrode layer 172 does not affect the transmittance of the sub-pixel electrode layer of the display region 171, and the sub-pixel electrode layer 172.
In the manufacturing process of the color resist layer 161 and the planarization layer 162, the color resist layer 161 is opened to form the third opening 1611, since the color resist is organic and is relatively thick, the area required by the third opening 1611 is relatively large, and the opening ratio is still lost, but the opening ratio is still improved compared with the design in which the common electrode 121 is disposed on the second metal layer M2 and longitudinally passes through the display region.
Meanwhile, the invention also provides a liquid crystal display panel 1, referring to fig. 7, the liquid crystal display panel 1 includes the array substrate 100, a color film substrate 200 and a liquid crystal layer 300, the array substrate 100 and the color film substrate 200 are oppositely disposed, the liquid crystal layer 300 is disposed between the array substrate 100 and the color film substrate 200, the color film substrate 200 includes a substrate 210, a black matrix layer 220 disposed on the substrate 210, and a color film electrode layer 230 disposed on the black matrix layer 220, the color film electrode layer 230 is oppositely disposed with respect to the pixel electrode layer, and the color film electrode layer 230 includes a plurality of CF common electrodes CFcom.
In another embodiment of the present invention, referring to fig. 8, the second opening 151 'of the passivation layer 150 opened on the array substrate 100' exposes a portion of the surface of the drain T3d of the third tft T3 (i.e., a portion of the surface of the drain T3d away from the gate insulating layer 130) in addition to the sidewall of the drain T3d of the third tft T3, and correspondingly, the third opening 1611 'opened on the color-resist layer 161 exposes a portion of the surface of the drain T3d of the third tft T3 (i.e., a portion of the surface of the drain T3d away from the gate insulating layer 130) in addition to the sidewall of the drain T3d of the third tft T3, so as to form a stepped structure, thereby increasing the contact area between the conductive film 192 and the drain T3d of the third tft T3, ensuring the stability of the electrical connection between the shared common electrode 121 and the drain T3d of the third tft T3, and ensuring the stable support of the first opening 131, the second opening 151', and the fourth opening 1621 'of the first opening 181' in turn.
In another embodiment of the present invention, referring to fig. 9, 9a and 10, the array substrate 100 ″ includes a bottom plate 110, a first metal layer M1 (not shown), a gate insulating layer 130, a second metal layer M2 (not shown), a passivation layer 150, an organic layer 160 and a pixel electrode layer (not shown) which are stacked. The organic layer 160 includes a color resist layer 161 and a planarization layer 162 which are stacked. The pixel electrode layer includes a plurality of sub-pixels 170 arranged in an array, and each sub-pixel 170 includes a main pixel electrode 171 and a sub-pixel electrode 172. In the sub-pixel array, each row of sub-pixels 170 is correspondingly provided with a gate scanning line 120, the gate scanning line 120 is located between a main pixel electrode 171 and a sub-pixel electrode 172, one column of sub-pixels corresponds to one data line 140, the main pixel electrode 171 is electrically connected with the drain electrode of a first thin film transistor T1, the sub-pixel electrode 172 is electrically connected with the drain electrode of a second thin film transistor T2, the source electrode of a third thin film transistor T3 is electrically connected with the drain electrode of the second thin film transistor T2, and the drain electrode T3d of the third thin film transistor T3 is electrically connected with the shared common electrode 121.
The gate electrode of the first thin film transistor T1, the gate electrode of the second thin film transistor T2, the gate electrode of the third thin film transistor T3, the gate scanning line 120, and the shared common electrode 121 are disposed on the same layer to form the first metal layer M1, the shared common electrode 121, the gate scanning line 120, and the array common electrode Acom are arranged in parallel at intervals, the first metal layer M1 is disposed on the bottom plate 110, and the gate insulating layer 130 covers the first metal layer M1. Referring to fig. 10, a second via hole 182 is formed in a surface of the gate insulating layer 130 corresponding to the drain electrode T3d of the third tft T3, the second via hole 182 exposes a portion of the shared common electrode 121, and the drain electrode T3d of the third tft T3 is electrically connected to the shared common electrode 121 through the second via hole 182.
The specific method is to form the second via hole 182 on the surface of the gate insulating layer 130 by using a photomask, then form the second metal layer M2 on the gate insulating layer 130, electrically connect the drain T3d of the third tft T3 of the second metal layer M2 with the common electrode 121 through the second via hole 182, thereby avoiding opening the color-resist layer 161, and the area required for forming the second via hole 182 by opening the gate insulating layer 130 is much smaller than the area required for opening the color-resist layer 161, so that the pixel electrode aperture ratio is further increased, and the transmittance is further increased.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that various modifications and decorations can be made by those skilled in the art without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. An array substrate, comprising:
a base plate;
a first metal layer disposed on the bottom plate, the first metal layer comprising: the grid scanning line, the array common electrode and the shared common electrode are arranged in parallel at intervals;
the pixel electrode layer and the first metal layer are arranged on the bottom plate in a different layer mode, the pixel electrode layer comprises a plurality of sub-pixel electrodes which are arranged in an array mode, and each sub-pixel electrode comprises a main pixel electrode and a sub-pixel electrode;
a first thin film transistor having a drain electrode electrically connected to the main pixel electrode;
a second thin film transistor, a drain of which is electrically connected to the sub-pixel electrode;
and a source of the third thin film transistor is electrically connected with the drain of the second thin film transistor, and a drain of the third thin film transistor is electrically connected with the shared common electrode.
2. The array substrate of claim 1,
the array substrate further includes:
the grid insulation layer is arranged on the bottom plate and covers the first metal layer;
a second metal layer disposed on the gate insulating layer, the second metal layer including a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and a source and a drain of the third thin film transistor;
the organic layer is arranged on the second metal layer, a first through hole which exposes a part of the shared common electrode and exposes a part of the drain electrode of the third thin film transistor is formed in the surface of the organic layer, and the pixel electrode layer is arranged on the organic layer on the outer side of the first through hole;
and the conductive film layer is deposited on the first via hole, at least covers the shared common electrode and part of the drain electrode of the third thin film transistor, and the drain electrode of the third thin film transistor is electrically connected with the shared common electrode through the conductive film layer.
3. The array substrate of claim 2, wherein the first via is opened on the surface of the organic layer between the main pixel electrode and the sub-pixel electrode.
4. The array substrate of claim 3, wherein an inner diameter of the first via hole near a side of the shared common electrode is smaller than an inner diameter of the first via hole near a side of the organic layer.
5. The array substrate of claim 4, wherein the first via exposes a sidewall of the drain of the third thin film transistor.
6. The array substrate of claim 5, wherein the first via exposes a sidewall of the drain electrode of the third thin film transistor and a portion of a surface of the drain electrode facing away from the shared common electrode.
7. The array substrate of claim 1,
the array substrate further includes:
the grid insulating layer is arranged on the bottom plate and covers the first metal layer;
a second through hole for exposing part of the shared common electrode is formed in the surface of the grid electrode insulating layer;
the drain of the third thin film transistor is electrically connected to the shared common electrode through the second via hole.
8. The array substrate of claim 1, wherein the shared common electrode is located between the gate scan line and the array common electrode corresponding to the sub-pixel electrode.
9. A liquid crystal display panel, comprising:
the array substrate according to any one of claims 1 to 8;
the color film substrate is arranged opposite to the array substrate;
and the liquid crystal layer is arranged between the array substrate and the color film substrate.
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| CN202111560939.XA CN114236925B (en) | 2021-12-14 | 2021-12-14 | Array substrate and liquid crystal display panel |
| PCT/CN2021/140612 WO2023108771A1 (en) | 2021-12-14 | 2021-12-22 | Array substrate and liquid crystal display panel |
| US17/623,023 US20240045289A1 (en) | 2021-12-14 | 2021-12-22 | Array substrate and liquid crystal display panel |
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| CN202111560939.XA CN114236925B (en) | 2021-12-14 | 2021-12-14 | Array substrate and liquid crystal display panel |
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| CN114236925B true CN114236925B (en) | 2023-02-28 |
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| CN114755865A (en) * | 2022-04-19 | 2022-07-15 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN117795412A (en) * | 2022-07-29 | 2024-03-29 | 京东方科技集团股份有限公司 | Display substrate and display device |
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| CN1580913A (en) * | 2004-05-14 | 2005-02-16 | 友达光电股份有限公司 | Thin film transistor array base board |
| KR101659831B1 (en) * | 2010-04-22 | 2016-09-27 | 삼성디스플레이 주식회사 | Liquid crystal display, method of driving the same, and method of manufacturing the same |
| CN105093740B (en) * | 2015-08-04 | 2018-07-17 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and its liquid crystal display device |
| CN105807520A (en) * | 2016-05-20 | 2016-07-27 | 深圳市华星光电技术有限公司 | 3t pixel structure and liquid crystal display device |
| CN106773408A (en) * | 2016-12-29 | 2017-05-31 | 深圳市华星光电技术有限公司 | Dot structure and liquid crystal display panel |
| CN106950768B (en) * | 2017-03-03 | 2019-12-24 | 深圳市华星光电技术有限公司 | Pixel unit and driving method thereof |
| US10541255B2 (en) * | 2017-04-05 | 2020-01-21 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate having sub-pixels including main region pixel electrode and secondary region pixel electrode that have branch electrodes and slits having different widths |
| CN106842750B (en) * | 2017-04-05 | 2018-11-23 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display pixel driving circuit and TFT substrate |
| CN107065350B (en) * | 2017-04-10 | 2019-10-25 | 深圳市华星光电半导体显示技术有限公司 | Eight farmland 3T dot structures |
| CN110109296A (en) * | 2019-04-12 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and liquid crystal display device |
| CN111176041A (en) * | 2020-02-21 | 2020-05-19 | Tcl华星光电技术有限公司 | Pixel structure and pixel circuit |
| CN112068371A (en) * | 2020-09-10 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN112631030B (en) * | 2020-12-03 | 2022-04-01 | Tcl华星光电技术有限公司 | Array substrate and method for measuring capacitance of array substrate |
| CN113176691B (en) * | 2021-04-02 | 2023-12-08 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN113311624A (en) * | 2021-04-06 | 2021-08-27 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN113314546B (en) * | 2021-05-21 | 2023-06-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, array substrate testing method and display panel |
| CN113741109A (en) * | 2021-09-08 | 2021-12-03 | Tcl华星光电技术有限公司 | Array substrate and display panel |
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- 2021-12-22 WO PCT/CN2021/140612 patent/WO2023108771A1/en active Application Filing
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| CN114236925A (en) | 2022-03-25 |
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