CN114221666A - Multi-mode time sequence control and intermediate frequency modulation signal generating device - Google Patents
Multi-mode time sequence control and intermediate frequency modulation signal generating device Download PDFInfo
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
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- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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Abstract
The invention discloses a multi-mode time sequence control and intermediate frequency modulation signal generating device, which comprises: the device comprises an interface driving circuit, a digital processor, a time sequence driving circuit and a four-channel digital intermediate frequency comprehensive circuit, wherein the interface driving circuit is used for receiving standard asynchronous serial data sent from the outside; the digital processor is used for decoding the standard asynchronous serial data, acquiring a digitalized operating instruction and configuration parameters, generating a multi-mode time sequence control signal according to the digitalized operating instruction and the configuration parameters, and configuring the four-channel digital intermediate frequency integrated circuit; the time sequence driving circuit is used for driving the multi-mode time sequence control signal; and the four-channel digital intermediate frequency synthesis circuit is used for generating four-channel intermediate frequency modulation signals through the serial configuration of the digital processor. The invention can generate multi-airspace, multi-mode and multi-state receiving and transmitting time sequence and modulation waveform, thereby effectively reducing the development period and verification cost of the short-range detector and improving the expandability and maintainability of the system.
Description
Technical Field
The invention relates to the technical field of radio detectors, in particular to a multi-mode time sequence control and intermediate frequency modulation signal generation device.
Background
The traditional proximity detector is usually designed for a single detector of a specific transceiver system, and is mainly based on certain solidified hardware, so that hardware must be redesigned to expand new functions and modes of the detector, and the design is often complex, needs a lot of manpower, material resources and development cost, and has a long development period.
In the related technology, a reconfigurable configurable radio detection mode is provided, namely a software radio idea is applied to the design of a short-range detector, a reconfigurable short-range detector hardware platform with high universality is constructed, and a time sequence control and intermediate frequency modulation signal required by the short-range detector is formed by a software configurable means, so that the traditional design idea facing a single function mode is eliminated, and the multi-mode transceiving requirement can be met only by parameter digital configuration without changing system hardware, thereby accelerating the system performance verification and shortening the research and development period.
The short-range detector designed by utilizing the software radio idea can effectively improve the reconfigurable performance of the system, but is limited by the limitation of the hardware level, and the detection mode of the reconfigurable configurable transceiving system is not mature. The reconfigurable configurable radio proximity detector adopts hardware configurable parameter design as much as possible, and realizes the functions realized by an analog circuit and a digital circuit used by the traditional proximity detector in a digital reconfiguration mode, thereby effectively improving the universality, the maintainability and the reliability of the system.
A typical reconfigurable configurable radio proximity detector is composed of a radio frequency antenna, a transceiver unit, a signal processor, and an actuator. The rapid development of reconfigurable configurable radio technology, especially the continuous improvement of chip technology, provides the possibility for further development of proximity detectors. From the technical development trend of the short-range detector, the ratio of software/hardware in the system is increasing day by day, most of the currently known short-range detectors involve the requirements of complex parameter modulation and transmission, multi-parameter demodulation of echo signals, multi-mode time sequence and the like, the hardware state of the transceiving system is multiple, the modes are complex, a large amount of analog signal processing is needed, the transceiving channelized design is complex, and the reconfigurable configurable transceiving system becomes one of the key technologies for improving the performance of the short-range detector.
Therefore, how to implement a reconfigurable, configurable, flexible-design, and multi-mode timing control and transceiving signal generating device is a problem that needs to be solved urgently.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a multi-mode timing control and intermediate frequency modulation signal generating apparatus to generate multi-spatial domain, multi-mode, multi-state transceiving timing and modulation waveforms, so as to effectively reduce the development period and verification cost of a proximity detector and improve the scalability and maintainability of a system.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a multi-mode timing control and IF modulation signal generating apparatus, comprising: the interface driving circuit 10 is used for receiving and converting standard asynchronous serial communication data sent by an external control system; the digital processor 20 is connected with the interface driving circuit 10, and the digital processor 20 is configured to receive the standard asynchronous serial communication data input by the interface driving circuit 10, decode and convert the standard asynchronous serial communication data according to a protocol, acquire a digitalized operating instruction and configuration parameters, and output self operating state parameters through the interface driving circuit 10; generating a multi-mode time sequence control signal according to the digitalized working instruction and the configuration parameters, and configuring the four-channel digital intermediate frequency integrated circuit 40 in a synchronous serial port mode to control the four-channel digital intermediate frequency integrated circuit 40 to generate four-channel configurable intermediate frequency modulation signals with configurable parameters including but not limited to frequency, phase, pulse width, period and bandwidth; a timing driving circuit 30 connected to the digital processor 20, wherein the timing driving circuit 30 is configured to perform voltage driving and level conversion on the TTL level signal output by the digital processor 20; the four-channel digital intermediate frequency synthesis circuit 40 is connected to the digital processor 20, and the four-channel digital intermediate frequency synthesis circuit 40 is configured to receive the serial configuration instruction and the configuration parameters output by the digital processor 20 and generate a four-channel configurable intermediate frequency modulation signal.
Optionally, the digital processor 20 includes: the interface communication module 21 is connected with the interface driving circuit 10, and the interface communication module 21 is configured to receive the standard asynchronous serial communication data, decode and convert the standard asynchronous serial communication data according to a protocol, and then obtain the digitized working instruction and the configuration parameters; the information management module 22 is connected with the interface communication module 21, and the information management module 22 is used for providing a clock for an internal module of the digital processor 20 and managing information parameters input by the interface communication module 21 and the working states of other software modules in the digital processor 20; the time sequence control module 23 is connected with the information management module 22, and the time sequence control module 23 is configured to receive the digitized operation instruction and the configuration parameter, and generate a multi-mode time sequence control signal according to the digitized operation instruction and the configuration parameter; and the digital intermediate frequency configuration module 24 is connected to the information management module 22, and the digital intermediate frequency configuration module 24 is configured to receive the digitalized operating instruction and the configuration parameters, and perform serial configuration on the direct digital frequency synthesizer 41 according to the digitalized operating instruction and the configuration parameters, so that the four-channel digital intermediate frequency synthesizer 40 generates the four-channel configurable intermediate frequency modulation signal.
Optionally, the four-channel digital intermediate frequency synthesizing circuit 40 includes: the direct digital frequency synthesizer 41 is connected to the digital intermediate frequency configuration module 24, and the direct digital frequency synthesizer 41 generates the four-channel configurable intermediate frequency modulation signal by serially configuring a register and a control timing sequence through the digital intermediate frequency configuration module 24; a filter 42 connected to the direct digital frequency synthesizer 41, wherein the filter 42 is configured to filter the four-channel configurable if modulated signal; and an amplifier 43 connected to the filter 42, where the amplifier 43 is configured to perform signal amplification processing on the four-channel configurable intermediate frequency modulated signal after filtering processing.
Optionally, the apparatus further comprises: the power circuit 50 is used for stabilizing the voltage of external input voltage through the low dropout regulator and supplying power to the multimode sequential control and intermediate frequency modulation signal generating device; a clock circuit 60, connected to the information management module 22 and the four-channel digital intermediate frequency synthesis circuit 40, respectively, where the clock circuit 60 is configured to provide a clock signal to a digital clock manager of the information management module 22 and provide a reference clock signal to the direct digital frequency synthesizer 41; wherein, the information management module 22 provides corresponding clock signals to other functional modules through the digital clock manager.
Optionally, the standard asynchronous serial communication data decoded by the interface communication module 21 includes: at least one of a transmitting switch state, a power amplifier switch state, a receiving switch state, a self-checking control parameter, a gain control parameter, a video switch state, a height switch state, a short-distance switch state, a sampling clock, a sampling synchronous parameter, a target airspace, a ground/sea mode, a working state, a modulation frequency, a modulation amplitude and a modulation phase parameter.
Optionally, the interface communication module 21 is specifically configured to: and receiving the standard asynchronous serial communication data converted by the interface driving circuit 10, and performing frame header, frame tail, checksum verification and decoding on the standard asynchronous serial communication data according to a protocol to acquire the digital work instruction and the configuration parameters.
Optionally, the information management module 22 is specifically configured to: providing a working clock of the interface communication module 21, and managing instructions and parameters transmitted by the interface communication module 21; managing the operating states of other software modules within the digital processor 20; sending a timing control module reference clock signal to the timing control module 23; a parameter configuration clock signal is provided to the digital intermediate frequency configuration module 24.
Optionally, the timing control module 23 is specifically configured to: generating a multi-mode time sequence control signal under at least one parameter of a target airspace, a working mode and a working state according to the digital working instruction and the configuration parameters; the target airspace comprises a high-altitude airspace, a low-altitude airspace and a low-altitude airspace, the working mode comprises a ground mode and a sea mode, and the working state comprises a self-checking state, a calibration state and a normal state.
Optionally, the digital intermediate frequency configuration module 24 is further configured to: the method comprises the steps of supporting a parameter-configurable dot frequency signal, a frequency modulation signal, a frequency hopping signal, a phase modulation signal and supporting the output of at least one waveform signal.
Optionally, the four-channel digital intermediate frequency synthesis circuit 40 is specifically configured to: and generating two paths of intermediate frequency modulation transmitting signals with configurable frequency, phase and pulse width parameters and two paths of intermediate frequency modulation receiving and demodulating signals with configurable frequency, phase and pulse width parameters.
The invention has at least the following technical effects:
(1) by adopting the reconfigurable and configurable thought of software radio, the digital reconfigurable configuration of the receiving and transmitting time sequence and the intermediate frequency modulation parameter based on the working instruction is realized according to the digital working instruction and the configuration parameter;
(2) the method supports application scenes of multiple airspaces, multiple modes, multiple states and the like, can generate intermediate frequency signals with complex parameters such as four paths of dot frequency, frequency modulation, frequency hopping, phase modulation, pulse width and the like, can be synchronously controlled with a time sequence signal, and realizes configurable work of a complex transceiving system;
(3) through a modularized and generalized design method, the maintainability and the expandability of the device are improved, the development cost is effectively reduced, the development period is shortened, and the application value is higher.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a block diagram of a multi-mode timing control and if modulation signal generating apparatus according to a first embodiment of the present invention;
fig. 2 is a block diagram of a multi-mode timing control and if modulation signal generating apparatus according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of an asynchronous serial data verification process according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating an external connection of an information management module according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating a timing control and if signal modulation operation according to an embodiment of the present invention;
fig. 6 is a block diagram of a multi-mode timing control and if modulation signal generating device according to a third embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The following describes the multimode timing control and if modulation signal generating apparatus of the present embodiment with reference to the drawings.
Fig. 1 is a block diagram of a multi-mode timing control and if modulation signal generating apparatus according to a first embodiment of the present invention. As shown in fig. 1, the apparatus 1 includes an interface driving circuit 10, a digital processor 20, a timing driving circuit 30, and a four-channel digital intermediate frequency synthesizing circuit 40.
The interface driving circuit 10 is configured to receive and convert standard asynchronous communication data sent by an external control system to form an asynchronous serial TTL level signal; the digital processor 20 is connected with the interface driving circuit 10, the digital processor 20 is configured to receive the standard asynchronous serial communication data input by the interface driving circuit 10, decode and convert the standard asynchronous serial communication data according to a protocol, acquire a digitalized operating instruction and configuration parameters, and output self operating state parameters through the interface driving circuit 10; generating a multi-mode time sequence control signal according to the digitalized working instruction and the configuration parameters, and configuring the four-channel digital intermediate frequency integrated circuit 40 in a synchronous serial port mode to control the four-channel digital intermediate frequency integrated circuit 40 to generate four-channel configurable intermediate frequency modulation signals with configurable parameters including but not limited to frequency, phase, pulse width, period and bandwidth; the timing driving circuit 30 is connected to the digital processor 20, and the timing driving circuit 30 is configured to perform voltage driving and level conversion on the TTL level signal output by the digital processor 20; the four-channel digital intermediate frequency synthesis circuit 40 is connected to the digital processor 20, and the four-channel digital intermediate frequency synthesis circuit 40 is configured to receive the serial configuration command and the configuration parameters output by the digital processor 20 and generate a four-channel configurable intermediate frequency modulation signal.
Specifically, the interface driving circuit 10 may be used for communication between the external control system and the device, so as to implement level conversion of a standard asynchronous serial signal sent by the external control system, and send the converted level signal to the digital processor 20. The digital processor 20 may receive the standard asynchronous serial signal after the interface level conversion, decode the standard asynchronous serial signal to obtain a digital operation instruction and configuration parameters including a timing signal and modulation parameters, generate a multi-mode timing control signal according to the digital operation instruction and configuration parameters, transmit the multi-mode timing control signal to the timing driving circuit 30, implement the timing signal level conversion through the timing driving circuit 30, and perform the parameter serial configuration on the four-channel digital intermediate frequency synthesis circuit 40 to generate a four-channel intermediate frequency modulation signal.
Fig. 2 is a block diagram of a multi-mode timing control and if modulation signal generating apparatus according to a second embodiment of the present invention. As shown in fig. 2, the digital processor 20 includes an interface communication module 21, an information management module 22, a timing control module 23, and a digital if configuration module 24. The digital processor 20 may adopt a software modular design and a Programmable technology, such as a high performance Programmable Gate Array (FPGA), and the processing modules in the device may be implemented in the digital processor 20.
In this embodiment, the interface communication module 21 is connected to the interface driving circuit 10, and the interface communication module 21 is configured to receive standard asynchronous serial communication data, decode and convert the standard asynchronous serial communication data according to a protocol, and then obtain a digitalized operation instruction and configuration parameters; the information management module 22 is connected with the interface communication module 21, and the information management module 22 is used for providing a clock for an internal module of the digital processor 20, and managing information parameters input by the interface communication module 21 and the working states of other software modules in the digital processor 20; the time sequence control module 23 is connected with the information management module 22, and the time sequence control module 23 is used for receiving the digital working instruction and the configuration parameter and generating a multi-mode time sequence control signal according to the digital working instruction and the configuration parameter; the digital intermediate frequency configuration module 24 is connected to the information management module 22, and the digital intermediate frequency configuration module 24 is configured to receive the digital work instruction and the configuration parameter, and perform serial configuration on the direct digital frequency synthesizer 41 according to the digital work instruction and the configuration parameter, so that the four-channel digital intermediate frequency synthesizer 40 generates a four-channel configurable intermediate frequency modulation signal.
Preferably, the interface driving circuit 10 completes the conversion of the communication level through the RS-422 bus, and the interface communication module 21 receives the converted standard asynchronous serial signal and decodes the standard asynchronous serial signal according to a protocol to obtain the digital work instruction and the configuration parameter. The standard asynchronous serial communication data decoded by the interface communication module 21 includes: at least one of a transmitting switch state, a power amplifier switch state, a receiving switch state, a self-checking control parameter, a gain control parameter, a video switch state, a height switch state, a short-distance switch state, a sampling clock, a sampling synchronous parameter, a target airspace, a ground/sea mode, a working state, a modulation frequency, a modulation amplitude and a modulation phase parameter.
It should be noted that the interface communication module 21 may be further specifically configured to: the standard asynchronous serial communication data converted by the interface driving circuit 10 is received, and the frame header, the frame tail, the checksum verification and the decoding are performed on the standard asynchronous serial communication data according to the protocol, so as to obtain the digital working instruction and the configuration parameters.
Specifically, as shown in fig. 3, the data start bit may be determined first, after the start bit is determined to be error-free, the 8-bit data bit and the 1-bit check bit are received, and finally the parity check is performed on the check bit. When the check is correct, 8-bit received data and a data valid flag are output, and then the receiving register is reset after the stop bit is received. If the received data is valid, the received data is stored in a Random Access Memory (RAM) and address accumulation judgment is performed. When the address is 0 or 1, performing frame header verification; when the address is a preset address N-3 or N-2, accumulating and checking; and when the address is the preset address N-1 or N, performing frame end check. And when all the checks are correct, the data receiving is finished. And when the address is other values, accumulating and judging the data bytes. And after the data reception is finished, sequentially reading the data from the RAM, decoding the data protocol, and waiting for the next reception initialization after the decoding is finished. Through the receiving and checking processing, the correctness of the received data can be effectively ensured, and the stability of system communication is improved.
In one embodiment of the present invention, information management module 22 may implement digital management and logic processing of the clocks of the functional modules. The information management module 22 is specifically configured to: providing a working clock of the interface communication module 21 and managing instructions and parameters transmitted by the interface communication module 21; managing the operating states of other software modules within the digital processor 20; sending a timing control module reference clock signal to the timing control module 23; the parameter configuration clock signal is provided to the digital intermediate frequency configuration module 24.
Specifically, as shown in fig. 4, the information management module 22 may provide various signals to the outside, including: the working clock signal provided externally, and the digital configuration parameter signal provided externally. As an example, the information management module 22 may send respective working clocks to the interface communication module 21, the timing control module 23, and the digital intermediate frequency configuration module 24 (lines sent to the interface communication module 21 are not shown), may receive standard asynchronous serial communication data transmitted by the interface communication module 21, that is, digitalized working instructions and configuration parameters, and then may send the digitalized working instructions and configuration parameters to the timing control module 23 and the digital intermediate frequency configuration module 24, where the digitalized working instructions and configuration parameters include working instructions, timing signals, and intermediate frequency configuration parameters.
In an embodiment of the present invention, the timing control module 23 is specifically configured to: generating a multi-mode time sequence control signal under at least one parameter of a target airspace, a working mode and a working state according to the digital working instruction and the configuration parameters; the target airspace comprises a high-altitude airspace, a low-altitude airspace and a super-low airspace, the working mode comprises a ground mode and a sea mode, and the working state comprises a self-checking state, a calibration state and a normal state.
Specifically, the timing control module 23 can generate multi-spatial domain, multi-mode and multi-state timing control signals according to the digitalized operating instructions and configuration parameters, and transmit the signals to the timing driving circuit 30, so that the timing driving circuit 30 drives the multi-spatial domain, multi-mode and multi-state timing control signals generated by the timing control module 23 to generate multi-mode timing signals.
In this embodiment, the digital intermediate frequency configuration module 24 may configure the direct digital frequency synthesizer 41 according to the digitalized operating instruction and the configuration parameter, so that the four-channel digital intermediate frequency synthesizer 40 generates the four-channel configurable intermediate frequency modulation signal.
It should be noted that the four-channel digital intermediate frequency synthesizing circuit 40 includes: the direct digital frequency synthesizer 41, the filter 42 and the amplifier 43. The direct digital frequency synthesizer 41 is connected with the digital intermediate frequency configuration module 24, and the direct digital frequency synthesizer 41 serially configures a register and a control time sequence through the digital intermediate frequency configuration module 24 to generate a four-channel configurable intermediate frequency modulation signal; the filter 42 is connected with the direct digital frequency synthesizer 41, and the filter 42 is used for filtering the four-channel configurable intermediate frequency modulation signal; the amplifier 43 is connected to the filter 42, and the amplifier 43 is configured to perform signal amplification processing on the filtered four-channel configurable intermediate frequency modulation signal.
Specifically, the digital intermediate frequency configuration module 24 may read a random code stored in an on-chip memory of the processor according to the digital configuration parameters, and configure a direct digital frequency synthesizer register in the four-channel digital intermediate frequency integrated circuit 40 in combination with parameters such as a frequency word and an amplitude word, to generate two channels of intermediate frequency modulation signals and two channels of received and demodulated intermediate frequency modulation signals, and then output the signals after passing through the filter 42 and the amplifier 43, thereby completing the intermediate frequency digital configuration. In this embodiment, the direct digital frequency synthesizer 41 can be an AD9959 direct digital frequency synthesizing chip from adeno corporation, which can support outputting four intermediate frequency modulation signals at most.
As an example, as shown in fig. 5, the target airspace, the working mode and the working state may be determined, if it is determined to be in the normal state, under the driving of the frequency division clock, the information management module 22 sends out a configuration parameter 1 and an output timing sequence a in the corresponding state, the timing control module 23 in the configuration module may generate a corresponding timing control signal according to the configuration parameter 1 and the output timing sequence a, the digital intermediate frequency configuration module 24 reads the configuration parameter according to the configuration parameter 1 and generates a control code, and configures a direct digital frequency synthesis register in the four-channel digital intermediate frequency synthesis circuit 40 to generate two intermediate frequency modulation signals synchronized with the output timing sequence a and two received and demodulated intermediate frequency modulation signals, that is, four-channel configurable intermediate frequency modulation signals.
It should be noted that the digital intermediate frequency configuration module 24 in this embodiment may also support outputting other complex waveform signals, such as a dot frequency signal, a frequency modulation signal, a frequency hopping signal, a phase modulation signal, and a pulse width signal, which may be configured with parameters, and may output at least one waveform signal of the foregoing modulation signals.
As shown in fig. 6, the apparatus 1 further includes: a power supply circuit 50 and a clock circuit 60. The power supply circuit 50 is used for stabilizing the external input voltage through the low-dropout linear regulator and supplying power to the device; the clock circuit 60 is connected to the information management module 22 and the four-channel digital intermediate frequency synthesis circuit 40, respectively, and the clock circuit 60 is configured to provide a high-precision low-jitter clock signal to the digital clock manager of the information management module 22 and provide a high-precision low-jitter reference clock signal to the direct digital frequency synthesizer 41; wherein, the information management module 22 provides corresponding clock signals to other functional modules through the digital clock manager.
In summary, the multi-mode timing control and intermediate frequency modulation signal generating apparatus of this embodiment adopts a design concept that software radio is reconfigurable and configurable, has the characteristics of strong versatility, digitally configurable parameters, and the like, can implement digital online configuration of timing and modulation parameters, and support application scenarios such as multi-airspace, multi-mode, multi-state, and the like, can generate complex intermediate frequency signals such as four-way dot frequency, frequency modulation, frequency hopping, phase modulation, and the like, is convenient for system function verification, and can implement phase, frequency, pulse width random coding and parametric modulation on the output intermediate frequency signal, and synchronize with the timing signal, so as to meet the use requirements of a transceiver system. In addition, the invention improves the maintainability and expandability of the device, effectively reduces the development cost, shortens the development period and has higher application value through a modularized and generalized design method.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (10)
1. A multi-mode timing control and IF modulation signal generating apparatus, comprising:
the interface driving circuit (10) is used for receiving and converting standard asynchronous serial communication data sent by an external control system;
the digital processor (20) is connected with the interface driving circuit (10), and the digital processor (20) is used for receiving the standard asynchronous serial communication data input by the interface driving circuit (10), decoding and converting the standard asynchronous serial communication data according to a protocol, acquiring a digital working instruction and configuration parameters, and outputting self working state parameters through the interface driving circuit (10); generating a multi-mode time sequence control signal according to the digitalized working instruction and the configuration parameters, and configuring a four-channel digital intermediate frequency integrated circuit (40) in a synchronous serial port mode to control the four-channel digital intermediate frequency integrated circuit (40) to generate four-channel configurable intermediate frequency modulation signals with configurable parameters including but not limited to frequency, phase, pulse width, period and bandwidth;
the timing driving circuit (30) is connected with the digital processor (20), and the timing driving circuit (30) is used for carrying out voltage driving and level conversion on the TTL level signal output by the digital processor (20);
the four-channel digital intermediate frequency synthesis circuit (40) is connected with the digital processor (20), and the four-channel digital intermediate frequency synthesis circuit (40) is used for receiving serial configuration instructions and configuration parameters output by the digital processor (20) and generating four-channel configurable intermediate frequency modulation signals.
2. The multi-mode timing control and if modulated signal generating apparatus of claim 1, wherein said digital processor (20) comprises:
the interface communication module (21) is connected with the interface driving circuit (10), and the interface communication module (21) is used for receiving the standard asynchronous serial communication data, decoding and converting the standard asynchronous serial communication data according to a protocol, and then acquiring the digitalized working instruction and the configuration parameters;
the information management module (22) is connected with the interface communication module (21), and the information management module (22) is used for providing a module clock inside the digital processor (20) and managing information parameters input by the interface communication module (21) and the working states of other software modules inside the digital processor (20);
the time sequence control module (23) is connected with the information management module (22), and the time sequence control module (23) is used for receiving the digital working instruction and the configuration parameters and generating a multi-mode time sequence control signal according to the digital working instruction and the configuration parameters;
the digital intermediate frequency configuration module (24) is connected with the information management module (22), and the digital intermediate frequency configuration module (24) is used for receiving the digital work instruction and the configuration parameters and carrying out serial configuration on the direct digital frequency synthesizer (41) according to the digital work instruction and the configuration parameters so as to enable the four-channel digital intermediate frequency synthesis circuit (40) to generate the four-channel configurable intermediate frequency modulation signal.
3. The multi-mode timing control and if modulated signal generating apparatus of claim 2, wherein said four-channel digital if synthesizing circuit (40) comprises:
the direct digital frequency synthesizer (41) is connected with the digital intermediate frequency configuration module (24), and the direct digital frequency synthesizer (41) generates the four-channel configurable intermediate frequency modulation signal through a serial configuration register and a control time sequence of the digital intermediate frequency configuration module (24);
a filter (42) connected to the direct digital frequency synthesizer (41), the filter (42) being configured to filter the four-channel configurable if modulated signal;
and the amplifier (43) is connected with the filter (42), and the amplifier (43) is used for performing signal amplification processing on the four-channel configurable intermediate frequency modulation signals after filtering processing.
4. The multi-mode timing control and if modulated signal generating apparatus of claim 3, further comprising:
the power supply circuit (50) is used for stabilizing the voltage of external input voltage through the low-dropout linear voltage stabilizer and supplying power to the multi-mode time sequence control and intermediate frequency modulation signal generation device;
the clock circuit (60) is respectively connected with the information management module (22) and the four-channel digital intermediate frequency synthesis circuit (40), and the clock circuit (60) is used for providing a clock signal for a digital clock manager of the information management module (22) and providing a reference clock signal for the direct digital frequency synthesizer (41); wherein the information management module (22) provides corresponding clock signals to other functional modules through the digital clock manager.
5. The multi-mode timing control and if modulated signal generating apparatus as claimed in claim 2, wherein said interface communication module (21) decodes said standard asynchronous serial communication data, comprising: at least one of a transmitting switch state, a power amplifier switch state, a receiving switch state, a self-checking control parameter, a gain control parameter, a video switch state, a height switch state, a short-distance switch state, a sampling clock, a sampling synchronous parameter, a target airspace, a ground/sea mode, a working state, a modulation frequency, a modulation amplitude and a modulation phase parameter.
6. The multi-mode timing control and if modulated signal generating apparatus of claim 2, wherein the interface communication module (21) is specifically configured to: and receiving the standard asynchronous serial communication data converted by the interface driving circuit (10), and performing frame head, frame tail, check sum check and decoding on the standard asynchronous serial communication data according to a protocol to acquire the digital work instruction and the configuration parameters.
7. The multi-mode timing control and if modulated signal generating device of claim 2, wherein the information management module (22) is specifically configured to: providing a working clock of the interface communication module (21), and managing instructions and parameters transmitted by the interface communication module (21); managing the operating state of other software modules within the digital processor (20); -sending a timing control module reference clock signal to the timing control module (23); -providing a parameter configuration clock signal to the digital intermediate frequency configuration module (24).
8. The multi-mode timing control and if modulated signal generating apparatus of claim 2, wherein the timing control module (23) is specifically configured to: generating a multi-mode time sequence control signal under at least one parameter of a target airspace, a working mode and a working state according to the digital working instruction and the configuration parameters; the target airspace comprises a high-altitude airspace, a low-altitude airspace and a low-altitude airspace, the working mode comprises a ground mode and a sea mode, and the working state comprises a self-checking state, a calibration state and a normal state.
9. The multi-mode timing control and if modulated signal generating apparatus of claim 2, wherein the digital if configuration module (24) is further configured to: the method comprises the steps of supporting a parameter-configurable dot frequency signal, a frequency modulation signal, a frequency hopping signal, a phase modulation signal and supporting the output of at least one waveform signal.
10. The multi-mode timing control and if modulated signal generating apparatus as claimed in any of claims 1-9, wherein said four-channel digital if synthesis circuit (40) is specifically configured to: and generating two paths of intermediate frequency modulation transmitting signals with configurable frequency, phase and pulse width parameters and two paths of intermediate frequency modulation receiving and demodulating signals with configurable frequency, phase and pulse width parameters.
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