CN113162625B - Successive approximation analog-to-digital converter based on charge injection compensation - Google Patents

Successive approximation analog-to-digital converter based on charge injection compensation Download PDF

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CN113162625B
CN113162625B CN202110396528.5A CN202110396528A CN113162625B CN 113162625 B CN113162625 B CN 113162625B CN 202110396528 A CN202110396528 A CN 202110396528A CN 113162625 B CN113162625 B CN 113162625B
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switch
charge injection
cal
array
configuration
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CN113162625A (en
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曹骁飞
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3Peak Inc
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3Peak Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

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Abstract

The invention discloses a successive approximation analog-to-digital converter based on charge injection compensation, which comprises: the comparator comprises a first input end, a second input end and an output end, and a bottom plate switch is arranged between the first input end and the second input end; the sampling and holding unit comprises a first capacitor array connected with a first input end of the comparator and a first switch array connected with the first capacitor array; the charge compensation unit comprises a second capacitor array connected with the first input end of the comparator and a second switch array connected with the second capacitor array, and is used for offsetting charge injection of the bottom plate switch; and the control logic unit is used for generating a first control logic for controlling the first switch array and a second control logic for controlling the second switch array according to a successive approximation control algorithm. The invention adds a charge compensation unit on the basis of the existing SAR ADC, and can compensate the charge injection introduced by a bottom plate switch under any switch configuration.

Description

Successive approximation analog-to-digital converter based on charge injection compensation
Technical Field
The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a successive approximation analog-to-digital converter based on charge injection compensation.
Background
A basic successive approximation analog-to-digital converter (SAR ADC) is shown in fig. 1. The device performs the conversion on command, and in order to process the ac signal, the SAR ADC must have an input Sample and Hold (SHA) function to achieve a hold of the signal during the conversion period.
During the transition period, the sample-and-hold (SHA) circuit is placed in hold mode, while the internal DAC is set to an intermediate level. The comparator determines whether the SHA output is greater or less than the DAC output and stores the result (bit 1, most significant bit of conversion) in a Successive Approximation Register (SAR). The DAC is then set to the ¼ range or the microband (depending on the value of bit 1) and the comparator determines bit 2 of the conversion, the result being likewise stored in the register, and the process continues until the values of all bits are determined. After all bits have been set, tested and reset as required, the contents of the SAR are converted to completion, corresponding to the value of the analog input. These bit "tests" form the basis of a serial output version of a SAR-type ADC.
In the prior art, a bottom plate switch is generally connected between two input ends of a Comparator (COMP), and switching between a sampling phase and a conversion phase is realized by turning on or off the bottom plate switch.
However, in high precision analog to digital converters, the nonlinearity introduced by the bottom plate switch injection is often not negligible, and then it is difficult to predict and compensate because the amount of error introduced by the switch injection is related to many factors such as the size of the switch, the equivalent impedance across the switch, process parameters, and manufacturing mismatch.
Therefore, in view of the above technical problems, it is desirable to provide a successive approximation analog-to-digital converter based on charge injection compensation.
Disclosure of Invention
The invention aims to provide a successive approximation analog-to-digital converter based on charge injection compensation so as to compensate charge injection of a bottom plate switch.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a successive approximation analog-to-digital converter based on charge injection compensation, the analog-to-digital converter comprising:
the comparator comprises a first input end, a second input end and an output end, and a bottom plate switch S is arranged between the first input end and the second input end w_bottom ；
A sample-hold unit including a first capacitor array connected to the first input terminal of the comparator and a first switch array connected to the first capacitor array for controlling the capacitors in the first capacitor array and the input voltage signal V IN Or a reference voltage high level V REFP Or the reference voltage is low level V REFN Connecting;
a charge compensation unit including a second capacitor array connected with the first input terminal of the comparator and a second switch array connected with the second capacitor array for controlling the capacitors in the second capacitor array and the high level V of the reference voltage REFP Or the reference voltage is low level V REFN Connected, the charge compensation unit is used for offsetting the bottom plate switch S w_bottom Charge injection of (3);
and the control logic unit is used for generating a first control logic for controlling the first switch array and a second control logic for controlling the second switch array according to a successive approximation control algorithm.
In one embodiment, the first capacitor array includes Nbit _ main first capacitors, and the capacitance value of the first capacitors is C =2 Nbit_main-1 C u Nbit _ main is more than or equal to 2; the first switch array comprises Nbit _ main first switches, Nbit _ main second switches and Nbit _ main third switches, and the first switches are electrically connected with the input powerPressure signal V IN A second switch electrically connected to the reference voltage and the first capacitor REFP A third switch electrically connected to the reference voltage at a low level V REFN And the first capacitor.
In an embodiment, the second capacitor array includes Nbit _ cal second capacitors, and the capacitance value of the second capacitors is C =2 Nbit_cal-1 C u_cal Nbit _ cal is more than or equal to 2; the second switch array comprises Nbit _ cal fourth switches and Nbit _ cal fifth switches, and the fourth switches are electrically connected with the reference voltage high level V REFP A fifth switch electrically connected to the reference voltage at a low level V REFN And a second capacitor.
In one embodiment, the analog-to-digital converter comprises:
in the foreground calibration mode, a target calibration configuration is obtained when the first switch array is in a preset sampling configuration and the second switch array is in a preset calibration configuration and the second switch array performs charge injection compensation;
and in the normal working mode, the first switch array is configured to be in a preset sampling configuration, and the second switch array is configured to be in a preset calibration configuration or a target calibration configuration.
In one embodiment, the foreground calibration mode includes:
first sampling phase, bottom plate switch S w_bottom Conducting, configuring the first switch array into a preset sampling configuration, configuring the second switch array into a preset calibration configuration, and then arranging the bottom plate switch S w_bottom The charge injection of (a) is 0;
first switching phase, bottom plate switch S w_bottom And closing, configuring the first switch array into a preset sampling configuration, configuring the second switch array into a preset calibration configuration, and configuring the bottom plate switch S w_bottom The charge injection is deltaV, and a successive approximation control algorithm is adopted to obtain a target calibration configuration of the second switch array so as to enable the first input end of the comparator to generate a voltage difference-V _ charge _ inj, thereby offsetting the bottom plate switch S w_bottom The charge injection deltaV.
In one embodiment, the normal operation mode includes:
second sampling phase, bottom plate switch S w_bottom Conducting, configuring the first switch array into a preset sampling configuration, configuring the second switch array into a preset calibration configuration, and then configuring the bottom plate switch S w_bottom The charge injection of (a) is 0;
second switching phase, bottom plate switch S w_bottom Turning off, the first switch array is configured to a preset sampling configuration, the second switch array configuration is switched from the preset calibration configuration to a target calibration configuration, so as to generate a voltage difference-V _ charge _ inj at the first input end of the comparator, and thus, the bottom plate switch S is offset w_bottom Charge injection deltaV.
In an embodiment, the analog-to-digital converter further includes a digital processing module, connected to the control logic unit, and configured to obtain the target calibration configuration after averaging according to the multiple calibration configurations.
In one embodiment, the digital processing module is a digital filter.
In an embodiment, the analog-to-digital converter further includes a calibration control storage unit connected to the control logic unit, and configured to store a target calibration configuration corresponding to the preset sampling configuration.
In one embodiment, the preset calibration configuration of the second switch array is a middle configuration, and the highest second capacitor in the second capacitor array is higher than the reference voltage high level V REFP The second capacitors of the other bits are connected with the reference voltage with a low level V REFN Are connected.
Compared with the prior art, the invention has the following advantages:
the charge compensation unit is added on the basis of the existing SAR ADC, so that charge injection introduced by a bottom plate switch under any switch configuration can be compensated, and measurement and compensation of mu V-magnitude charge injection are realized;
the signal is directly compensated in a voltage mode, and the signal can be matched with a compensation circuit of any other analog domain without introducing conflict or mismatch;
the digital processing module can improve the signal-to-noise ratio of the measurement results, thereby reducing the need for analog portion switching and comparator noise.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a successive approximation type analog-to-digital converter in the prior art;
FIG. 2 is a circuit diagram of a successive approximation analog-to-digital converter according to the present invention;
FIG. 3 is a circuit diagram of a successive approximation analog-to-digital converter according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a successive approximation analog-to-digital converter in a charge injection compensation state according to an embodiment of the present invention;
fig. 5 is a timing diagram of the voltage Va at the first input terminal of the comparator during the successive approximation calibration process of the successive approximation analog-to-digital converter according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
Referring to fig. 2, the successive approximation analog-to-digital converter based on charge injection compensation in the present invention includes:
a Comparator (COMP)10 including a first input terminal (-), a second input terminal (+) and an output terminal, wherein a bottom plate switch S is arranged between the first input terminal and the second input terminal w_bottom ；
The sample-and-hold unit 20 comprises a first capacitor array CDAC _ main connected to the first input terminal of the comparator and a second capacitor array CDAC _ mai connected to the first input terminal of the comparatorn connected to a first switch array S _ main for controlling the capacitance of the first capacitor array CDAC _ main and the input voltage signal V IN Or a reference voltage high level V REFP Or the reference voltage is low level V REFN Connecting;
a charge compensation unit 30 including a second capacitor array CDAC _ cal connected to the first input terminal of the comparator and a second switch array S _ cal connected to the second capacitor array for controlling the capacitance of the second capacitor array CDAC _ cal and the high level V of the reference voltage REFP Or the reference voltage is low by a level V REFN Connected, the charge compensation unit is used for offsetting the bottom plate switch S w_bottom Charge injection of (3);
and the control logic unit 40 is used for generating first control logic for controlling the first switch array S _ main and second control logic for controlling the second switch array S _ cal according to a successive approximation control algorithm.
Preferably, the reference voltage is low by a level V REFN Typically ground potential (0V).
Specifically, in the sample-and-hold unit 20, the first capacitor array CDAC _ main includes Nbit _ main first capacitors C 0_main 、C 1_main 、…C Nbit_main-1_main The capacitance value of the first capacitor is C =2 Nbit_main-1 C u Nbit _ main ≧ 2, i.e., C 0_main =C u 、C 1_main =2C u 、…C Nbit_main-1_main =2 Nbit-1_main C u (ii) a The first switch array S _ main comprises Nbit _ main group switches S 0_main 、S 1_main 、…S Nbit-1_main Each group of switches includes a first switch S1, a second switch S2 and a third switch S3, the first switch S1 is electrically connected to the input voltage signal V1 IN A second switch S2 electrically connected to the reference voltage and the first capacitor REFP A third switch S3 electrically connected to the reference voltage at a low level V REFN And the first capacitor.
Specifically, in the charge compensation unit 30, the second capacitor array CDAC _ cal includes Nbit _ cal second capacitors C 0_cal 、C 1_cal 、…C Nbit _ cal-1_cal The capacitance value of the second capacitor is C =2 Nbit_cal-1 C u_cal Nbit _ cal ≧ 2, i.e., C 0_cal =C u_cal 、C 1_cal =2C u_cal 、…C Nbit _ cal-1_cal =2 Nbit_cal-1 C u_cal (ii) a The second switch array S _ cal includes Nbit _ cal groups of switches S 0_cal 、S 1_cal 、…S Nbit _ cal-1_cal Each group of switches includes a fourth switch S4 and a fifth switch S5, the fourth switch S4 is electrically connected to the reference voltage high level V REFP A fifth switch S5 electrically connected to the reference voltage at a low level V REFN And a second capacitor.
The analog-to-digital converter comprises a foreground calibration mode and a normal operation mode.
In the foreground calibration mode, acquiring a target calibration configuration when the second switch array S _ cal performs charge injection compensation when the first switch array S _ main is in a preset sampling configuration and the second switch array S _ cal is in a preset calibration configuration, specifically including:
first sampling phase, bottom plate switch S w_bottom Conducting, configuring the first switch array S _ main to a preset sampling configuration, configuring the second switch array S _ cal to a preset calibration configuration, and then configuring the bottom plate switch S w_bottom The charge injection of (a) is 0;
first switching phase, bottom plate switch S w_bottom When the system is turned off, the first switch array S _ main is configured to be in a preset sampling configuration, the second switch array S _ cal is configured to be in a preset calibration configuration, and the bottom plate switch S is turned on w_bottom The target calibration configuration of the second switch array S _ cal is obtained by adopting a successive approximation control algorithm, so that the first input end of the comparator generates a voltage difference-V _ charge _ inj, and the bottom plate switch S is offset w_bottom Charge injection deltaV.
In the normal operating mode, the first switch array S _ main is configured as a preset sampling configuration, and the second switch array S _ cal is configured as a preset calibration configuration or a target calibration configuration, which specifically includes:
second sampling phase, bottom plateSwitch S w_bottom Conducting, configuring the first switch array S _ main to a preset sampling configuration, configuring the second switch array S _ cal to a preset calibration configuration, and then configuring the bottom plate switch S w_bottom The charge injection of (a) is 0;
second switching phase, bottom plate switch S w_bottom The first switch array S _ main is switched off, the first switch array S _ main is configured to be in a preset sampling configuration, and the second switch array S _ cal is switched from a preset calibration configuration to a target calibration configuration so as to generate a voltage difference-V _ charge _ inj at the first input end of the comparator, thereby offsetting the bottom plate switch S w_bottom The charge injection deltaV.
The specific working principle of the successive approximation analog-to-digital converter based on charge injection compensation is as follows:
in the calibration mode, first enter the first sampling phase, bottom plate switch S w_bottom Conducting, switching the first switch array S _ main to the preset sampling configuration corresponding to the desired calibration, each group of switches in the first switch array S _ main being connected to V IN 、V REFP Or V REFN In the above, the second switch array S _ cal is configured in the preset calibration configuration, and the corresponding charge injection amount is 0 in the preset calibration configuration. Then enters a first conversion phase, a bottom plate switch S w_bottom And closing, wherein all switches in the first switch array S _ main remain unchanged, and a voltage difference deltaV seen by the first input terminal of the comparator is the charge injection of the switch introduced at this time. At this time, the calibration second switch array S _ cal may be sequentially set to 1 from high to low by using a conventional successive approximation algorithm, and the final target calibration configuration may be found by the binary method.
In a normal mode, firstly entering a second sampling phase, and configuring a second switch array S _ cal in a preset calibration configuration; and in a second sampling phase, the second switch array c is switched to a target calibration configuration, and a voltage difference-V _ charge _ inj, -V _ charge _ inj is approximately equal to deltaV is generated at the first input end of the comparator, so that the bottom plate switch S is counteracted w_bottom Charge injection deltaV.
The second switch array S _ cal is exemplified by 4 bits (Nbit _ cal =4), and its charge injection amount is equal to its sampling phase and conversion phaseDelta value of input code. For example, the middle code of the ideal 4-bit second switch array S _ cal is 4' b 1000. In the sampling phase, the input of the second switch array S _ cal is always connected to 4' b 1000. In the conversion phase, the input of the second switch array S _ cal is still 4' b1000, and the input of the second switch array S _ cal is not changed, i.e. the highest level is connected to V in the sampling phase REFP All low-order are connected with V REFN (ii) a When the phase is switched, the highest bit is connected with V REFP All low-order are connected with V REFN . Since the input of the second switch array S _ cal is not changed, the second switch array S _ cal outputs the charge injected at the conversion phase as 0, i.e., the output voltage deltaV = 0. In the same way, the input of the second switch array S _ cal of the sampling phase is connected with 4 'b 1000, and is converted into 4' b1111, so that the charge injection compensation amount is the forward maximum; the sampling phase second switch array S _ cal is connected to 4 'b 1000, the conversion phase is connected to 4' b0000, and the charge injection compensation amount is a negative maximum value.
Further, the analog-to-digital converter in this embodiment further includes a digital processing module 50 and a quasi-control storage unit 60, wherein:
the digital processing module 50 is connected to the control logic unit 40, and is configured to obtain a target calibration configuration after averaging according to the multiple calibration configurations;
the calibration control storage unit 60 is connected to the control logic unit 40 and the digital processing module 50, and is configured to store a target calibration configuration corresponding to a preset sampling configuration.
Since the error introduced by the switch injection is usually very small and thus is easily affected by the noise of the circuit itself, the calibration process described above may be repeatedly performed, and then the calibration result is averaged for multiple times by introducing a digital processing module, thereby improving the accuracy of the calibration result.
In this embodiment, the digital processing module is a digital filter, and the simplest first-order digital filter may be generally selected, and the operation is implemented by performing multiple calibrations and then averaging. Recording the configuration of the first time calibration as Trim _ code1, the configuration of the second time calibration as Trim _ code2, the configuration of the Nth time calibration as Trim _ codeN, and the output of the digital processing module as the target calibration configuration after multiple times of averaging:
Trim_code_out=（Trim_code1+Trim_code2+…Trim_codeN）/N。
the preset calibration configuration of the second switch array S _ cal is a middle configuration, and the second capacitor of the highest position in the second capacitor array CDAC _ cal is higher than the reference voltage high level V REFP The second capacitors of the other bits are connected with the reference voltage with a low level V REFN Are connected. The second switch array S _ cal is for example 4 bits (Nbit _ cal =4), and the ideal default calibration configuration is 4' b 1000. The input of the second switch array S _ cal is 4' b1000 at the sampling phase, thereby ensuring that its output range is positive-negative direction symmetric.
Referring to fig. 3 and 4, in an embodiment of the invention, the successive approximation analog-to-digital converter is a 10-bit SAR ADC with 4-bit charge injection compensation, i.e., Nbit _ main =10 and Nbit _ cal = 4.
The first capacitor array CDAC _ main includes 10 first capacitors having a capacitance value of C =2 Nbit-1_main C u I.e. C 0_main =C u 、C 1_main =2C u 、…C 9_main =512C u (ii) a The first switch array S _ main comprises 10 groups of switches S 0_main 、S 1_main 、…S 9_main Each group of switches includes a first switch S1, a second switch S2 and a third switch S3, the first switch S1 is electrically connected to the input voltage signal V1 IN A second switch S2 electrically connected to the reference voltage and the first capacitor REFP A third switch S3 electrically connected to the first capacitor at a low reference voltage level V REFN And the first capacitor.
The second capacitor array CDAC _ cal includes 4 second capacitors having a capacitance value of C =2 Nbit_cal-1 C u_cal I.e. C 0_cal =C u_cal 、C 1_cal =2C u_cal 、C 2_cal =4C u_cal 、C 3_cal =8C u_cal (ii) a The second switch array S _ cal comprises 4 groups of switches S 0_cal 、S 1_cal 、S 2_cal 、S 3_cal Each group of switches includes a fourth switch S4 and a fifth switch S5, the fourth switch S4 is electrically connected to the reference voltage high level V REFP And a second capacitor, a fifth switch S5 electrically connected to the reference voltage at a low level V REFN And a second capacitor.
First, logic control signals of the first switch array S _ main corresponding to the first capacitor array CDAC _ main are determined when calibration is required. Taking fig. 3 as an example, when the first switch S1 in the first switch array S _ main is turned on, the second switch S2 and the third switch S3 are turned off, and the first capacitors are connected to the input voltage signal V IN At this time, calibration V IN During sampling, the bottom polar plate samples the switch S w_bottom Charge injection of (2).
It should be understood that the first switch array S _ main may be connected differently and the corresponding charge injection may be different, and that the first switch array S _ main may be calibrated regardless of the connection.
The calibration process is divided into a sampling phase and a conversion phase. Sampling phase as shown in fig. 3, the first capacitor array CDAC _ main is connected to the input voltage signal V through the first switch array S _ main IN In the second capacitor array CDAC _ cal, the highest bit capacitance C 3_cal Is connected with V REFP Low level capacitor C 2_cal 、C 1_cal 、C 0_cal Are all connected with V REFN . Then S w_bottom Off, when the charge injection generates a voltage V _ charge _ inj at the first input Va of the comparator.
During the calibrated transition phase, the first switch array S _ main remains unchanged. The calibration CDAC is set to 1 by the comparison algorithm of the SAR bit by bit, and then whether the Va voltage is larger than 0 at the moment is judged by the comparator. According to the output Dout of the comparator, the input bit of the second capacitor array S _ cal is determined from high order to low order, and finally Va approaches to 0 through continuous approximation.
The calibration process of CDAC _ cal and S _ cal in this embodiment is described in detail below with reference to FIGS. 3-5.
For the first comparison, the second switch array S _ cal is unchanged, and the highest-order capacitor C 3_cal Is connected with V REFP Low level capacitor C 2_cal 、C 1_cal 、C 0_cal Are all connected with V REFN Then judging a comparator, judging that the voltage Va at the moment isIf not, it is greater than 0. If Va is greater than 0, the comparator output 1 'b 0, representing the second capacitor array CDAC _ cal is highest connected to 1' b0, recording Dout _ cal<3>= 1' b0, control logic controls switch S of CDAC _ cal 3_cal Switching over C 3_cal To V REFN 。
Then for the 2 nd Bit of CDAC _ cal set 1' b1, control logic controls switch S of CDAC _ cal 2_cal Switching over C 2_cal To V REFP Then, the comparator is judged to judge whether the voltage Va is larger than 0 at the moment. If Va is less than 0, the comparator output 1 'b 1, representing CDAC _ cal is connected to 1' b1 the second time, Dout _ cal is recorded<2>= 1' b1, control logic controls switch S of CDAC _ cal 2_cal Switching over C 2_cal To V REFP 。
Next, for the 3 rd Bit of CDAC _ cal set 1' b1, control logic controls switch S of CDAC _ cal 1_cal Switching over C 1_cal To V REFP Then, the comparator is judged to judge whether the voltage Va is larger than 0 at the moment. Assuming that Va is less than 0, the comparator output 1 'b 1, representing CDAC _ cal 3 rd bit 1' b1, records Dout _ cal<1>= 1' b1, control logic controls switch S of CDAC _ cal 1_cal Switching over C 1_cal To V REFP 。
Finally, for the 4 th position 1' b1 of CDAC _ cal, the control logic controls switch S of CDAC _ cal 0_cal Switching over C 0_cal To V REFP Then, the comparator is judged to judge whether the voltage Va is larger than 0 at the moment. Assuming that Va is less than 0, the comparator output 1 'b 1, representing CDAC _ cal bit 4 is connected to 1' b1, records Dout _ cal<0>= 1' b1, control logic controls switch S of CDAC _ cal 0_cal Switching over C 0_cal To V REFP 。
Thus, Dout _ cal <3:0> = 4' b0111, which is the quantization result of the voltage V _ charge _ inj, is obtained, and the configuration of the second switch array S _ cal is shown in fig. 4.
Under the ideal and noise-free condition, the accurate value of Dout _ cal can be obtained only by performing the conversion process once, but under the normal condition, the signal quantity of charge injection is very small, namely the signal Va at the input end of the comparator is very small, the above processes are repeated for a plurality of times of calibration, and the times of Dout _ cal1<3:0>, Dout _ cal2<3:0>, … Dout _ calN <3:0> are obtained, wherein N is the times of the plurality of times of calibration. The digital processing module calculates the average value of multiple calibrations, and the final calibration code is Dout _ cal <3:0> = (Dout _ cal1<3:0> + Dout _ cal2<3:0> + … + Dout _ calN <3:0 >)/N.
Thus, with the configuration of CDAC _ cal and S _ cal, a voltage deltaV may be generated at the comparator output Va during the conversion phase, the magnitude of deltaV being approximately equal to-V _ charge _ inj, thereby eliminating the effect of the prior charge injection.
The technical scheme shows that the invention has the following beneficial effects:
the charge compensation unit is added on the basis of the existing SAR ADC, so that charge injection introduced by a bottom plate switch under any switch configuration can be compensated, and measurement and compensation of mu V-magnitude charge injection are realized;
the signal is directly compensated in a voltage mode, and the signal can be matched with a compensation circuit of any other analog domain without introducing conflict or mismatch;
the digital processing module can improve the signal-to-noise ratio of the measurement results, thereby reducing the need for analog portion switching and comparator noise.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. A successive approximation analog-to-digital converter based on charge injection compensation, the analog-to-digital converter comprising:
the comparator comprises a first input end, a second input end and an output end, and a bottom plate switch S is arranged between the first input end and the second input end w_bottom ；
A sample-hold unit including a first capacitor array connected with the first input terminal of the comparator and a first switch array connected with the first capacitor array for controlling the capacitors in the first capacitor array and the input voltage signal V IN Or a reference voltage high level V REFP Or the reference voltage is low level V REFN Connecting;
a charge compensation unit including a second capacitor array connected with the first input terminal of the comparator and a second switch array connected with the second capacitor array for controlling the capacitors in the second capacitor array and the high level V of the reference voltage REFP Or the reference voltage is low level V REFN Connected, the charge compensation unit is used for offsetting the bottom plate switch S w_bottom Charge injection of (3);
the control logic unit is used for generating a first control logic for controlling the first switch array and a second control logic for controlling the second switch array according to a successive approximation control algorithm;
the analog-to-digital converter comprises when operating in a foreground calibration mode,
first sampling phase, bottom plate switch S w_bottom Conducting, configuring the first switch array into a preset sampling configuration, and configuring the second switch array into a preset calibration configuration;
first switching phase, bottom plate switch S w_bottom Turning off, configuring the first switch array into a preset sampling configuration, configuring the second switch array into a preset calibration configuration, and obtainingTarget calibration configuration of the second switch array to counteract the bottom plate switch S w_bottom Charge injection of (2).
2. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 1, wherein the first capacitor array comprises Nbit _ main first capacitors, and the capacitance value of the first capacitors is C-2 Nbit_main-1 C u Nbit _ main is more than or equal to 2; the first switch array comprises Nbit _ main first switches, Nbit _ main second switches and Nbit _ main third switches, and the first switches are electrically connected to the input voltage signal V IN A second switch electrically connected to the reference voltage and the first capacitor REFP A third switch electrically connected to the reference voltage at a low level V REFN And the first capacitor.
3. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 1, wherein the second capacitor array comprises Nbit _ cal second capacitors, and the capacitance value of the second capacitors is C-2 Nbit_cal-1 C u_cal Nbit _ cal is more than or equal to 2; the second switch array comprises Nbit _ cal fourth switches and Nbit _ cal fifth switches, and the fourth switches are electrically connected with the reference voltage high level V REFP A fifth switch electrically connected to the reference voltage at a low level V REFN And a second capacitor.
4. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 1, wherein the analog-to-digital converter comprises:
in the foreground calibration mode, a target calibration configuration is obtained when the first switch array is in a preset sampling configuration and the second switch array is in a preset calibration configuration and the second switch array performs charge injection compensation;
and a normal operating mode, wherein in the normal operating mode, the first switch array is configured to a preset sampling configuration, and the second switch array is configured to a preset calibration configuration or a target calibration configuration.
5. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 4, wherein the foreground calibration mode comprises:
a first sampling phase, at which time the bottom plate switch S w_bottom The charge injection of (2) is 0;
a first switching phase, in which the bottom plate switch S is on w_bottom The charge injection is deltaV, and a successive approximation control algorithm is adopted to obtain a target calibration configuration of the second switch array so as to enable the first input end of the comparator to generate a voltage difference-V _ charge _ inj, thereby offsetting the bottom plate switch S w_bottom Charge injection deltaV.
6. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 4, wherein the normal operation mode comprises:
second sampling phase, bottom plate switch S w_bottom Conducting, configuring the first switch array into a preset sampling configuration, configuring the second switch array into a preset calibration configuration, and then configuring the bottom plate switch S w_bottom The charge injection of (a) is 0;
second switching phase, bottom plate switch S w_bottom Turning off, the first switch array is configured to a preset sampling configuration, the second switch array configuration is switched from the preset calibration configuration to a target calibration configuration, so as to generate a voltage difference-V _ charge _ inj at the first input end of the comparator, and thus, the bottom plate switch S is offset w_bottom Charge injection deltaV.
7. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 4, wherein the analog-to-digital converter further comprises a digital processing module connected to the control logic unit for obtaining the target calibration configuration after averaging according to the multiple calibration configurations.
8. The charge injection compensation based successive approximation analog-to-digital converter according to claim 7, wherein the digital processing module is a digital filter.
9. The successive approximation analog-to-digital converter based on charge injection compensation according to claim 4, characterized in that the analog-to-digital converter further comprises a calibration control storage unit connected to the control logic unit for storing a target calibration configuration corresponding to a preset sampling configuration.
10. The charge injection compensation-based successive approximation analog-to-digital converter according to claim 4, wherein the preset calibration configuration of the second switch array is an intermediate configuration, the second capacitor of the highest bit in the second capacitor array is higher than the reference voltage by a high level V REFP The second capacitors of the other bits are connected with the reference voltage with a low level V REFN Are connected.
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