CN114189002A - Switching control circuit, charging chip, electronic device and related method - Google Patents
Switching control circuit, charging chip, electronic device and related method Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
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Abstract
The invention provides a switching control circuit, which comprises an oscillator circuit, a delay calibration and time sequence circuit, a target current acquisition circuit and a current switching circuit. The oscillator circuit is used for generating a clock signal, the delay calibration and time sequence circuit is used for carrying out delay calibration on the clock signal so as to output at least one control signal, and the target current acquisition circuit is used for responding to the at least one control signal to obtain a target current which is used for reflecting the target constant power current in the constant power mode. The current switching circuit is used for receiving the target current and reflecting a first preset current of the target constant current in the constant current mode, and controlling and outputting one of the target current and the first preset current. The invention also provides a charging chip and an electronic device. The invention can control the power in the constant power mode to be consistent and ensure the switching precision of switching the constant power mode to the constant current mode.
Description
Technical Field
The present invention relates to a control circuit, and more particularly, to a switching control circuit for controlling switching between a constant power mode and a constant current mode, a charging chip having the switching control circuit, and an electronic device having the switching control circuit.
Background
At present, the charging technology of terminals such as mobile phones and tablet computers is rapidly developed, and the rapid charging technology also becomes the standard configuration of the current terminals. Generally, the current fast charging technology includes three stages/modes of constant voltage, constant power and constant current during the charging process.
In the initial constant voltage mode, when the output current is small, the output power is smaller than the set power, and then the Constant Voltage (CV) is output; with the gradual increase of the output current, after the power reaches a set power value, the output voltage begins to drop while the current is increased, and the Constant Power (CP) output is maintained; when the output current is increased to the set maximum current value, the Constant Current (CC) mode is entered, the output current is kept unchanged, and the voltage continues to drop. Generally, in the constant power mode, the power is required to be kept consistent in real time; in the constant current mode, the CC current switched from the constant power mode to the constant current mode is accurate. However, in the prior art, it is often impossible to ensure that the power in the constant power mode is always consistent, or when switching from the constant power mode to the constant current mode, there is an overlapping interval, resulting in inaccurate switching point, and the current situation often results in a problem that the charging efficiency is reduced or the charging device is damaged after a long time.
Therefore, how to control the power in the constant power mode to be consistent and ensure the switching accuracy of the constant power mode to the constant current mode becomes a problem to be considered in the fast charging technology.
Disclosure of Invention
The invention aims to provide a switching control circuit, a charging chip and an electronic device, which can control the power in a constant power mode to be consistent and ensure the switching accuracy of switching from the constant power mode to a constant current mode.
In one aspect, a switching control circuit is provided that includes an oscillator circuit, a delay calibration and timing circuit, a target current acquisition circuit, and a current switching circuit. The oscillator circuit is used for generating a clock signal. The delay calibration and timing circuit is used for performing delay calibration on the clock signal so as to output at least one control signal. The target current obtaining circuit is used for responding to the at least one control signal to obtain a target current, and the target current is used for reflecting the target constant power current in the constant power mode. The current switching circuit comprises a first input end, a second input end and a current output end, wherein the first input end is used for receiving the target current, the second input end is used for receiving a first preset current, and the first preset current is used for reflecting the target constant current in a constant current mode; the current switching circuit is used for controlling a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end, wherein when the target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
In another aspect, a charging chip is provided, where the charging chip includes a switching control circuit, and the switching control circuit includes an oscillator circuit, a delay calibration and timing circuit, a target current obtaining circuit, and a current switching circuit. The oscillator circuit is used for generating a clock signal. The delay calibration and timing circuit is used for performing delay calibration on the clock signal so as to output at least one control signal. The target current obtaining circuit is used for responding to the at least one control signal to obtain a target current, and the target current is used for reflecting the target constant power current in the constant power mode. The current switching circuit comprises a first input end, a second input end and a current output end, wherein the first input end is used for receiving the target current, the second input end is used for receiving a first preset current, and the first preset current is used for reflecting the target constant current in a constant current mode; the current switching circuit is used for controlling a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end, wherein when the target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
In another aspect, an electronic device is provided, which includes a switching control circuit including an oscillator circuit, a delay calibration and timing circuit, a target current obtaining circuit, and a current switching circuit. The oscillator circuit is used for generating a clock signal. The delay calibration and timing circuit is used for performing delay calibration on the clock signal so as to output at least one control signal. The target current obtaining circuit is used for responding to the at least one control signal to obtain a target current, and the target current is used for reflecting the target constant power current in the constant power mode. The current switching circuit comprises a first input end, a second input end and a current output end, wherein the first input end is used for receiving the target current, the second input end is used for receiving a first preset current, and the first preset current is used for reflecting the target constant current in a constant current mode; the current switching circuit is used for controlling a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end, wherein when the target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
When the current target current is smaller than the first preset current, namely when the current target current is still in a constant power mode, the switching control circuit, the charging chip and the electronic device perform current control in the constant power mode by outputting the target current, so that the output current is the target constant power current; and when the current target current reaches the first preset current, namely the switching point of the current constant power mode and the constant current mode, the first preset current is output at the moment, so that the output current is the target constant current, and the current mode is accurately switched to the constant current mode. The switching accuracy of switching the constant power mode to the constant current mode is realized. In addition, because the delay calibration and the sequential circuit are adopted for delay calibration, the constant output power can be ensured, and the output power cannot change along with the change of the output voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic voltage-current curve during charging.
Fig. 2 is a circuit block diagram of a switching control circuit according to an embodiment of the present application.
Fig. 3 is a specific circuit diagram of a switching control circuit according to an embodiment of the present application.
Fig. 4 is a timing diagram of a clock signal and a plurality of control signals according to an embodiment of the present disclosure.
Fig. 5 is a circuit block diagram of a current switching circuit in a switching control circuit according to an embodiment of the present application.
Fig. 6 is a specific circuit diagram of a current switching circuit according to an embodiment of the present application.
Fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.
Fig. 8 is a flowchart of a handover control method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The method for adjusting the threshold range of the capacitance key signal can be applied to any terminal equipment with a capacitance key.
Fig. 1 is a schematic diagram of a voltage-current curve during a charging process. As shown in fig. 1, in general, during the charging process, three stages/modes of constant voltage, constant power and constant current are included. In the initial constant voltage mode, when the output current is small and the output power is less than the set power P0, outputting a Constant Voltage (CV); with the gradual increase of the output current, after the power reaches a set power value P0, entering a constant power mode, in the constant power mode, when the current increases, the output voltage starts to decrease, and the Constant Power (CP) output is maintained, that is, the output power is maintained at the set power value P0; when the output current increases to the set current value Icc, a Constant Current (CC) mode is entered, the output current remains unchanged, i.e. the set current value Icc is maintained, and the voltage continues to drop. Therefore, during the charging process, the voltage is decreased from the constant power mode to the constant current mode, and the current is increased from the constant voltage mode to the constant power mode until the constant current mode is kept. Fig. 1 is a schematic diagram of a voltage-current curve in an ideal state.
Please refer to fig. 2, which is a circuit block diagram of a switching control circuit 100 according to an embodiment of the present application. The switching control circuit 100 is used for switching control between a constant power mode and a constant current mode and controlling power constancy in the constant power mode. As shown in fig. 1, the switching control circuit 100 includes an oscillator circuit 1, a delay calibration and timing circuit 2, a target current obtaining circuit 3, and a current switching circuit 4.
Wherein, the oscillator circuit 1 is used for generating a clock signal; the delay calibration and timing circuit 2 is used for performing delay calibration on the clock signal to output at least one control signal; the target current obtaining circuit 3 is configured to obtain a target current in response to the plurality of control signals, where the target current is used to reflect a target constant power current in a constant power mode; the current switching circuit 4 includes a first input terminal 41, a second input terminal 42 and a current output terminal 43, where the first input terminal 41 is configured to receive the target current, the second input terminal 42 is configured to receive a first preset current, and the first preset current is used to reflect a target constant current in a constant current mode; the current switching circuit 4 is configured to control the current output end 43 to output an output current according to the target current received by the first input end 41 and the first preset current received by the second input end 42, where the output current is the target current when the current target current is smaller than the first preset current, so as to implement current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
Therefore, in the present application, since the target current reflects a target constant power current in a constant power mode, and the first preset current reflects a target constant current in a constant power mode, when the current target current is smaller than the first preset current, it indicates that the current is still in the constant power mode, and at this time, current control in the constant power mode is performed by outputting the target current, so that the output current is the target constant power current; and when the current target current reaches the first preset current, the switching point of the current constant power mode and the constant current mode is indicated, and at this time, the first preset current is output, so that the output current is the target constant current, and the current mode is accurately switched to the constant current mode. The switching accuracy of switching the constant power mode to the constant current mode is realized. In addition, because the delay calibration and the time sequence circuit 2 are adopted for delay calibration, the constant output power can be ensured, and the output power can not change along with the change of the output voltage.
The target constant power current in the present application refers to a current that should be output currently in a constant power mode, that is, a current that can maintain a constant power and corresponds to a current output voltage in the constant power mode. The target constant current refers to a set current value Icc output in the constant current mode.
The target current used for reflecting the target constant power current in the constant power mode in the application means that the target current is equal to or in a certain proportional relation with the target constant power current in the constant power mode, and the first preset current used for reflecting the target constant current in the constant current mode means that the first preset current is equal to or in a certain proportional relation with the target constant current in the constant current mode. When the target current is in a certain proportional relationship, the proportional relationship between the target current and the target constant power current in the constant power mode is the same as the proportional relationship between the first preset current and the target constant current in the constant current mode, for example, the proportional relationship may be reduced by the same proportional coefficient.
Further, as shown in fig. 2, the switching control circuit 100 further includes a feedback comparison circuit 5, where the feedback comparison circuit 5 is configured to receive the output current output by the current switching circuit 4 and a feedback current reflecting a current actual output current, compare the output current with the feedback current, and generate an adjustment signal when the output current is inconsistent with the feedback current until the feedback current is consistent with the output current, so that the actual current in the constant power mode is consistent with the target constant power current to implement current control in the constant power mode, or the actual current in the constant current mode is consistent with the target constant current to switch to the constant current mode to implement current control in the constant current mode.
Specifically, to further realize that the actually output current is equal to the current that should be output in the current constant power mode through the feedback comparison circuit 5, so as to ensure the power to be constant, and to realize that the actually output current is equal to the set current value Icc that should be output in the current constant current mode when switching to the constant current mode, so as to ensure the accurate switching between the constant power and the constant current.
In some embodiments, the oscillator circuit 1 is configured to receive an associated current related to a present output voltage and the first preset current, and generate the clock signal according to the output current and the first preset current.
That is, in some embodiments, the clock signal generated by the oscillator circuit 1 is specifically generated according to the output current related to the present output voltage and the first preset current.
The associated current associated with the current output voltage may refer to a current converted from the current output voltage, for example, by dividing the current output voltage by a resistance value of a specific resistor. In some embodiments, the specific resistance, e.g., a resistance of 200 ohms, may be connected at the output of the switching control circuit 100, with the associated current being generated in the specific resistance. Wherein the associated current is actually changing since the present output voltage is changing all the time.
Fig. 3 is a specific circuit diagram of the switching control circuit 100 according to an embodiment of the present application. As shown in fig. 3, the oscillator circuit 1 includes a comparator 11, a first capacitor C1, a first resistor R1, and an NMOS transistor M0, wherein the comparator 11 includes a first non-inverting input 111, a first inverting input 112, and a first output 113, the first non-inverting input 111 is configured to receive the associated current Ivout, the first non-inverting input 111 is further grounded through the first capacitor C1, the first inverting input 112 is configured to receive the first predetermined current, the first inverting input 112 is further grounded through the first resistor R1, the NMOS transistor M0 and the first capacitor C1 are connected in parallel between the first non-inverting input 111 and the ground, and the first output 113 is connected to the gate of the NMOS transistor M0. Wherein the first predetermined current flows through the first resistor R1 to generate a predetermined reference voltage Vr at the first inverting input terminal 112, the first predetermined current is used to charge the first capacitor C1, so that the voltage Vc of the first capacitor C1 at the end connected to the first non-inverting input terminal 111 rises, that is, the voltage Vc of the first non-inverting input terminal 111 rises, when the voltage Vc of the first non-inverting input terminal rises to reach the predetermined reference voltage Vr, the comparator 11 outputs a high level signal to the gate of the NMOS transistor M0 through the first output terminal 113 to control the NMOS transistor M0 to be turned on, so that the first capacitor C1 is discharged through the turned-on NMOS transistor M0, so that the voltage of the first non-inverting input terminal 111 falls to be less than the predetermined reference voltage Vr, so that the comparator outputs a low level signal through the first output terminal 113, thereby, the oscillator circuit 1 is caused to output a clock signal that varies periodically, wherein a low level time period in each period of the clock signal is equal to a charging time period T for which the first capacitor is charged to reach the preset reference voltage.
As shown in fig. 3, the delay calibration and timing circuit 2 includes a signal input terminal 20, a first signal output terminal 21, a second signal output terminal 22 and a third signal output terminal 23, the signal input terminal 20 of the delay calibration and timing circuit 2 is connected to the first output terminal 113 of the comparator 11 for receiving the clock signal, and the delay calibration and timing circuit 2 is configured to perform delay calibration on the clock signal to output a first control signal S1, a second control signal S2 and a third control signal S3 through the first signal output terminal 21, the second signal output terminal 22 and the third signal output terminal 23, respectively.
Fig. 4 is a timing diagram of a clock signal and a plurality of control signals. Wherein, the low level duration in each period of the clock signal CK output by the oscillator circuit 1 is equal to the charging duration T for the first capacitor to charge to reach the preset reference voltage. As shown in fig. 4, the first control signal S1 is a signal obtained by extending and inverting a high level time period of the clock signal CK, wherein the high level time period of the first control signal S1 is equal to a charging time period T for the first capacitor C1 to be charged to reach the preset reference voltage, i.e., equal to a low level time period of the clock signal CK. The second control signal S1 is equal to the clock signal CK, i.e., the second control signal S1 can be the clock signal CK. The third control signal S3 is a signal obtained by delaying the high level of the clock signal CK, i.e., delaying to flip to the high level, the high level period of the third control signal S3 is staggered from the high level period of the second control signal S2, and the high level periods of the second control signal S2 and the third control signal S3 are both located in the low level period of the first control signal S1.
Therefore, the delay calibration and timing circuit 2 performs delay calibration on the clock signal, and outputs the first control signal S1, the second control signal S2 and the third control signal S3 through the first signal output terminal 21, the second signal output terminal 22 and the third signal output terminal 23, respectively, for controlling the subsequent circuits, so as to achieve constant power output.
Although the associated current Ivout varies with the current output voltage, it is known that charging generally requires more than one hour, and therefore the charging time period T for the first capacitor to charge to the preset reference voltage is much shorter than the time period of the constant power mode, and therefore, the clock signal and the period of the plurality of control signals can be regarded as constant in a short time, and therefore, the clock signal and the plurality of control signals shown in fig. 4 are kept substantially the same in each of several periods.
Specifically, as shown in fig. 3, the target current obtaining circuit 3 includes a first switch K1, a second switch K2, a third switch K3, a second capacitor C2, a third capacitor C3, a first operational amplifier 31 and a second resistor R2, one end of the first switch K1 is used for accessing a second preset current, the second preset current is related to a target output voltage when the constant power mode is switched to the constant current mode, the other end of the first switch K2 is grounded through the third switch K3, the second switch K3 is connected between the connection node N1 of the first switch K1 and the third switch K3 and the second non-inverting input terminal 311 of the first operational amplifier 31, the connection node N1 of the first switch K1 and the third switch K3 is also grounded through a second capacitor C2, the second non-inverting input terminal 311 is further grounded through the third capacitor C3, and the second inverting input terminal 312 of the first operational amplifier 31 is further grounded through the second resistor R2.
Referring back to fig. 1, the ideal current corresponding to the switching time point when the constant power mode is switched to the constant current mode is the set current value Icc in the constant current mode, the corresponding switching point output voltage is Vsp, and the power of the constant power is equal to the power of the switching time point, that is, equal to the product of the target output voltage Vsp and the constant current Icc.
The second predetermined current related to the switching point output voltage when the constant power mode is switched to the constant current mode may refer to the second predetermined current being converted from the switching point output voltage Vsp, for example, obtained by dividing the switching point output voltage by a resistance value of a specific resistor, for example, by 200 ohms.
Since the target output voltage is generally a fixed value after the switching control circuit 100 is applied to a terminal, for example, since the current corresponding to the target output voltage is exactly a constant current theoretically, and the power at this time is also the set power in the constant power mode, the target output voltage is a value uniquely obtained according to the set current value Icc in the constant current mode and the set power in the constant power mode. Therefore, the second preset current can be directly generated by a constant current source (called a constant current source for short) after being calculated in advance according to the switching point output voltage and the resistance value of the specific resistor.
The first preset current may also be generated by a constant current source, which is referred to as a constant current source for short.
As shown in fig. 3, the first inverting input terminal 112 of the comparator 11 is specifically connected to a first constant current source Y1, the first constant current source Y1 is configured to generate a first preset current, and the first inverting input terminal 112 of the comparator 11 receives the first preset current generated by the first constant current source Y1. The second input terminal 42 of the current switching circuit 4 is connected to a second constant current source Y2, the second constant current source Y2 is also used for providing the first preset current, and the second input terminal 42 of the current switching circuit 4 receives the first preset current generated by the second constant current source Y2. One end of the first switch K1, which is used for connecting in the second preset current, is connected with a third constant current source Y3, and the third constant current source Y3 is used for generating the second preset current. Herein, "XX receives the current generated by the constant current source" in this application refers to the current generated by the constant current source flowing in the direction of XX, for example, the first preset current generated by the second constant current source Y2 received by the second input terminal 42 of the current switching circuit 4 refers to the first preset current generated by the second constant current source Y2 flowing into the second input terminal 42 of the current switching circuit 4.
As shown in fig. 3, the first signal output terminal 21 is connected to the first switch K1 for outputting the first control signal S1 to the first switch K1 to control the on/off of the first switch K1, the second signal output terminal 22 is connected to the second switch K2 for outputting the second control signal to the second switch K2 to control the on/off of the second switch K2, and the third signal output terminal 23 is connected to the third switch K3 for outputting the third control signal S3 to the third switch K3 to control the on/off of the third switch K3.
Wherein the first switch K1, the second switch K2 and the third switch K3 are all high-level conducting switches, the second control signal S2 and the third control signal S3 are continuously low level within a first duration time that the first control signal S1 is high level, the first switch K1 is continuously conducting, the second switch K2 and the third switch K3 are turned off, the second preset current continuously charges the second capacitor C2 through the conducting first switch K1 within the first duration time, the second control signal S2 is firstly changed to high level within a second duration time that the first control signal S1 is low level, the first control signal S1 and the third control signal S3 are both low level at the moment, the second switch K2 is conducting, the first switch K1 and the third switch K3 are turned off, and the charges of the second capacitor C73742 and the third capacitor C2 are shared by the conducting second switch K2, that is, the second capacitor C2 charges the third capacitor C3. When the third control signal S3 changes to high level, the first control signal S1 and the second control signal S2 are both low level, the third switch K3 is turned on, the first switch K1 and the second switch K2 are turned off, and the second capacitor C2 is discharged by connecting the turned-on third switch K3 to ground. Through the above periodic process, under the control of the first control signal S1, the second control signal S2 and the third control signal S3 for several periods, the voltage of the third capacitor C3 is equal to the cut-off voltage Vs when the second capacitor C2 is charged and cut off, the second non-inverting input terminal 311 of the first operational amplifier 31 is virtually short with the second inverting input terminal 312, so that the voltage of the second inverting input terminal 312 is also the cut-off voltage Vs, the cut-off voltage Vs is applied to the second resistor R0, and the current flowing through the second resistor R0 is the target current Iconv.
That is, with the above configuration, the target current obtaining circuit 3 can obtain the target current Iconv reflecting the target constant power current in the constant power mode.
Specifically, as described above, the ideal current corresponding to the switching time point of switching from the constant power mode to the constant current mode is the set current value Icc in the constant current mode, and the corresponding switching point output voltage is Vsp.
In some embodiments, let the target current Iconv be equal to the target constant power current in the constant power mode and let the present output voltage be Vout, so that the target current Iconv and the present output voltage Vout are actually powers in the constant power mode and equal to the switching point output voltage Vsp.
That is, equation 1 can be derived:
Vout*Iconv＝Vsp*Icc。
as described above, when the oscillator circuit 1 generates the clock signal CK, the associated current Ivout charges the first capacitor C1, such that the charging time period of the first capacitor C1 connected to the first non-inverting input terminal 111 reaching the preset reference voltage Vr is T, the capacitance of the first capacitor C1 is C1, according to the charge calculation formula, Ivout T × Vr × C1, the first preset current Icc1, and the resistance of the first resistor R1 is R1, since the preset reference voltage Vr × Icc1 × R1 and, as mentioned above, Ivout is Vout/R, formula 2 is obtained:
Ivout*T＝Icc1*R1*C1。
further, equation 3 can be obtained: t ═ Icc1 ═ R1 ═ C1/Ivout;
in the target current obtaining circuit 3, as mentioned above, the on-time of the first switch K1 is equal to the charging time T of the first capacitor C1 connected to the first non-inverting input terminal 111 to reach the preset reference voltage Vr, and the charging time T of the second capacitor C2 by the second preset current Ivsp is also equal to T, so that the capacitance of the second capacitor C2 is set to C2, and according to the charge calculation formula, Ivsp T is equal to the cut-off voltage Vs C2, so that the formula 4 can be reached: the cutoff voltage Vs ═ i vsp T/C2, equation 3 above: by substituting T ═ Icc1 ═ R1 × C1/Ivout into equation 4, equation 5 can be obtained:
Vs＝Ivsp*Icc1*R1*C1/(C2*Ivout)；
assuming that the associated current Ivout is generated by applying the current output voltage Vout to a specific resistor R having a resistance value R, Ivout is Vout/R. Assuming that the second predetermined current is i vp, the output voltage Vsp is also applied to a specific resistor R having a resistance R for the switching point, i.e., i vp is Vsp/R.
Therefore, since Iconv is the cutoff voltage Vs/R2, Ivsp is Vsp/R, Ivout is Vout/R, equation 6 can be obtained:
if Iconv R2 is Vsp Icc 1R 1C 1R/(R C2 Vout), resistance R1 is R2, and capacitance C1 is C2, equation 6 can be simplified as follows:
iconv _ R2 ═ Vsp _ Icc1 ═ R1/Vout, i.e., consistent with the foregoing equation 1: iconv Vout Vsp Icc 1. That is, in the present application, the target current Iconv is obtained by the design of the switching control circuit described above, and corresponds to the current output voltage Vout and conforms to the constant power mode.
As shown in fig. 2-3, in some embodiments, the switching control circuit 100 further includes a current mirror circuit 6, the current mirror circuit 6 being configured to mirror the target current Iconv to the first input 41 of the current switching circuit 4. As shown in fig. 3, the current mirror circuit 6 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3, sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to each other, a gate of the first MOS transistor M1 is connected to a gate of the second MOS transistor M2, a drain of the first MOS transistor M1 is connected to a source of the third MOS transistor M3, a drain of the second MOS transistor M2 is connected to the first input terminal 41 of the current switching circuit 4, a drain of the third MOS transistor M3 is connected to a far end of the second resistor R2, a gate of the third MOS transistor M3 is connected to the second output terminal 312 of the first operational amplifier 31, a current flowing through the third MOS transistor M3 is equal to a target current flowing through the second resistor R2, the first MOS transistor M1 and the second MOS transistor M2 constitute a current mirror, and the drain of the third MOS transistor M3 flows through the target current mirror transistor M2, so that the first input 41 of the current switching circuit 4 receives the target current Iconv.
As shown in fig. 3, the sources of the first MOS transistor M1 and the second MOS transistor M2 are both connected to a voltage source VDD.
As shown in fig. 3, as also described above, the second input terminal 32 of the current switching circuit 3 is connected to the second constant current source Y2 to receive the first predetermined current generated by the second constant current source Y2.
The current switching circuit 3 may output the target current Iconv when the current target current is smaller than the first preset current, so as to implement current control in a constant power mode; when the target current reaches the first preset current, outputting the first preset current Icc1 for switching to the constant current mode and realizing current control in the constant current mode.
Fig. 5 is a circuit block diagram of a current switching circuit 4 according to an embodiment of the present application. The current switching circuit 4 further includes an adding circuit 401, a subtracting circuit 402, a first current mirror 403, and a second current mirror 404, the adding circuit 401 is connected to the first input terminal 41 and the second input terminal 42 of the current switching circuit 4, and is configured to add the first preset current and the target current to output a sum current of the first preset current Icc1 and the target current Iconv, wherein the sum current is equal to a sum of the first preset current Icc1 and the target current Iconv when the target current Iconv is smaller than the first preset current Icc1, and the sum current is equal to twice the first preset current Icc1 when the target current Iconv is not smaller than the first preset current Icc 1. The first current mirror 403 is configured to mirror the summed current to the subtracting circuit 402, the subtracting circuit 402 is configured to subtract the summed current from the first preset current Icc1 to obtain a subtracted current difference, and the second current mirror 404 is connected between the subtracting circuit 402 and the current output end 43 of the current switching circuit 4, and is configured to mirror the current difference to the current output end 43 to obtain an output current output from the current output end 43.
Wherein, when the target current Iconv is smaller than the first preset current Icc1, the summed current is equal to the sum of the first preset current Icc1 and the target current Iconv, when the target current Iconv is not smaller than the first preset current Icc1, the summed current is equal to twice the first preset current Icc1, and, when the target current Iconv is smaller than the first preset current Icc1, the constant power mode is still performed, and when the target current is not smaller than the first preset current Icc, the constant current mode is performed. Therefore, in the constant power mode, the sum current is equal to the sum of the first predetermined current Icc1 and the target current Iconv, and the target current Iconv is obtained by subtracting the first predetermined current Icc 1; in the constant current mode, the sum current is equal to twice the first preset current Icc1, and is subtracted from the first preset current Icc1 to obtain the first preset current Icc 1.
Therefore, the current switching circuit 4 can output the target current Iconv to realize current control in the constant power mode when the current target current is smaller than the first preset current Icc1 by the above circuit structure; outputting the first preset current Icc1 when the target current Iconv reaches the first preset current Icc 1.
Fig. 6 is a specific circuit diagram of the current switching circuit 4 according to an embodiment of the present application. As shown in fig. 6, the adding circuit 401 includes a fourth MOS transistor M4 and a fifth MOS transistor M4, a drain of the fourth MOS transistor M4 is connected to the second input terminal 42 of the current switching circuit 4 for receiving the first preset current Icc1, a drain of the fifth MOS transistor M4 is connected to the first input terminal 41 of the current switching circuit 4 for receiving the target current Iconv, a gate of the fourth MOS transistor M4 is connected to a gate of the fifth MOS transistor M5, a source of the fourth MOS transistor M4 is connected to a source of the fifth MOS transistor M5, the fourth MOS transistor M4 and the fifth MOS transistor form the adding circuit 401, and a source connected to the fifth MOS transistor M5 through the fourth MOS transistor M4 outputs a sum current.
As mentioned above, when the target current is smaller than the first preset current, the summed current is equal to the sum of the first preset current and the target current, and when the target current is not smaller than the first preset current, the source output current of the fifth MOS transistor M5 is limited to the first preset current, so that the summed current is equal to twice the first preset current.
The first current mirror 403 includes a sixth MOS transistor M6 and a seventh MOS transistor M7, a drain of the sixth MOS transistor M6 is connected to a source of the fourth MOS transistor M4 and a source of the fifth MOS transistor M5, a source of the sixth MOS transistor M6 is grounded, a gate of the sixth MOS transistor M6 is connected to a gate of the seventh MOS transistor M7, a source of the seventh MOS transistor M7 is grounded, the summed current is mirrored to the seventh MOS transistor M7, and a current flowing through the seventh MOS transistor M7 is the summed current.
The subtraction circuit 402 includes a first branch L1, a second branch L2, and a third branch L3, first ends of the first branch L1, the second branch L2, and the third branch L3 are connected to a same node N2, a second end of the first branch L1 is used for inputting the first preset current Icc1, a second end of the second branch L2 is connected to a drain of the seventh MOS transistor M7, and a flowing current is the sum current. The second current mirror 404 includes an eighth MOS transistor M8 and a ninth MOS transistor M9, a drain of the eighth MOS transistor M8 is connected to the second end of the third branch L3, wherein a current of the third branch L3 is equal to a difference between a sum current flowing through the second branch L2 and a first predetermined current Icc1 flowing through the first branch L1. That is, as shown in fig. 6, the current flowing through the first branch L1 flows into the node N2, the current flowing through the third branch L3 also flows into the node N2, and the direction of the summed current flowing through the second branch L2 flows from the node N2 to the seventh MOS transistor M7, so that the summed current flowing through the second branch L2 is substantially equal to the sum of the current flowing through the third branch L3 and the first predetermined current Icc1 flowing through the first branch L1. Therefore, the current of the third branch L3 is equal to the difference between the summed current flowing through the second branch L2 and the first predetermined current Icc1 flowing through the first branch L1.
The gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, the drain of the eighth MOS transistor M8 is connected to the second end of the third branch L3, the current flowing through the drain of the eighth MOS transistor M8 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current flowing through the first branch L1, the source of the eighth MOS transistor M8 is connected to the source of the ninth MOS transistor M9, the drain of the ninth MOS transistor M9 is connected to the current output end 43 of the current switching circuit 4, the current of the drain of the eighth MOS transistor M8 is mirrored to the drain of the ninth MOS transistor M9, so that the output current output by the current output end 43 is equal to the difference between the summed current flowing through the second branch L2 and the first preset current flowing through the first branch L1. Thereby, the output current is the target current Iconv when the present target current Iconv is less than the first preset current Icc1, and the output current is the first preset current Icc1 when the target current Iconv reaches the first preset current Icc 1.
As shown in fig. 6, the second end of the first branch L2 is connected to a fourth constant current source Y4, the fourth constant current source Y4 generates the first preset current Icc1, and the second end of the first branch L2 receives the first preset current Icc1 generated by the fourth constant current source Y4.
The source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are both connected to a voltage source VDD.
Referring back to fig. 3, the feedback comparison circuit 5 specifically includes a second operational amplifier 51, the second operational amplifier includes a third non-inverting input terminal 511, a third inverting input terminal 512 and a third output terminal 513, the third non-inverting input terminal 511 is configured to receive a feedback current Ics reflecting the current actual output current, and the third non-inverting input terminal 511 is further connected to the ground through a third resistor R3. The third inverting input terminal 512 is connected to the current output terminal 43 of the current switching circuit 4, and the third inverting input terminal 512 is also connected to the ground through a fourth resistor R4.
The feedback current Ics flows through the third resistor R3 so that the third non-inverting input terminal 511 has a corresponding voltage, the output current output from the current output terminal 43 of the current switching circuit 4 flows through the fourth resistor R4 so that the third inverting input terminal 512 has a corresponding voltage, and the second operational amplifier 51 compares the voltages of the third non-inverting input terminal 511 and the third inverting input terminal 512 and generates an adjustment signal when the voltages of the third non-inverting input terminal 511 and the third inverting input terminal 512 are not equal to each other. Specifically, when the voltage of the third non-inverting input terminal 511 is greater than the voltage of the third inverting input terminal 512, a high-level adjustment signal is output, and when the voltage of the third non-inverting input terminal 511 is less than the voltage of the third inverting input terminal 512, a low-level adjustment signal is output.
Wherein the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4. The voltage at the third non-inverting input terminal 511 is equal to Ics × R3, and the output current output by the current output terminal 43 is Icp, the voltage at the third inverting input terminal 512 is equal to Icp × R4, and since the resistance value of the third resistor R3 is equal to the resistance value of the fourth resistor R4, the magnitude relationship between the voltage at the third non-inverting input terminal 511 and the voltage at the third inverting input terminal 512 is the relationship between the feedback current Ics and the output current Icp.
The adjustment signal may be provided to a subsequent processing circuit, and the subsequent processing circuit may control to decrease the actually output current when receiving the adjustment signal of the high level, and control to increase the actually output current when receiving the adjustment signal of the low level, so that the actually output current, i.e., the feedback current Ics, is equal to the output current Icp. For another example, the output path may have a switch therein, and the processing circuit may control to change the duty ratio of the on/off of the switch to change the magnitude of the current actually output.
The third output terminal 513 is further connected to components such as a capacitor and a resistor for filtering.
Therefore, through the switching control circuit 100 of the present application, the power in the constant power mode can be controlled to be consistent, and the switching accuracy of switching from the constant power mode to the constant current mode can be ensured.
In some embodiments, the switching control circuit 100 may be integrated into a chip, such as a charging chip, to achieve power uniformity in a constant power mode during charging and ensure switching accuracy of switching from the constant power mode to a constant current mode. Further, the charging chip may be a fast charging chip supporting fast charging.
Please refer to fig. 7, which is a block diagram illustrating an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes the aforementioned switching control circuit 100.
The electronic device 100 may be a terminal such as a mobile phone and a tablet computer, and the electronic device 100 may also be a charging adapter.
The electronic device 100 further includes other elements, which are not described in detail since they are not related to the improvement of the present invention.
Please refer to fig. 8, which is a flowchart illustrating a handover control method according to an embodiment of the present application. The switching control method is applied to the switching control circuit 100. As shown in fig. 8, the handover control method includes:
801: a clock signal is generated by an oscillator circuit.
802: and carrying out delay calibration on the clock signal through a delay calibration and time sequence circuit so as to output a plurality of control signals.
803: and responding to the control signals through a target current acquisition circuit to obtain a target current, wherein the target current is used for reflecting the target constant power current in the constant power mode.
804: and receiving the target current through a first input end of the current switching circuit, and receiving a first preset current through a second input end of the current switching circuit, wherein the first preset current is used for reflecting the target constant current in a constant current mode.
805: the current switching circuit controls a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end; when the current target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode, and when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
The switching control method may further include other steps, and may further include steps corresponding to the operations executed by the switching control circuit 100, for example: when the current target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current, and the switching to the constant current mode and the current control in the constant current mode are realized "includes: and receiving the output current output by the current switching circuit and a feedback current reflecting the current actual output current through a feedback comparison circuit, comparing the output current with the feedback current, and generating an adjusting signal when the output current is inconsistent with the feedback current until the feedback current is consistent with the output current, so that the actual current in a constant power mode is consistent with the target constant power current to realize the current control in the constant power mode, or the actual current in the constant current mode is consistent with the target constant current to switch to the constant current mode to realize the current control in the constant current mode.
Specifically, the other steps included in the switching control method may refer to the related description of the switching control circuit 100.
Reference is made herein to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope hereof. For example, various operational steps, as well as components used to perform the operational steps, may be deleted, modified or combined with other steps.
The foregoing is illustrative of embodiments of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the embodiments of the present invention and are intended to be within the scope of the present invention.
Claims (10)
1. A switching control method is applied to a switching control circuit, and comprises the following steps:
outputting a plurality of control signals through a delay calibration and a time sequence circuit;
responding to the control signals through a target current acquisition circuit to obtain a target current, wherein the target current is used for reflecting a target constant power current in a constant power mode;
receiving the target current through a first input end of a current switching circuit, and receiving a first preset current through a second input end of the current switching circuit, wherein the first preset current is used for reflecting the target constant current in a constant current mode;
the current switching circuit controls a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end; when the current target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode, and when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
2. A switching control circuit, comprising:
a delay calibration and timing circuit for outputting at least one control signal;
the target current obtaining circuit is used for responding to the at least one control signal to obtain a target current, and the target current is used for reflecting a target constant power current in a constant power mode;
the current switching circuit comprises a first input end, a second input end and a current output end, wherein the first input end is used for receiving the target current, the second input end is used for receiving a first preset current, and the first preset current is used for reflecting the target constant current in a constant current mode; the current switching circuit is used for controlling a current output end to output an output current according to the target current received by the first input end and the first preset current received by the second input end,
when the target current is smaller than the first preset current, the output current is the target current and is used for realizing current control in a constant power mode; when the target current reaches the first preset current, the output current is the first preset current and is used for switching to the constant current mode and realizing current control in the constant current mode.
3. The switching control circuit according to claim 2, further comprising a feedback comparison circuit, wherein the feedback comparison circuit is configured to receive an output current output by the current switching circuit and a feedback current reflecting a current actual output current, compare the output current with the feedback current, and generate a regulation signal when the output current is inconsistent with the feedback current until the feedback current is consistent with the output current, so that the actual current in the constant power mode is consistent with the target constant power current to achieve current control in the constant power mode, or make the actual current in the constant current mode be consistent with the target constant current to switch to the constant current mode and achieve current control in the constant current mode.
4. The switching control circuit of claim 3, further comprising an oscillator circuit for generating a clock signal; the oscillator circuit is configured to receive a correlation current related to a current output voltage and the first preset current, and generate the clock signal according to the correlation current and the first preset current, where the delay calibration and timing circuit calibrates the clock signal to output at least one control signal.
5. The switching control circuit of claim 4, wherein the oscillator circuit comprises a comparator, a first capacitor, a first resistor, and an NMOS transistor, the comparator comprises a first positive input terminal, a first negative input terminal, and a first output terminal, the first positive input terminal is configured to receive the associated current and is further grounded through the first capacitor, the first negative input terminal is configured to receive the first predetermined current and is further grounded through the first resistor, the NMOS transistor and the first capacitor are connected in parallel between the first positive input terminal and ground, and the first output terminal is connected to a gate of the NMOS transistor; wherein the first predetermined current flows through the first resistor to generate a predetermined reference voltage at the first inverting input terminal, the first predetermined current is used for charging the first capacitor, so that the voltage of the first non-inverting input terminal rises, when the voltage of the first non-inverting input terminal rises to reach the preset reference voltage, the comparator outputs a high level signal to the grid electrode of the NMOS tube through a first output end, and controlling the NMOS tube to be conducted so that the first capacitor is discharged through the conducted NMOS tube, so that the voltage of the first non-inverting input terminal is decreased to be less than the preset reference voltage, so that the comparator outputs a low level signal through the first output terminal, thereby, the oscillator circuit outputs a clock signal which periodically changes, and the low level time length in each period of the clock signal is equal to the charging time length T for the first capacitor to charge to reach the preset reference voltage.
6. The switching control circuit of claim 5, wherein the delay calibration and timing circuit comprises a first signal output terminal, a second signal output terminal, and a third signal output terminal, and the delay calibration and timing circuit is used to perform delay calibration on the clock signal to output a first control signal, a second control signal, and a third control signal through the first signal output terminal, the second signal output terminal, and the third signal output terminal, respectively, wherein the first control signal is a signal obtained by extending a high level time duration in the clock signal and then performing phase inversion, and wherein the high level time duration in the first control signal is equal to a charging time duration T for the first capacitor to be charged to the preset reference voltage; the second control signal is equal to the clock signal, the third control signal is a signal obtained by delaying a high level of the clock signal, a high level period of the third control signal is staggered from a high level period of the second control signal, and the high level periods of the second control signal and the third control signal are both located in a low level period of the first control signal.
7. The switching control circuit of claim 6, wherein the target current obtaining circuit comprises a first switch, a second switch, a third switch, a second capacitor, a third capacitor, a first operational amplifier, and a second resistor, one end of the first switch is used for accessing a second preset current, the second preset current is related to the output voltage when the constant power mode is switched to the constant current mode, the other end of the first switch is grounded through the third switch, the second switch is connected between a connection node of the first switch and the third switch and the second non-inverting input end of the first operational amplifier, the connection node of the first switch and the third switch is grounded through a second capacitor, the second positive phase input end is grounded through the third capacitor, and the second negative phase input end of the first operational amplifier is grounded through the second resistor.
8. The switching control circuit according to claim 7, wherein the first signal output terminal is connected to the first switch for outputting the first control signal to the first switch to control the on or off of the first switch, the second signal output terminal is connected to the second switch for outputting the second control signal to the second switch to control the on or off of the second switch, and the third signal output terminal is connected to the third switch for outputting the third control signal to the third switch to control the on or off of the third switch; wherein the first switch, the second switch, and the third switch are all high-level conducting switches, the second control signal and the third control signal are continuously low level within a first duration time when the first control signal is high level, the first switch is continuously conducting, the second switch and the third switch are off, the second preset current continuously charges the second capacitor through the conducting first switch within the first duration time, the second control signal is firstly changed into high level within a second duration time when the first control signal is low level, the first control signal and the third control signal are both low level at this time, the second switch is conducting, the first switch and the third switch are off, the second capacitor and the third capacitor are charge-shared through the conducting second switch, when the third control signal is changed into high level, at the moment, the first control signal and the second control signal are both low level, the third switch is turned on, the first switch and the second switch are turned off, and the second capacitor is connected with the ground through the turned-on third switch to discharge; under the control of a first control signal, a second control signal and a third control signal of a plurality of cycles, the voltage of the third capacitor is equal to a cut-off voltage when the second capacitor is charged and cut off, the second non-inverting input terminal and the second inverting input terminal of the first operational amplifier are virtually short, so that the voltage of the second inverting input terminal is also the cut-off voltage, the cut-off voltage is applied to the second resistor, and the current flowing through the second resistor is the target current.
9. A charging chip, characterized in that it comprises a switching control circuit according to any one of claims 1 to 8.
10. An electronic device, characterized in that the electronic device comprises a switching control circuit according to any of claims 1-8.
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