CN114171586B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN114171586B CN114171586B CN202210123457.6A CN202210123457A CN114171586B CN 114171586 B CN114171586 B CN 114171586B CN 202210123457 A CN202210123457 A CN 202210123457A CN 114171586 B CN114171586 B CN 114171586B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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Abstract
The invention discloses a semiconductor device, which at least comprises: a first field effect transistor; and a second field effect transistor; setting a lightly doped drain on the source side of the first field effect transistor as a lightly doped drain part on the source side, setting a lightly doped drain on the drain side of the first field effect transistor as a lightly doped drain part on the drain side, and setting the lightly doped drain length of the lightly doped drain part on the drain side to be larger than the lightly doped drain length of the lightly doped drain part on the source side; the lightly doped drain length of the source side lightly doped drain portion is smaller than that of the lightly doped drain portion arranged on the second field effect transistor, and the lightly doped drain length of the drain side lightly doped drain portion is larger than that of the lightly doped drain portion arranged on the second field effect transistor. The invention provides a semiconductor device and a manufacturing method thereof, which can inhibit the increase of circuit area in the semiconductor device and inhibit the generation of leakage current.
Description
Technical Field
The present invention relates to semiconductor devices, and more particularly to a semiconductor device and a method for manufacturing the same.
Background
In a Semiconductor device, a large number of Metal-Oxide-Semiconductor (MOSFET) transistors are formed on a silicon substrate to form each circuit.
Disclosure of Invention
In a semiconductor device, low power consumption is an important factor. Therefore, MOS transistors in semiconductor devices need to reduce leakage current. The leakage current of the MOS transistor is, for example, a sub-threshold current or GIDL (Gate Induced drain leakage). GIDL refers to a current that tunnels between energy bands due to an increase in electric field intensity in a region where a gate and a drain overlap and becomes a leakage current.
The invention provides a semiconductor device and a method for manufacturing the same, which can restrain the increase of circuit area in the semiconductor device and the generation of leakage current.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a semiconductor device, which at least comprises:
a first field effect transistor; and
a second field effect transistor;
setting a lightly doped drain electrode at the source electrode side of the first field effect transistor as a source electrode side lightly doped drain electrode part, setting a lightly doped drain electrode at the drain electrode side of the first field effect transistor as a drain electrode side lightly doped drain electrode part, and setting the length of the lightly doped drain electrode at the drain electrode side lightly doped drain electrode part to be larger than the length of the lightly doped drain electrode at the source electrode side lightly doped drain electrode part;
the lightly doped drain length of the source side lightly doped drain portion is smaller than the lightly doped drain length of the lightly doped drain arranged on the second field effect transistor, and the lightly doped drain length of the drain side lightly doped drain portion is larger than the lightly doped drain length of the lightly doped drain arranged on the second field effect transistor.
In an embodiment of the present invention, a length obtained by adding the lightly doped drain length of the source side lightly doped drain portion and the lightly doped drain length of the drain side lightly doped drain portion is 2 times a length of a lightly doped drain provided in the second field effect transistor.
In one embodiment of the present invention, the depth of the source side lightly doped drain portion is equal to the depth of the drain side lightly doped drain portion.
In one embodiment of the present invention, the impurity concentration of the source-side lightly doped drain portion is equal to the impurity concentration of the drain-side lightly doped drain portion.
In one embodiment of the present invention, in the semiconductor device, the first field effect transistor is provided in plurality and adjacent to each other.
In one embodiment of the present invention, in the semiconductor device, the first field effect transistor is provided in plurality, and sources of the first field effect transistors are connected to each other and drains of the first field effect transistors are connected to each other.
In one embodiment of the present invention, the first field effect transistor is a high voltage metal oxide semiconductor field effect transistor, and the power supply voltage is 2.5V or more and 8V or less.
In one embodiment of the present invention, the first field effect transistor constitutes an output buffer circuit.
In an embodiment of the invention, when the lightly doped drain length of the source side lightly doped drain portion is d1 and the lightly doped drain length of the drain side lightly doped drain portion is d2, d2/d1 is greater than or equal to 2.
In an embodiment of the invention, when the lightly doped drain length of the source side lightly doped drain portion is d1 and the lightly doped drain length of the drain side lightly doped drain portion is d2, d2/d1 is greater than or equal to 6.
In an embodiment of the invention, when the lightly doped drain length of the source side lightly doped drain portion is d1 and the lightly doped drain length of the drain side lightly doped drain portion is d2, d2/d1 is greater than or equal to 9.
A method of manufacturing a semiconductor device for manufacturing a semiconductor device including a first field effect transistor and a second field effect transistor, comprising:
a gate formation step of forming a gate of the first field effect transistor;
a source-drain formation step of forming a source and a drain of the first field effect transistor; and
a lightly doped drain injection step of forming a source side lightly doped drain portion and a drain side lightly doped drain portion, wherein the source side lightly doped drain portion is used as a lightly doped drain on a source side of the first field effect transistor, and the drain side lightly doped drain portion is used as a lightly doped drain on a drain side of the first field effect transistor;
the lightly doped drain length of the drain side lightly doped drain part is greater than that of the source side lightly doped drain part;
the lightly doped drain length of the source side lightly doped drain portion is smaller than the lightly doped drain length of the lightly doped drain arranged on the second field effect transistor, and the lightly doped drain length of the drain side lightly doped drain portion is larger than the lightly doped drain length of the lightly doped drain arranged on the second field effect transistor.
In one embodiment of the present invention, the gate forming step forms a gate oxide film and a gate electrode, and the lightly doped drain implantation step is performed before the gate electrode is formed.
In one embodiment of the present invention, the gate forming step forms a gate oxide film and a gate electrode, and the lightly doped drain implanting step is performed after the gate electrode is formed into a predetermined gate pattern.
In one embodiment of the present invention, the gate forming step forms a gate oxide film and a gate electrode, and the lightly doped drain implanting step is performed after the gate electrode is formed and before the gate electrode is formed into a predetermined gate pattern.
As described above, the present invention provides a semiconductor device and a method for manufacturing the same, which can efficiently perform the injection of a lightly doped drain, suppress an increase in circuit area, and suppress the generation of a leakage current.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a diagram showing an example of each circuit formed on a silicon substrate according to an embodiment of the present invention.
Fig. 3 is a diagram showing an example of a MOSFET array according to an embodiment of the present invention.
Fig. 4 is a diagram showing a simulation result of an unbalanced structure according to an embodiment of the present invention.
Fig. 5 is a diagram showing a simulation result of an unbalanced structure according to an embodiment of the present invention.
Fig. 6 is a diagram showing a simulation result of an unbalanced structure according to an embodiment of the present invention.
Fig. 7 is a diagram showing a relationship between an unbalanced structure and an electric field strength according to an embodiment of the present invention.
Fig. 8 is a diagram showing a relationship between an unbalanced structure and an electric field strength according to an embodiment of the present invention.
Fig. 9 is a diagram showing steps of the first manufacturing method 1 according to an embodiment of the present invention.
Fig. 10 is a diagram showing steps of the first manufacturing method 1 according to an embodiment of the present invention.
Fig. 11 is a diagram showing steps of the first manufacturing method 1 according to an embodiment of the present invention.
Fig. 12 is a diagram showing steps of a manufacturing method 2 according to an embodiment of the present invention.
Fig. 13 is a diagram showing steps of a manufacturing method 2 according to an embodiment of the present invention.
Fig. 14 is a diagram showing steps of the production method 2 according to the embodiment of the present invention.
Fig. 15 is a diagram showing steps of a manufacturing method 2 according to an embodiment of the present invention.
Fig. 16 is a diagram showing steps of a 3 rd manufacturing method according to an embodiment of the present invention.
Fig. 17 is a diagram showing steps of the 3 rd manufacturing method according to the embodiment of the present invention.
Fig. 18 is a diagram showing steps of a 3 rd manufacturing method according to an embodiment of the present invention.
Fig. 19 is a block diagram of a source driver according to an embodiment of the present invention.
Fig. 20 is a diagram showing an example of an output buffer circuit according to an embodiment of the present invention.
Description of reference numerals: 1 a first field effect transistor, 2 a second field effect transistor, 3 a MOSFET arrangement, 4 a MOSFET circuit, 5 a core logic circuit, 10 a semiconductor device, BF buffer, CT contact, D1, D2 drain, E0 lightly doped drain, E1 source side lightly doped drain, E2 drain side lightly doped drain, G1, G2 gate, IF insulating film, INV inverter, L channel length, Lg gate length, M metal wiring, OX gate oxide film, S1, S2 source, SW sidewall, W1, W2 well, D0 lightly doped drain length, D1 lightly doped drain length, D2 lightly doped drain length.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a semiconductor device 10, wherein the semiconductor device 10 includes a first field effect transistor 1 and a second field effect transistor 2. In the semiconductor device 10, the first field effect transistor 1 and the second field effect transistor 2 are mixed and mounted on the same substrate. In fig. 1 (and also in other figures), a first field effect transistor 1 and a second field effect transistor 2, which are mounted in a mixed manner, are separately shown. The first Field Effect Transistor 1 and the second Field Effect Transistor 2 are Semiconductor devices (FETs) having MOS structures, where the MOS is a Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET). Further, an insulating film IF and a contact portion CT are formed on the upper surfaces of the first field effect transistor 1 and the second field effect transistor 2, and a metal wiring M is provided on the metal layer.
Referring to fig. 1, the first field effect transistor 1 is a mosfet structure, and the first field effect transistor 1 includes a gate (gate electrode) G1, a source S1, a drain D1, and a well W1. The gate G1 is formed on the gate oxide film OX. The first field effect transistor 1 is, for example, an N-Metal-Oxide-Semiconductor (NMOS).
As shown in fig. 1, the first field effect transistor 1 is provided with a Lightly Doped Drain (LDD) which is a region having a lower impurity concentration than the Drain D1 or the source S1 and is provided with respect to the Drain D1 or the source S1 (e.g., an end portion). The lightly doped drain provided on the source side of the first field effect transistor 1 is a source side lightly doped drain portion E1. The lightly doped drain provided on the drain side of the first field effect transistor 1 is a drain side lightly doped drain portion E2. As shown in fig. 1, the lightly doped drain length of the source side lightly doped drain portion E1 is set to d1, and the lightly doped drain length of the drain side lightly doped drain portion E2 is set to d 2. The lightly doped drain length is the length in the same direction as the channel length L in the lightly doped drain region. That is, the length of the lightly doped drain region between the source S1 and the drain D1 is referred to as a lightly doped drain length. As shown in fig. 1, in the first field effect transistor 1, the lightly doped drain length d1 of the source side lightly doped drain portion E1 is smaller than the lightly doped drain length d2 of the drain side lightly doped drain portion E2 (d 1 < d 2). That is, the first field effect transistor 1 has an unbalanced structure in which the lightly doped drain lengths are different between the drain D1 side and the source side.
Referring to fig. 1, the second field effect transistor 2 has the same MOS structure as the first field effect transistor 1, and the second field effect transistor 2 includes a gate G2, a source S2, a drain D2, and a well W2. The gate G2 is formed on the gate oxide film OX. Further, the second field effect transistor 2 is provided with a lightly doped drain portion E0 at the source S2 and the drain D2, respectively. In the second field effect transistor 2, the lightly doped drain length of the source side lightly doped drain portion E0 and the lightly doped drain length of the drain side lightly doped drain portion E0 are equal and are both d 0. That is, the second field effect transistor 2 has a symmetrical structure in which the lightly doped drain lengths are equal on the drain side and the source side. The second field effect transistor 2 is, for example, an N-type metal oxide semiconductor.
Referring to fig. 1, in the semiconductor device 10, the first field effect transistor 1 has the relationship of d1 < d2 as described above. On the other hand, as described above, in the second field effect transistor 2, the lightly doped drain portions E0 formed on the drain side and the source side have the same lightly doped drain length and are d 0. Further, the first field effect transistor 1 and the second field effect transistor 2 are in such a relationship that the lightly doped drain length d1 of the source side lightly doped drain portion E1 of the first field effect transistor 1 is smaller than the lightly doped drain length d0 of the lightly doped drain portion E0 provided in the second field effect transistor 2. The lightly doped drain length d2 of the drain side lightly doped drain portion E2 of the first field effect transistor 1 is longer than the lightly doped drain length d0 of the lightly doped drain portion E0 provided in the second field effect transistor 2. That is, the first field effect transistor 1 and the second field effect transistor 2 have a relationship of d1 < d0 < d 2.
As shown in fig. 1, in the first field effect transistor 1, the lightly doped drain length d1 of the source side lightly doped drain portion E1 and the lightly doped drain length d2 of the drain side lightly doped drain portion E2 are added to each other to obtain a length 2 times as long as the lightly doped drain length d0 of the lightly doped drain portion E0 of the second field effect transistor 2. That is, the first field-effect transistor 1 and the second field-effect transistor 2 have a relationship of d1 + d2 ═ d0 + d0 ═ 2 × d 0. For example, the gate length of the gate G1 of the first field effect transistor 1 and the gate length of the gate G2 of the second field effect transistor 2 can be manufactured with the minimum gate length in the process, and the gate lengths Lg that are the same as each other can be employed. In this case, channel lengths L equal to each other can be adopted in the first field effect transistor 1 and in the second field effect transistor 2. That is, the first field-effect transistor 1 and the second field-effect transistor 2 have a relationship of d1 + d2 + L ═ d0 + d0 + L ═ 2 × d0 + L.
As shown in fig. 1, if the length including the gate length Lg and the length of the sidewall SW is set to Lt, since the gate length Lg and the length of the sidewall SW are equal to each other in the first field effect transistor 1 and the second field effect transistor 2, Lt is d1 + d2 + L, d0 + d0 + L, 2 × d0 + L. That is, compared to the case where the second field effect transistor 2 is formed with the minimum gate length, the first field effect transistor 1 also forms the gate G1 with the minimum gate length, and the total size (d 1 + d 2) of the lightly doped drains can be made constant, so that the element size can be made the same.
Referring to fig. 1, in the first field effect transistor 1, the depth of the source side lightly doped drain portion E1 is equal to the depth of the drain side lightly doped drain portion E2, and both the depths are Ld. Since the drain-side lightly doped drain portion E2 and the source-side lightly doped drain portion E1 are formed by the same process (the same mask), the depth of the drain-side lightly doped drain portion E2 in the stacking direction is equal to that of the source-side lightly doped drain portion E1. The depth of the lightly doped drain of the second field effect transistor 2 is also Ld. The impurity concentration of the source-side lightly doped drain portion E1 is equal to the impurity concentration of the drain-side lightly doped drain portion E2. For example, since the drain-side lightly doped drain portion E2 and the source-side lightly doped drain portion E1 are formed by the same process (the same mask), the impurity concentrations are equal. The impurity concentration of the lightly doped drain of the second field effect transistor 2 is also equal to the impurity concentrations of the source side lightly doped drain portion E1 and the drain side lightly doped drain portion E2.
Referring to fig. 2 and 3, fig. 2 is a diagram showing an example of each circuit formed on a silicon substrate. For example, as shown in fig. 2, a MOSFET array 3 (MOSFET row), a MOSFET circuit 4 (MOSFET circuit), and a Core logic circuit 5 (Core logic circuit) are formed on a silicon substrate. In the MOSFET arrangement 3, a plurality of first field effect transistors 1, for example, as shown in fig. 3, are provided, and the plurality of first field effect transistors 1 are adjacent to each other. Adjacent means, for example, that the elements are arranged at a minimum spacing from each other. For example, the sources S1 and the drains D1 of the adjacent first field effect transistors 1 may be connected to each other. The MOSFET circuit 4 is a region constituting a circuit using MOS elements. In the MOSFET circuit 4, elements such as capacitive elements are also arranged in mixture with MOS. The Core logic circuit refers to a logic circuit (Core logic). The first field effect transistor 1 is formed, for example, in a MOSFET array 3. The second field effect transistor 2 is formed, for example, in a MOSFET circuit 4. As shown in fig. 2, the semiconductor device 10 corresponds to multiple power supplies, for example, the MOSFET array 3 and the MOSFET circuit 4 are supplied with, for example, 6V power supply, and the core logic circuit 5 is supplied with, for example, 1.2V power supply. That is, the first field effect transistor 1 is applied to a high voltage mosfet in the semiconductor device 10. Specifically, the power supply voltage of the first field effect transistor 1 is, for example, 2.5V or more and, for example, 8V or less, and when applied to a high-voltage mosfet, the leakage current can be suppressed even in a high-voltage system.
With reference to fig. 4 to 6, the effect of the unbalanced structure of the first field effect transistor 1 will be described. Fig. 4, 5, and 6 are graphs showing simulation results of the unbalanced structure of the lightly doped drain length. In FIG. 4, the horizontal axis represents d2/d1, and the vertical axis represents the Ioff (off-current) ratio. The ordinate indicates the Ioff ratio when d2/d1 is 1 (i.e., a symmetrical structure in which d1 is d 2) as a reference (100%). In fig. 4, the drain voltage Vd becomes 8V, and the gate voltage Vg becomes 0V. In FIG. 5, the abscissa represents d2/d1, and the ordinate represents the threshold voltage Δ Vth [ mV ]. The vertical axis shows the difference from 0mV, Δ Vth in the case of d2/d1 ═ 1 (i.e. a symmetrical configuration of d1 ═ d 2) of, for example, 0 mV. In fig. 5, Vd is 0.05V. In FIG. 6, the abscissa represents d2/d1, and the ordinate represents the ratio of Idsat (saturated drain current). The ordinate axis represents the Idsat ratio when d2/d1 is 1 (i.e., a symmetric structure where d1 is d 2) as a reference (100%). In fig. 6, Vd ═ Vg ═ 8V. In fig. 4, 5, and 6, the gate length is, for example, 0.9 μm.
Referring to fig. 4 to 6, as shown in fig. 4, the larger d2/d1 (larger than the region where d2/d1 is 1), the smaller the off-current Ioff. As shown in fig. 5 and 6, it is understood that the increase in d2/d1 has a small influence on the threshold voltage Vth and the saturated drain current Idsat. For example, when d2/d1 is 9, the off-current Ioff is reduced by 25%, the threshold voltage Vth is shifted by, for example, -1 mV, and the saturated drain current Idsat is shifted by, for example, + 1.7%, compared to the case where d2/d1 is 1. Preferably, the ratio d2/d1 is greater than, for example, 1 and is, for example, 10 or less. On the other hand, for example, in the case of d2/d1 > 10, since there is a possibility that the gate overlap on the source S1 side increases and the resistance increases, it is preferable that d2/d1 be kept at 9, for example. On the other hand, the off current Ioff increases as d2 is smaller than d1 (smaller than the region where d2/d1 is equal to 1). In the case where d2 is smaller than d1, the increase rate of the off-current Ioff is large.
Referring to fig. 7 and 8, fig. 7 and 8 are graphs showing the relationship between the ratio d2/d1 and the electric field strength. Fig. 7 is a view showing the state (depth [ μm ]) of the drain side lightly doped drain portion E2 in the case where d2/d1 is changed. Fig. 7 shows the pattern of d2/d1 > 1, the pattern of d2/d1 ═ 1, and the pattern of d2/d1 < 1. Fig. 8 is a graph showing a change in electric field intensity in the depth direction at the position OL in fig. 7 where the gate G1 and the drain D1 overlap. Fig. 8 shows patterns when d2/d1 is 1.0, d2/d1 is 9.0, and d2/d1 is 0.9, respectively. The larger D2/D1, the smaller the electric field intensity at the drain D1 end compared to the case where D2/D1 is less than 1. If d2/d1 is small, the electric field is locally concentrated and increased, and if d2/d1 is large, the electric field intensity is decreased due to dispersion.
As shown in fig. 7 and 8, the leakage current can be effectively suppressed by adopting a structure of d1 < d2 as in the first field effect transistor 1. Among them, d2/d1 is preferably at least 2. More preferably, d2/d1 is not less than 6, for example. More preferably, d2/d1 is at least 9, for example. As described above, d2/d1 is preferably 10 or less. Further, the first field effect transistor 1 can suppress an increase in the footprint even in comparison with the symmetrically structured mosfet (second field effect transistor 2) by the relationship of d1 + d2 + L being 2 × d0 + L. That is, the unbalanced structure of the first field effect transistor 1 is a structure capable of suppressing an increase in the footprint and reducing the leakage current. In addition, by adopting the configuration as d1 < d2 of the first field-effect transistor 1, the risk of entering a region smaller than d2/d1, which is caused by the Lithography alignment deviation, is reduced as compared with the MOS of the symmetrical configuration as the second field-effect transistor 2, avoiding causing an increase in leakage current. In the unbalanced structure such as the first field effect transistor 1, the source side lightly doped drain portion E1 (i.e., d 1) is preferably provided because there is a possibility that the drain current will decrease when the source side lightly doped drain portion E1 is not provided.
Referring to fig. 9-11, a method for fabricating a semiconductor device 10 according to a first embodiment of the present invention is provided. In the manufacturing steps of the first manufacturing method, the same steps are performed for the first field effect transistor 1 and the second field effect transistor 2. For example, in the case where the first field effect transistor 1 is lightly doped drain implanted, the second field effect transistor 2 is also lightly doped drain implanted. The same applies to the other corresponding portions. The same applies to the second manufacturing method or the third manufacturing method described later. Fig. 9 to 11 schematically illustrate the respective manufacturing steps of the semiconductor device 10. In fig. 9 to 11, a case where the first field effect transistor 1 is formed on the left side and the second field effect transistor 2 is formed on the right side is shown as an example with reference to the direction in the drawings.
Referring to fig. 9-11, first, a shallow trench isolation sti (shallow trench isolation) with a depth of, for example, 300nm is formed on the surface of the silicon substrate. STI is a structure for separating elements, and is formed by digging a groove (trench) at a predetermined position and filling the groove with a silicon oxide film. Since the STI is formed using an insulator, each portion formed on the surface of the silicon substrate is electrically separated.
Referring to FIG. 9, a P-type impurity such as boron (B) is implanted to a concentration range of 1 × 1017/cm3~5×1017/cm3For example, after the gate oxide film OX is formed and before the gate G1 is formed, the concentration of the P-type well(s) is (are) set to, for example, 1X 1018/cm3~1×1019/cm3And implanting N-type impurities such as phosphorus (P). The gate oxide film OX is formed by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) film, a wet oxide film, a dry oxide film, or an in-situ moisture-generated oxide film (ISSG)Oxide film, In-Situ Stem Generation oxide film) or a laminated film thereof, to a film thickness of, for example, 15 nm. In the lightly doped drain implantation, ion implantation is performed in a state where a region other than a region where the lightly doped drain is formed is covered with a Photoresist mask (PR, Photoresist in fig. 9) on a surface of a silicon substrate (on a gate oxide film OX) where the mosfet is formed. The positions of the masks are designed in consideration of the regions where the source S1 and the drain D1 are to be formed. In the example of fig. 9, the first field effect transistor 1 has an unbalanced structure and the second field effect transistor 2 has a symmetrical structure with respect to the current direction in the drawing, and therefore the mask is formed to the left (toward the source S1) in the first field effect transistor 1 as compared with the second field effect transistor 2.
Referring to fig. 10, when the lightly doped drain implantation is performed and the mask is removed, as shown in fig. 10, a gate G1 is formed on the gate oxide film OX, and the gate G1 is, for example, 100nm polysilicon. In addition, a sidewall SW is also formed. In addition, in a pre-designed region, for example, an N-type impurity such As arsenic (As) is implanted to form a region having a concentration of, for example, 1X 1021/cm3Source S1 and drain D1. Thus, in the first field effect transistor 1, the source side lightly doped drain portion E1 having a lightly doped drain length d1 is formed, and the drain side lightly doped drain portion E2 having a lightly doped drain length d2 is formed. In addition, in the second field effect transistor 2, a lightly doped drain portion E0 having a lightly doped drain length d0 is formed.
As shown in fig. 11, when each element is formed, as shown in fig. 11, an insulating film IF and a contact CT are formed on the surface of the silicon substrate. Specifically, a thick silicon oxide film is formed on the surface of the silicon substrate by Chemical Vapor Deposition (CVD) or the like, thereby forming the insulating film IF. Then, a contact portion CT for wiring each terminal of the element and another element is formed. The contact portion CT is formed by forming a contact hole in the insulating film IF by etching and filling tungsten or the like in the contact hole. In this way, a CT (contact) layer is formed in the step of forming an insulating film or the like, and metal wiring or the like (metal layer) is laid on the surface of the CT layer.
Referring to fig. 9 to 11, the present invention provides a method for manufacturing a semiconductor device 10, which includes a gate forming step of forming a gate G1 of a first field effect transistor 1, a source-drain forming step of forming a source S1 and a drain D1 of the first field effect transistor 1, and a lightly doped drain implantation step of forming a source side lightly doped drain portion E1 and a drain side lightly doped drain portion E2. The source side lightly doped drain portion E1 serves as a lightly doped drain on the source S1 side of the first field effect transistor 1, and the drain side lightly doped drain portion E2 serves as a lightly doped drain on the drain side of the first field effect transistor 1.
Referring to fig. 9-11, in an embodiment of the invention, the gate forming process forms a gate oxide film OX and a gate G1, and the lightly doped drain implantation process is performed before forming a gate G1. In particular, as shown in fig. 9, in another embodiment of the present invention, the lightly doped drain implantation step is performed after the gate oxide film OX is formed and before the gate G1 is formed. In other embodiments of the present invention, the lightly doped drain implantation step may be performed before the gate oxide film OX is formed or formed, as long as the lightly doped drain implantation step is performed before the gate G1 is formed. In particular, by performing lightly doped drain implantation before forming the gate oxide film OX and the gate electrode G1 as shown in fig. 9, a lightly doped drain can be formed more efficiently in a predetermined region. Therefore, the mosfet having the unbalanced structure as in the first field effect transistor 1 can be efficiently formed.
Referring to fig. 12-14, a method of fabricating a semiconductor device 10 according to a second embodiment of the present invention is provided. Fig. 12 to 14 schematically illustrate respective manufacturing steps of the semiconductor device 10. In each of fig. 12 to 14, a case where the first field effect transistor 1 is formed on the left side and the second field effect transistor 2 is formed on the right side is shown as an example with reference to the current direction in fig. 12 to 14. Referring to fig. 12, first, shallow trench isolation sti (shallow trench isolation) with a depth of, for example, 300nm is formed on the surface of the silicon substrate. Shallow trench isolation is a structure for separating elementsAnd is formed by digging a groove (trench) at a predetermined position and filling the groove with a silicon oxide film. Since the shallow trench isolation is formed using an insulator, each portion formed on the surface of the silicon substrate is electrically separated. Then, a P-type impurity such as boron (B) is implanted on the silicon substrate to have a concentration of, for example, 1 × 1017/cm3~5×1017/cm3For example, a gate oxide film OX having a film thickness of, for example, 15nm is formed by a low-pressure chemical vapor deposition film, a wet oxide film, a dry oxide film, an in-situ moisture generation oxide film, or a stacked film thereof, and a gate G1 of, for example, 100nm polysilicon is formed on the gate oxide film OX. The gate G1 is etched into a prescribed gate pattern after the polysilicon layer is formed.
Referring to FIG. 13, an N-type impurity such as phosphorus (P) is implanted to a concentration of, for example, 1X 1018/cm3~1×1019/cm3The lightly doped drain is implanted. As shown in fig. 13, although the gate electrode G1 is etched into a predetermined shape, the gate oxide film OX is not formed into a shape corresponding to the gate electrode G1, but maintains the original shape (i.e., the shape in which the layer covers the entire device) of the layer (i.e., the film state). In the lightly doped drain implantation, ion implantation is performed in a state where a region other than the region where the lightly doped drain is formed is covered with a photoresist mask on the surface of the silicon substrate where the mosfet is formed (on the gate G1 in fig. 13). In this embodiment, the positions of the masks are designed in consideration of the regions where the source S1 and the drain D1 are to be formed. That is, as shown in fig. 13, the mask is shorter than the gate G1 in the channel length direction. In the example of fig. 13, the first field effect transistor 1 has an unbalanced structure and the second field effect transistor 2 has a symmetrical structure, based on the current direction in the drawing, and therefore the mask of the second field effect transistor 2 is formed on the left side (on the source S1) compared to the first field effect transistor 1. In the lightly doped drain implantation, impurities are implanted into the surface of the silicon substrate through the gate oxide film OX. Further, impurities near the gate G1 are implanted into the silicon substrate surface through the gate G1 and the gate oxide film OX.
Referring to FIG. 14, when the lightly doped drain implantation is performed and the mask is removedIn the removal, As shown in FIG. 14, an N-type impurity such As arsenic (As) is implanted into a region designed in advance to have a concentration of, for example, 1X 1021/cm3Source S1 and drain D1. Thus, in the first field effect transistor 1, the source side lightly doped drain portion E1 having a lightly doped drain length d1 is formed, and the drain side lightly doped drain portion E2 having a lightly doped drain length d2 is formed. In addition, in the second field effect transistor 2, a lightly doped drain portion E0 having a lightly doped drain length d0 is formed.
Referring to fig. 12-14, a second method of fabricating a semiconductor device 10 according to the present invention includes: a gate forming step of forming the gate G1 of the first field effect transistor 1, a source-drain forming step of forming the source S1 and the drain D1 of the first field effect transistor 1, and a lightly doped drain implanting step of forming the source side lightly doped drain portion E1 and the drain side lightly doped drain portion E2. The source side lightly doped drain portion E1 serves as a lightly doped drain on the source S1 side of the first field effect transistor 1, and the drain side lightly doped drain portion E2 serves as a lightly doped drain on the drain D1 side of the first field effect transistor 1. The gate forming step forms a gate oxide film OX and a gate G1, and the lightly doped drain implanting step is performed after forming (i.e., etching) a gate G1 into a predetermined gate pattern.
Referring to fig. 13 and 15, in the present embodiment, the implantation direction of the impurity is angled in the implantation of the lightly doped drain. For example, the impurity implantation is performed at an angle of, for example, 30 ° to 45 ° with respect to the stacking direction so as to easily implant the impurity into the lower portion of the gate electrode G1, and the impurity implantation into the lower portion of the gate electrode G1 is efficiently performed. As shown in fig. 15, in another embodiment of the present invention, impurity implantation may be performed without an angle with respect to the stacking direction.
Referring to fig. 16-18, a method of fabricating a semiconductor device 10 according to a third embodiment of the present invention is provided. Fig. 16 to 18 are views schematically showing the respective manufacturing steps of the semiconductor device 10. With reference to the present direction in fig. 16 to 18, in each of the drawings, a case where the first field effect transistor 1 is configured on the left side and the second field effect transistor 2 is configured on the right side is shown as an example.
Referring to fig. 16, first, a shallow trench isolation sti (shallow trench isolation) with a depth of, for example, 300nm is formed on the surface of the silicon substrate. The shallow trench isolation is a structure for separating elements, and is formed by digging a trench (trench) at a predetermined position and filling the trench with a silicon oxide film. Since the shallow trench isolation is formed using an insulator, each portion formed on the surface of the silicon substrate is electrically separated. Then, a P-type impurity such as boron (B) is implanted on the silicon substrate to have a concentration of, for example, 1 × 1017/cm3~5×1017/cm3The left and right P-type wells are formed with a gate oxide film OX by, for example, a low-pressure chemical vapor deposition film, a wet oxide film, a dry oxide film, an in-situ moisture generating oxide film, or a stacked film thereof, and a layer of, for example, 100nm polysilicon for the gate G1 is formed on the gate oxide film OX. The thickness of the gate oxide film OX is, for example, 15 nm. That is, the gate oxide film OX and the gate electrode G1 are formed.
Referring to FIG. 17, as shown in FIG. 17, an N-type impurity such as phosphorus (P) is implanted to a concentration of, for example, 1 × 1018/cm3~1×1019/cm3And injecting the left and right lightly doped drain. As shown in fig. 17, the polysilicon and gate oxide film OX used for the gate G1 are not formed (i.e., etched) in a shape corresponding to the gate G1, but remain in the original shape of the layer (the layer covering the entire device). In the lightly doped drain implantation, ion implantation is performed in a state where a region other than a region where the lightly doped drain is formed is covered with a photoresist mask (PR in fig. 17) on the surface of the silicon substrate where the MOS is formed. Here, the positions of the masks are designed in consideration of the regions where the source S1 and the drain D1 are to be formed. In the example of fig. 17, with reference to the current direction in fig. 17, since the unbalanced structure is adopted in the first field effect transistor 1 and the symmetrical structure is adopted in the second field effect transistor 2, the mask is formed further to the left (toward the source S1) in the first field effect transistor 1 than in the second field effect transistor 2. In lightly doped drain implantation, impurities pass through the polysilicon and the gateAn oxide film OX is implanted into the surface of the silicon substrate.
Referring to fig. 18, when the lightly doped drain implantation is performed and the mask is removed, as shown in fig. 18, the polysilicon and the gate oxide film OX are etched corresponding to the gate pattern. In addition, in a pre-designed region, for example, an N-type impurity such As arsenic (As) is implanted to form a region having a concentration of, for example, 1X 1021/cm3Source S1 and drain D1. Thus, in the first field-effect transistor 1, the source side lightly doped drain portion E1 having a lightly doped drain length d1 is formed, and the drain side lightly doped drain portion E2 having a lightly doped drain length d2 is formed. In addition, in the second field effect transistor 2, a lightly doped drain portion E0 having a lightly doped drain length d0 is formed.
As shown in fig. 1 and 16 to 18, when each element is formed, an insulating film IF and a contact CT are formed. Specifically, a thick silicon oxide film is formed on the surface of the silicon substrate by chemical vapor deposition or the like to form the insulating film IF. Then, a contact portion CT for wiring each terminal of the element and another element is formed. The contact portion CT is formed by forming a contact hole in the insulating film IF by etching and filling tungsten or the like in the contact hole. In this way, a CT (contact) layer is formed in the step of forming an insulating film or the like, and metal wiring or the like (metal layer) is laid on the surface of the CT layer.
Referring to fig. 16-18, a third method of manufacturing a semiconductor device 10 according to the present invention includes: a gate forming step of forming the gate G1 of the first field effect transistor 1, a source-drain forming step of forming the source S1 and the drain D1 of the first field effect transistor 1, and a lightly doped drain implanting step of forming the source side lightly doped drain portion E1 and the drain side lightly doped drain portion E2. The gate forming step forms a gate oxide film OX and a gate electrode G1, and the lightly doped drain implantation step is performed after the gate electrode G1 is formed and before the gate electrode G1 is formed into a predetermined gate pattern. The source side lightly doped drain portion E1 serves as a lightly doped drain on the source S1 side of the first field effect transistor 1, and the drain side lightly doped drain portion E2 serves as a lightly doped drain on the drain D1 side of the first field effect transistor 1.
Referring to fig. 3, 18-20, fig. 19 shows a block diagram of a source driver. The source driver includes, for example, a shift register, a level shifter, a sample-and-hold circuit, and an output buffer circuit. In the output buffer circuit, the MOS used are arranged at a minimum interval as shown in fig. 3, for example. Fig. 20 is a diagram showing an example of an output buffer circuit. In fig. 18, 192 inputs and outputs are provided, and fig. 20 is a circuit showing a combination of one of the inputs and the output. As shown in fig. 20, a signal is output from the input terminal VIN to the output terminal VOUT via the buffer BF and the inverter INV (P-type metal oxide semiconductor field effect transistor and N-type metal oxide semiconductor field effect transistor). The first field effect transistor 1 is applied to an N-type metal oxide semiconductor field effect transistor in the inverter INV. In the output buffer circuit, for example, 192 circuits shown in fig. 20 are arranged to suppress leakage current and suppress circuit area by using N-type metal oxide semiconductor field effect transistors and adopting an unbalanced configuration as the first field effect transistor 1.
Referring to fig. 18 to 20, the present invention provides a semiconductor device and a method for manufacturing the same, in which the lightly doped drain length of the drain side lightly doped drain portion E2 is greater than the lightly doped drain length of the source side lightly doped drain portion E1, so as to effectively suppress the leakage current. Further, the lightly doped drain length of the source side lightly doped drain portion E1 is made smaller than the lightly doped drain length of the lightly doped drain provided in the second field effect transistor 2, and the lightly doped drain length of the drain side lightly doped drain portion E2 is made larger than the lightly doped drain length of the lightly doped drain provided in the MOS2, so that the first field effect transistor 1 can be suppressed in circuit area increase as compared with the second field effect transistor 2. That is, the first field effect transistor 1 can reduce the leakage current while suppressing an increase in area as compared with the second field effect transistor 2.
In the description of the present specification, reference to the description of the terms "present embodiment," "example," "specific example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended to be merely illustrative. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (15)
1. A semiconductor device, comprising:
a first field effect transistor; and
a second field effect transistor;
setting a lightly doped drain electrode at the source side of the first field effect transistor as a source side lightly doped drain electrode part, setting a lightly doped drain electrode at the drain side of the first field effect transistor as a drain side lightly doped drain electrode part, and setting the length of the lightly doped drain electrode at the drain side lightly doped drain electrode part to be larger than the length of the lightly doped drain electrode at the source side lightly doped drain electrode part;
the lightly doped drain length of the source side lightly doped drain part is less than that of the lightly doped drain arranged on the second field effect transistor, and the lightly doped drain length of the drain side lightly doped drain part is greater than that of the lightly doped drain arranged on the second field effect transistor;
wherein channel lengths of the first field effect transistor and the second field effect transistor are equal.
2. The semiconductor device according to claim 1, wherein a length obtained by adding a lightly doped drain length of the source side lightly doped drain portion and a lightly doped drain length of the drain side lightly doped drain portion is 2 times a length of a lightly doped drain provided in the second field effect transistor.
3. The semiconductor device according to claim 1 or 2, wherein a depth of the source-side lightly doped drain portion is equal to a depth of the drain-side lightly doped drain portion.
4. The semiconductor device according to claim 1 or 2, wherein an impurity concentration of the source-side lightly doped drain portion is equal to an impurity concentration of the drain-side lightly doped drain portion.
5. A semiconductor device according to claim 1 or 2, wherein a plurality of the first field-effect transistors are provided in the semiconductor device, and the plurality of the first field-effect transistors are adjacent to each other.
6. The semiconductor device according to claim 5, wherein a plurality of the first field-effect transistors are provided, sources of the plurality of the first field-effect transistors are connected to each other, and drains of the plurality of the first field-effect transistors are connected to each other.
7. The semiconductor device according to claim 1, wherein the first field effect transistor is a high-voltage metal oxide semiconductor field effect transistor, and wherein a power supply voltage is 2.5V or more and 8V or less.
8. A semiconductor device according to claim 1, wherein the first field effect transistor constitutes an output buffer circuit.
9. The semiconductor device according to claim 1 or 2, wherein the lightly doped drain length of the source side lightly doped drain portion is d1, and the lightly doped drain length of the drain side lightly doped drain portion is d2, and d2/d1 is 2 or more.
10. The semiconductor device according to claim 1 or 2, wherein the lightly doped drain length of the source side lightly doped drain portion is d1, and the lightly doped drain length of the drain side lightly doped drain portion is d2, and d2/d1 is 6 or more.
11. The semiconductor device according to claim 1 or 2, wherein the lightly doped drain length of the source side lightly doped drain portion is d1, and the lightly doped drain length of the drain side lightly doped drain portion is d2, and wherein d2/d1 is 9 or more.
12. A method of manufacturing a semiconductor device including a first field effect transistor and a second field effect transistor, comprising:
a gate formation step of forming a gate of the first field effect transistor;
a source-drain formation step of forming a source and a drain of the first field effect transistor; and
a lightly doped drain injection step of forming a source side lightly doped drain portion as a lightly doped drain on a source side of the first field effect transistor and a drain side lightly doped drain portion as a lightly doped drain on a drain side of the first field effect transistor;
the lightly doped drain length of the drain side lightly doped drain part is greater than that of the source side lightly doped drain part;
the lightly doped drain length of the source side lightly doped drain part is less than that of the lightly doped drain arranged on the second field effect transistor, and the lightly doped drain length of the drain side lightly doped drain part is greater than that of the lightly doped drain arranged on the second field effect transistor;
wherein channel lengths of the first field effect transistor and the second field effect transistor are equal.
13. The method for manufacturing a semiconductor device, according to claim 12, wherein the gate forming step forms a gate oxide film and a gate electrode, and the lightly doped drain implanting step is performed before the gate electrode is formed.
14. The method of manufacturing a semiconductor device according to claim 12, wherein the gate forming step forms a gate oxide film and a gate electrode, and wherein the lightly doped drain implanting step is performed after the gate electrode is formed into a predetermined gate pattern.
15. The method of manufacturing a semiconductor device according to claim 12, wherein the gate forming step forms a gate oxide film and a gate electrode, and wherein the lightly doped drain implantation step is performed after the gate electrode is formed and before the gate electrode is formed into a predetermined gate pattern.
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