CN1141502A - Method of forming internallic insulating layers in semiconductor devices - Google Patents
Method of forming internallic insulating layers in semiconductor devices Download PDFInfo
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- CN1141502A CN1141502A CN96104047A CN96104047A CN1141502A CN 1141502 A CN1141502 A CN 1141502A CN 96104047 A CN96104047 A CN 96104047A CN 96104047 A CN96104047 A CN 96104047A CN 1141502 A CN1141502 A CN 1141502A
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- insulating barrier
- concentration
- teos
- thickness
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A method of forming an intermetallic insulating film of a semiconductor device is disclosed. The method not only has superior ashesiveness and uniform step-coverage, but also prevents forming airgap formed by penetration of damp. According to the method, metal interlinkage is formed on semiconductor substrate firstly. And then, a first insulation layer is formed by reaction of tetraethylorthosilicate(TEOS)gas of preset amount and O[3] gas of the preset concentration in CVD furnace to make thickness enough to fill the space between the metal interlinkage. Subsequently, a second insulation layer of preset thickness is formed on the first insulation layer using the same furnace only changing the concentration of TEOS.
Description
The present invention relates to make the method for semiconductor device, more particularly, relate to the method that in having the metal interconnected semiconductor device of multilevel hierarchy, forms internallic insulating layers.
Along with the raising of semiconductor device integrated level, require metal interconnected semiconductor device with multilayer.In making semiconductor device, the interval between every layer the metal wire and two-layer between the interval should be with the intermetallic insulating barrier insulation of the dielectric material of for example oxide or nitride and so on.Requirement to high-quality internallic insulating layers is: anti-outlet capacity; To metal interconnected high tack; And step is topped uniformly.Use for example boron phosphorus silicate glass (BPSG) at present always, glass fibre (spin on glass) (SOG) and these dielectric materials of tetraethyl orthosilicate (TEOS) as internallic insulating layers.
When using BPSG, need a kind of additional reflow treatment as internallic insulating layers.Thereby, exist in the layer the interstitial problem in precalculated position, inside.Simultaneously, when using SOG, then owing to penetrating of moisture causes metal interconnected corrosion as insulating barrier.Its reason be because layer itself to have the tack of a large amount of moistures and it and metal level also poor.
Except that above-mentioned material, also proposed to use the method for TEOS film as insulating barrier.This method makes tetraethyl orthosilicate (TEOS) gas and O
3Gas reacts and forms the TEOS film.This method is full of the interval between the metal wire easily, because the TEOS film has improved the effect of surface reaction, itself can directly absorb moisture from air but the TEOS film that forms comprises a large amount of moistures and layer.Metal interconnected surface is passed by the hydrogen atom group that is present in the moisture, causes the stress changes of formed layer.If this change is serious, then rupture at the formed layer of predetermined thickness.
Thereby, the object of the present invention is to provide a kind of method that is used in semiconductor device, forming insulating barrier between the metal, it not only has good tack and step covering uniformly, and can avoid owing to penetrating of moisture causes the space.
For realizing purpose of the present invention, at first on Semiconductor substrate, form metal interconnected.Then, form first insulating barrier, its thickness makes it possible to be filled in fully the interval between the metal interconnected line in one deck.This insulating barrier itself by making predetermined concentration the teos gas body and the O of predetermined concentration
3Gas reacts in the CVD stove and makes.Then, on first insulating barrier, use identical CVD stove to form second insulating barrier, only be to use the TEOS of variable concentrations with predetermined thickness.
Preferably form first insulating barrier like this: be the O of 3.0 to 5.0mol wt% with concentration
3, deposition temperature is 360 to 420 ℃, the concentration of TEOS is 1.0 to 2.0slpm.In addition, preferably form second insulating barrier like this: working concentration is the O of 3.0 to 5.0mol wt%
3, deposition temperature is 360 to 420 ℃, the concentration of TEOS less than 1.0 to 2.0slpm.
The thickness of best first insulating barrier is 6,000 or higher, and the thickness of second insulating barrier is preferably 1,000 or less than 1000 .
Fig. 1 is the experimental result table that carries out for the physical property of measuring the TEOS film that forms.Be intended to seek the only condition that forms first insulating barrier.
Fig. 2 is the curve that film thickness changes with deposition time, and its formation temperature is 390 ℃, and the supply of TEOS gas is 1.3slpm, O
3Concentration be 130g/m
3
Fig. 3 is the curve of deposition rate of the film of expression deposit, the supply stuck-at-.3slpm of the TEOS gas of this moment, and O
3Concentration change by formation temperature.
Fig. 4 is the curve that the deposition rate of TEOS film changes with the supply of TEOS gas.
Fig. 5 is the SEM micrograph of semiconductor device, wherein is formed with internallic insulating layers according to embodiments of the invention.
The following describes most preferred embodiment of the present invention, but this does not constitute the restriction to the present invention's design.
The insulating barrier that is used for the insulated metal interconnection of the present invention is divided into two parts.In other words, have first insulating barrier that is used for being full of fully the interval between the metal wire in one deck metal interconnected and second insulating barrier that is used for covering metal interconnected and first insulating barrier.Two-layer have different performances, depends on formation method separately.
The present invention is described in more detail below.
At first on Semiconductor substrate, form metal interconnected by deposit and formation metallic pattern.Then, make TEOS gas and O by the chemical vapor deposition method
3Gas reacts, and forms the one the second insulating barriers in order.
TEOS gas is one of raw material that forms insulating barrier.
Described first insulating barrier is such formation: be the O of 3.0 to 5.0mol wt% with concentration
3Formation temperature is 360 to 420 ℃, and TEOS concentration is 1.0 to 2.0slpm.Preferably form first insulating barrier like this, make the interval between its metal interconnected middle metal wire that is filled in one deck fully, thereby improve or keep the performance of semiconductor device.In the present embodiment, the thickness of first insulating barrier is 6000 .
Then form second insulating barrier of predetermined thickness on first insulating barrier, wherein second insulating barrier has the physical property that is different from first insulating barrier.The reacting furnace of first insulating barrier preferably and second insulating barrier be same so that the contacting of the moisture that exists in minimizing and the air.
The formation condition of second insulating barrier remove outside the concentration of TEOS should be with first insulating barrier identical.That is O,
3Concentration be 3.0 to 5.0mol wt%; deposition temperature is 360 to 420 ℃, and these are identical with first insulating barrier, and the concentration of TEOS is 0.5slpm or lower; it is lower than the concentration of first insulating barrier, and the thickness of second insulating barrier should be controlled at 1000 or below 1000 .
Fig. 1 is that expression is measured the physical property gained result's of formed TEOS film table in order to seek the appropraite condition that forms first insulating barrier.
In order to form first insulating barrier that thickness is 6000 , making formation temperature respectively is 360,390 and 420 ℃, and TEOS gas supply is 1.3,2.3 and 3.3slpm, O
3Concentration be 70g/m
3(=3.27mol wt%), 100g/m
3(=4.66mol wt%).
Under these conditions, in order to obtain the stress changes rate, measure stress and shrinkage in the thickness of first insulating barrier that forms.In addition, also measure deposition thickness, the uniformity, the deposition rate of per minute, reflection coefficient (R.I), evenness and consistency.
Shown in the result as follows: 1.3 to 1.4% low stress change rate under 420 ℃ high temperature; 17 to 24% heavily stressed change rate and about 0.5% low thickness shrinkage under 420 ℃ high temperature; And at 360 and 390 ℃ down 0.2% with interior low-down thickness shrinkage.When the concentration of given TEOS is 1.3slpm, when deposition temperature is 360 and 420 ℃, according to O
3The shrinkage of concentration first insulating barrier as follows.
For deposition temperature is 360 ℃, O
3Concentration be 70g/m
3, 100g/m
3And 130g/m
3, shrinkage is respectively 1.60,1.23 and 1.86%.In addition, be 420 ℃ for deposition temperature, O
3Concentration is 70g/m
3, 100g/m
3And 130g/m
3, shrinkage is respectively 0.35,0.12 and 0.52%.Like this, as given O
3Concentration is 130g/m
3The time, the change rate that shows is a high relatively value.
From The above results as seen, work as O
3Concentration be 130g/m
3Situation under because in layer, exist a large amount of moistures to determine that formed layer is a porous.Because the combination densely of the constituting atom of insulating barrier, so show excellent physical property.Thereby, O
3Concentration be 130g/m
3Situation in only scope of the present invention, got rid of.
In addition, be the suitable quantity delivered of 390 ℃ TEOS gas in order to determine for deposition temperature, O
3Concentration is 100g/m
3, and TEOS gas supply is 1.3,2.3, and 3.3slpm, the thickness shrinkage is respectively 0.52,1.20 and 1.50%.This result shows that TEOS concentration is 2.3, and 3.3slpm is that 1.3 formed layers are more loose than TEOS concentration, because the former has relatively large moisture than the latter.When the constituting atom of insulating barrier by densely in conjunction with the time, just show good physical property.Thereby, 2.3 and the situation of 3.3slpm in OK range of the present invention, got rid of.
Be used for the thickness that most of sample of the present invention approaches thick 6000 of appointment.Conforming value is 0.89 to 2.59%.At deposition temperature is 390 ℃, and TEOS gas supply is 3.3slpm, O
3Deposition rate had peak when concentration was 4.66mol wt%.Reflection coefficient when deposit first insulating barrier is almost identical with the reflection coefficient of annealing after 30 minutes.Evenness when deposition temperature is 420 ℃ (planarity) is much at one and for maximum.The consistency scope is 10 to 41%.In addition, TEOS gas supply is 1.35slpm and O
3Concentration be 4.6mol wt%.
Fig. 2 be when formation temperature be 390 ℃, TEOS gas supply is 1.3slpm, and O
3Concentration be 130g/m
3The time thickness with the change curve of deposition time.
Deposition thickness increases linearly with deposition time as shown in Figure 2.Therefore, be defined as obtaining 6000A or the bigger required deposition time of thickness was at least 560 seconds or longer.
Fig. 3 is that dense the crossing of working as TEOS is fixed as 1.3slpm, changes O
3Concentration the time deposited film the curve that changes by formation temperature of deposition rate.
As shown in Figure 3, work as O
3When concentration increased, the deposition rate of per minute reduced.And, showing in given temperature range, the deposition rate when the deposition rate ratio is at low temperature when high temperature is low.
Fig. 4 is the curve that the deposition rate of TEOS film changes with TEOS gas supply.As shown in Figure 4, when the amount of IEOS increased, deposition rate increased linearly.
Fig. 5 is the SEM micrograph of semiconductor device, wherein is formed with the internallic insulating layers by embodiments of the invention.
As shown in the figure, there is not the space to take place.So just, moisture entrance composition or hydrogen atom group determining in the layer that forms, not resemble in the routine techniques.
Described in detail as former, internallic insulating layers of the present invention is made of two-layer, and they have the performance that differs from one another.In addition, they not only have the physical property of OK range, and can stop penetrating of moisture.Thereby the present invention can reduce the generation in space and the variation of stress, and these are cause faults in the semiconductor device.In addition, the present invention not only provides and has suppressed the phenomenon that the space takes place, but also has improved output, because dielectric layers forms in same stove.
To find out more significantly after its its feature of the inventive embodiment of Pi Luing and advantage those of ordinary skill in the art explanation on read herein.In this respect, though understand specific embodiment of the present invention quite in detail, these embodiment can be modified and retrofit under the situation that does not break away from design of the present invention.
Claims (4)
1, a kind of method that forms internallic insulating layers in the semiconductor device comprises routine step down:
On Semiconductor substrate, form metal interconnected;
In the chemical vapor deposition stove, make the teos gas body of scheduled volume and the O of scheduled volume
3Gas reacts and forms first insulating barrier and can fully be full of interval between metal interconnected to its thickness; And
On first insulating barrier, in same stove, form second insulating barrier of predetermined thickness, compare the concentration that only changes TEOS when its formation condition and formation first insulating barrier.
2, method as claimed in claim 1, wherein said first insulating barrier are the O of 3.0 to 5.0mol wt% in concentration
3, deposition temperature is 360 to 420 ℃, the concentration of TEOS is to form under 1.0 to 2.0slpm the condition.
3, method as claimed in claim 1, wherein said second insulating barrier are the O of 3.0 to 5.Omol wt% in concentration
3, deposition temperature is 360 to 420 ℃, TEOS concentration forms under the condition less than 0.5slpm.
4, method as claimed in claim 1, the thickness of wherein said first insulating barrier be 6000 or more than, the thickness of second insulating barrier is 1000 or littler.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR444/95 | 1995-03-04 | ||
| KR1019950004444A KR0144227B1 (en) | 1995-03-04 | 1995-03-04 | Method of contact forming |
| KR444/1995 | 1995-03-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1141502A true CN1141502A (en) | 1997-01-29 |
| CN1072839C CN1072839C (en) | 2001-10-10 |
Family
ID=19409228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96104047A Expired - Fee Related CN1072839C (en) | 1995-03-04 | 1996-03-04 | Method of forming internallic insulating layers in semiconductor devices |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR0144227B1 (en) |
| CN (1) | CN1072839C (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03175632A (en) * | 1989-12-04 | 1991-07-30 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH0680657B2 (en) * | 1989-12-27 | 1994-10-12 | 株式会社半導体プロセス研究所 | Method for manufacturing semiconductor device |
-
1995
- 1995-03-04 KR KR1019950004444A patent/KR0144227B1/en not_active IP Right Cessation
-
1996
- 1996-03-04 CN CN96104047A patent/CN1072839C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1072839C (en) | 2001-10-10 |
| KR960035798A (en) | 1996-10-28 |
| KR0144227B1 (en) | 1998-08-17 |
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Owner name: HYNIX SEMICONDUCTOR INC. Free format text: FORMER NAME OR ADDRESS: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
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Address after: Gyeonggi Do, South Korea Patentee after: Hairyoksa Semiconductor Co., Ltd. Address before: Gyeonggi Do, South Korea Patentee before: Hyundai Electronics Industries Co., Ltd. |
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