CN114121656B - 一种基于硅衬底的新型hemt器件的制备方法及器件 - Google Patents
一种基于硅衬底的新型hemt器件的制备方法及器件 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 14
- 239000010703 silicon Substances 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 53
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 230000006911 nucleation Effects 0.000 claims abstract description 16
- 238000010899 nucleation Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 82
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 238000005229 chemical vapour deposition Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 5
- 230000008025 crystallization Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 6
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000011049 filling Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 30
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 8
- 239000010409 thin film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052742 iron Inorganic materials 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 239000000370 acceptor Substances 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Abstract
本发明公开了一种基于硅衬底的新型HEMT器件的制备方法,涉及半导体技术领域,通过上述方法获得了器件,该器件包括衬底、AlN成核层、超晶格缓冲层、UID‑GaN层、GaN缓冲层、掺硅的AlGaN背势垒层、GaN沟道层、第二AlGaN势垒层、GaN沟道层、第一AlGaN势垒层、栅介质层、漏电极、源电极、栅极以及Si3N4钝化层,GaN缓冲层由UID‑GaN、掺碳GaN和掺铁GaN薄层周期性循环生长而成,本发明在AlGaN/GaN异质结外延过程中采用超晶格作为底层缓冲层,可以减少GaN材料与Si衬底的晶格不匹配,此外,通过在超晶格缓冲层上刻蚀大于或等于6个凹孔并在凹孔内填充UID‑GaN,可以进一步减少GaN材料与Si衬底晶格不匹配产生的应力,同时又能减少Si衬底外延时的翘曲以及电流崩塌,从而提高AlGaN/GaN HEMT器件的横向击穿电压。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种基于硅衬底的新型HEMT器件的制备方法及利用该方法获得的器件。
背景技术
与传统的传统的硅基功率器件相比,GaN功率器件具有耐高温、耐高压、抗强辐射以及高功率等优势。同时,AlGaN/GaN等异质结界面处可以产生高浓度以及高迁移率的的二维电子气,不需要掺n型或p型杂质即可形成导电沟道,在未来具有极高的应用价值。
GaN功率器件经过理论研究具有相当高的击穿电压,但实际上由于工艺以及不同材料之间的失配,GaN功率器件现有击穿电压远达不到理论水平。主要原因有:
一、电场集中效应,栅极靠近漏极侧的电场强度达到最大有一个电场强度峰值,使器件提前击穿。
二、电流在缓冲区会有泄露,从源极流过的电子经过缓冲区流向漏极形成回路,使器件提前击穿。
为了解决上述问题,一般采用的方法有将缓冲层掺碳或铁杂质,这是由于MOCVD生长GaN不可避免地引入背景n型掺杂剂,例如氮空位和氧杂质和碳杂质,UID-GaN缓冲层具有不足的电阻率,这可能导致寄生泄漏路径,增加关态泄漏电流。掺碳GaN通过产生受主陷阱来降低背景载流子浓度,提高缓冲层的电阻率,从而提高击穿电压,但是这会降低结晶质量,它们也像陷阱一样充当受体,导致电流崩塌,击穿电压提高幅度有限。也可采用铁掺杂来俘获背景载流子,若采用单一铁掺杂,由于铁源存在记忆效应,在外延生长过程中会影响沟道和势垒生长。因此如何有效提升GaN材料结晶质量的同时有效降低背景载流子浓度是高质量高阻外延生长研究的关键。
发明内容
本发明的目的在于提供一种基于硅衬底的新型HEMT器件的制备方法及利用该方法获得的器件,以解决现有技术中导致的上述缺陷。
一种基于硅衬底的新型HEMT器件的制备方法,包括如下步骤:
(1)在衬底上生长AlN成核层,生长温度1000-1100℃,薄膜厚度10-300nm,生长压力为50-300mbar,用于为后续的GaN缓冲层生长提供成核节点,提高GaN薄膜结晶质量;
(2)在AlN成核层基础上,采用金属有机源化学气相沉积(MOCVD)或其他方法非故意掺杂生长形成的超晶格缓冲层,薄膜厚度范围为100nm-10um;
(3)在超晶格缓冲层生长一定厚度后从MOCVD中取出,通过光刻和湿法腐蚀的方法对已生长的超晶格缓冲层进行选区腐蚀,形成方块型凹孔,刻蚀深度为50nm-5um;
(4)采用金属有机源化学气相沉积方法在超晶格缓冲层凹孔里生长UID-GaN薄膜层,生长厚度为50nm-5um;
(5)在UID-GaN薄膜层生长结束后采用光刻自对准方法,干法刻蚀掉凹孔之外的UID-GaN薄膜层,凹孔之外的UID-GaN薄膜层被刻蚀后再送回MOCVD设备生长GaN缓冲层;
(6)在上一步骤形成的结构的基础上采用金属有机源化学气相沉积方法自下而上生长掺Si的AlGaN背势垒层、氮化镓沟道层、第二AlGaN势垒层、氮化镓沟道层以及第一AlGaN势垒层;
(7)采用金属有机源化学气相沉积方法在最上层的AlGaN势垒层上生长栅介质层,然后再栅介质层上形成栅电极;
(8)采用电子束蒸发钛、铝、镍、金来沉积用于源极/漏极欧姆接触的钛/铝/镍/金金属层,随后在N2环境中快速热退火,最终形成漏电极和源电极,钛/铝/镍/金金属层的厚度为10-20nm;
(9)在源电极与栅极之间、漏电极与栅极之间均形成有Si3N4钝化层。
进一步地,所述衬底采用Si材料,也可以采用其他材料,如金刚石。
进一步地,所述步骤(2)中所述超晶格缓冲层由大于等于5对两种不同Al摩尔分数的AlxGa1-xN和AlyGa1-yN周期性生长而成,0<=x,y<=1。
进一步地,所述步骤(3)中选区生长的区数大于等于6个。
进一步地,所述步骤(5)中GaN缓冲层采用金属有机源化学气相沉积方法获得,薄膜厚度范围为100nm-10um。
进一步地,所述步骤(5)中GaN缓冲层的生长过程依次按照以下三个步骤循环生长不小于6个周期:
a)采用金属有机源化学气相沉积方法生长UID-GaN薄膜层;
b)采用金属有机源化学气相沉积方法生长10-100nm掺碳GaN薄膜;
c)采用金属有机源化学气相沉积方法生长10-100nm掺铁GaN薄膜。
所述步骤(6)中的AlGaN势垒层采用AlxGa1-xN势垒层,其中0<=x<=1。
依据上述方法制备出的HEMT器件,该器件包括自下而上依次排布的衬底、AlN成核层、超晶格缓冲层、UID-GaN层、GaN缓冲层、AlGaN背势垒层、GaN沟道层、第二势垒层、GaN沟道层、第一势垒层、栅介质层,分布于两端的漏电极和源电极,设置于AlGaN势垒层三顶部的栅极以及源电极与栅极之间、漏电极与栅极之间的Si3N4钝化层。
本发明的优点在于:
(1)本发明的器件在AlGaN/GaN异质结外延过程中采用超晶格作为底层缓冲层,可以减少GaN材料与Si衬底的晶格不匹配,此外,通过在超晶格缓冲层上刻蚀大于或等于6个凹孔并在凹孔内填充UID-GaN,可以进一步减少GaN材料与Si衬底晶格不匹配产生的应力,同时又能减少Si衬底外延时的翘曲以及电流崩塌,从而提高AlGaN/GaN HEMT器件的横向击穿电压。
(2)在超晶格缓冲层之上生长了特制的GaN缓冲层,GaN缓冲层由UID-GaN、掺碳GaN和掺铁GaN薄层周期性循环生长而成,周期型掺杂可以提高GaN缓冲层的电阻率并减小电流崩塌,从而又进一步提高击穿电压;掺碳GaN缓冲层、掺铁GaN缓冲层结合UID-GaN缓冲层能补偿GaN缓冲层中背景电子同时它也比单一掺碳或者掺铁缓冲层的结晶质量高。
(3)AlGaN背势垒层由掺Si的AlGaN组成,其降低了栅极和漏极之间沿GaN沟道的电场,抑制了缓冲区中碳诱导的受主陷阱对沟道二维电子气的俘获,增加沟道中二维电子气密度,减少了电流崩塌。
(4)采用双沟道AlGaN/GaN异质结HEMT,横向击穿电压得以再次提高,适合应用于大功率器件。
附图说明
图1为本发明的结构示意图。
图2为形成超晶格缓冲层后的示意图。
图3为在超晶格缓冲层凹孔里生长UID-GaN薄膜层后的示意图。
图4为在UID-GaN薄膜层上生长GaN缓冲层的示意图。
图5为循环生长GaN缓冲层的示意图。
其中:101衬底,102AlN成核层,103超晶格缓冲层,104UID-GaN薄膜层,105GaN缓冲层,106第二AlGaN势垒层,107GaN沟道层,108第一AlGaN势垒层,109AlGaN势垒层,110栅介质层,111源极,112漏极,114Si3N4钝化层,113栅极。
具体实施方式
为使本发明实现的技术手段、创作特征、达成目的与功效易于明白了解,下面结合具体实施方式,进一步阐述本发明。
实施例1
(1)在Si衬底101上生长AlN成核层102,生长温度1000℃,薄膜厚度10nm,生长压力为50mbar,用于为后续的GaN缓冲层105生长提供成核节点,提高GaN薄膜结晶质量;
(2)在AlN成核层102基础上,采用金属有机源化学气相沉积(MOCVD)或其他方法非故意掺杂生长形成的超晶格缓冲层103,如图2所示,薄膜厚度范围为100nm,所述超晶格缓冲层103由大于等于5对两种不同Al摩尔分数的AlxGa1-xN和AlyGa1-yN周期性生长而成,0<=x,y<=1;
(3) 在超晶格缓冲层103生长一定厚度后从MOCVD中取出,通过光刻和湿法腐蚀的方法对已生长的超晶格缓冲层103进行选区腐蚀,形成方块型凹孔,刻蚀深度为50nm;
(4) 采用金属有机源化学气相沉积方法在超晶格缓冲层103凹孔里生长UID-GaN薄膜层104,生长厚度为50nm;
(5) 在UID-GaN薄膜层104生长结束后采用光刻自对准方法,干法刻蚀掉凹孔之外的UID-GaN薄膜层104,如图3所示,凹孔之外的UID-GaN薄膜层104被刻蚀后再送回MOCVD设备生长GaN缓冲层105,如图4所示;
(6)在上一步骤形成的结构的基础上采用金属有机源化学气相沉积方法自下而上生长掺Si的AlGaN背势垒层106、氮化镓沟道层107、第二AlGaN势垒层108、氮化镓沟道层107以及第一AlGaN势垒层109,两个AlGaN势垒层采用均AlxGa1-xN势垒层,其中0<=x<=1。
(7) 采用金属有机源化学气相沉积方法在最上层的AlGaN势垒层上生长栅介质层110,然后再栅介质层110上形成栅电极;
(8) 采用电子束蒸发钛、铝、镍、金来沉积用于源极111/漏极112欧姆接触的钛/铝/镍/金金属层,随后在N2环境中快速热退火,最终形成漏电极和源电极,钛/铝/镍/金金属层的厚度为10nm;
(9)在源电极与栅极113之间、漏电极与栅极113之间均形成有Si3N4钝化层114。
进一步地,所述步骤(3)中选区生长的区数大于等于6个。
进一步地,所述步骤(5)中GaN缓冲层105采用金属有机源化学气相沉积方法获得,薄膜厚度范围为100nm,其生长过程依次按照以下三个步骤循环生长不小于6个周期,如图5所示:
a)采用金属有机源化学气相沉积方法生长UID-GaN薄膜层104;
b)采用金属有机源化学气相沉积方法生长10nm掺碳GaN薄膜;
c)采用金属有机源化学气相沉积方法生长10nm掺铁GaN薄膜。
实施例2
其余与实施例1相同,不同之处在于:AlN成核层102,生长温度1050℃,薄膜厚度205nm,生长压力为185mbar;超晶格缓冲层103,薄膜厚度范围为1um;步骤(3)中刻蚀深度为1um;步骤(4)中UID-GaN薄膜层104生长厚度为1um;钛/铝/镍/金金属层的厚度为15nm;步骤b)中采用金属有机源化学气相沉积方法生长50nm掺碳GaN薄膜;步骤c) 中采用金属有机源化学气相沉积方法生长50nm掺铁GaN薄膜。
实施例3
其余与实施例1相同,不同之处在于:AlN成核层102,生长温度1100℃,薄膜厚度300nm,生长压力为300mbar;超晶格缓冲层103,薄膜厚度范围为10um;步骤(3)中刻蚀深度为5um;步骤(4)中UID-GaN薄膜层104生长厚度为5um;钛/铝/镍/金金属层的厚度为20nm;步骤b)中采用金属有机源化学气相沉积方法生长100nm掺碳GaN薄膜;步骤c) 中采用金属有机源化学气相沉积方法生长100nm掺铁GaN薄膜。
由技术常识可知,本发明可以通过其它的不脱离其精神实质或必要特征的实施方案来实现。因此,上述公开的实施方案,就各方面而言,都只是举例说明,并不是仅有的。所有在本发明范围内或在等同于本发明的范围内的改变均被本发明包含。
Claims (8)
1.一种基于硅衬底的新型HEMT器件的制备方法,其特征在于,包括如下步骤:
(1)在衬底(101)上生长AlN成核层(102),生长温度1000-1100℃,薄膜厚度10-300nm,生长压力为50-300mbar,用于为后续的GaN缓冲层(105)生长提供成核节点,提高GaN薄膜结晶质量;
(2)在AlN成核层(102)基础上,采用金属有机源化学气相沉积(MOCVD)或其他方法非故意掺杂生长形成的超晶格缓冲层(103),薄膜厚度范围为100nm-10um;
(3) 在超晶格缓冲层(103)生长一定厚度后从MOCVD中取出,通过光刻和湿法腐蚀的方法对已生长的超晶格缓冲层(103)进行选区腐蚀,形成方块型凹孔,刻蚀深度为50nm-5um;
(4) 采用金属有机源化学气相沉积方法在超晶格缓冲层(103)凹孔里生长UID-GaN薄膜层(104),生长厚度为50nm-5um;
(5) 在UID-GaN薄膜层(104)生长结束后采用光刻自对准方法,干法刻蚀掉凹孔之外的UID-GaN薄膜层(104),凹孔之外的UID-GaN薄膜层(104)被刻蚀后再送回MOCVD设备生长GaN缓冲层(105);
(6) 在上一步骤形成的结构的基础上采用金属有机源化学气相沉积方法自下而上生长掺Si的AlGaN背势垒层(106)、氮化镓沟道层(107)、第二AlGaN势垒层(108)、氮化镓沟道层(107)以及第一AlGaN势垒层(109);
(7) 采用金属有机源化学气相沉积方法在最上层的AlGaN势垒层上生长栅介质层(110),然后再栅介质层(110)上形成栅电极;
(8) 采用电子束蒸发钛、铝、镍、金来沉积用于源极(111)/漏极(112)欧姆接触的钛/铝/镍/金金属层,随后在N2环境中快速热退火,最终形成漏电极和源电极,钛/铝/镍/金金属层的厚度为10-20nm;
(9)在源电极与栅极(113)之间、漏电极与栅极(113)之间均形成有Si3N4钝化层。
2.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述衬底(101)采用Si材料。
3.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述步骤(2)中所述超晶格缓冲层(103)由大于等于5对两种不同Al摩尔分数的AlxGa1-xN和AlyGa1-yN周期性生长而成,0<=x,y<=1。
4.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述步骤(3)中选区生长的区数大于等于6个。
5.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述步骤(5)中GaN缓冲层(105)采用金属有机源化学气相沉积方法获得,薄膜厚度范围为100nm-10um。
6.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述步骤(5)中GaN缓冲层(105)的生长过程依次按照以下三个步骤循环生长不小于6个周期:
a)采用金属有机源化学气相沉积方法生长UID-GaN薄膜层(104);
b)采用金属有机源化学气相沉积方法生长10-100nm掺碳GaN薄膜;
c)采用金属有机源化学气相沉积方法生长10-100nm掺铁GaN薄膜。
7.根据权利要求1所述的一种基于硅衬底(101)的新型HEMT器件的制备方法,其特征在于,所述步骤(6)中的AlGaN势垒层采用AlxGa1-xN势垒层,其中0<=x<=1。
8.根据权利要求1所述的方法制备出的HEMT器件,其特征在于,该器件包括自下而上依次排布的衬底(101)、AlN成核层(102)、超晶格缓冲层(103)、UID-GaN层(104)、GaN缓冲层(105)、AlGaN背势垒层(106)、GaN沟道层(107)、第二势垒层(108)、GaN沟道层(107)、第一势垒层(109)、栅介质层(110),分布于两端的漏电极和源电极,设置于第一势垒层(109)顶部的栅极(113)以及源电极与栅极(113)之间、漏电极与栅极(113)之间的Si3N4钝化层(114)。
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