CN114117974A - Chip clock driving unit external member and design method and chip - Google Patents
Chip clock driving unit external member and design method and chip Download PDFInfo
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Abstract
The application provides a chip clock driving unit suite, a design method and a chip, wherein the design method of the chip clock driving unit suite comprises the following steps: determining the longest clock connection length in the chip; designing a maximum clock driving unit of the chip according to the longest clock connection length, wherein the driving capacity of the maximum clock driving unit is the maximum clock driving capacity required by the chip corresponding to the longest clock connection length; designing at least one other clock driving unit of the chip, wherein the clock driving capacity of the at least one other clock driving unit is smaller than that of the maximum clock driving unit, the external size and the port of the at least one other clock driving unit are the same as those of the maximum clock driving unit, and the chip clock driving unit suite comprises the maximum clock driving unit and the at least one other clock driving unit.
Description
Technical Field
The present invention relates to integrated circuit technology, and for example, to a chip clock driving unit kit, a design method, and a chip.
Background
With the expansion of chip scale, the chip clock structure becomes more and more important for timing convergence of the whole chip. The large-scale chip needs to adopt the influence of reasonable clock tree control Process, Voltage, Temperature (PVT) and hybrid-corner (cross-corner), and structurally ensures that the clock drift (clock skew) under each corner can be controlled within a reasonable range. And a unit with large driving capacity is adopted to reduce the clock delay of the top layer, which is beneficial to reducing the influence caused by On-Chip disturbance (OCV), thereby ensuring the rapid convergence of the whole Chip time sequence.
In the current chip design, the driving capability of the clock driving unit in the chip is designed according to the maximum clock connection length in the chip, but overdrive is easily caused to other clock connection lengths, so that the consumption on a clock path is increased.
Disclosure of Invention
The application provides a chip clock driving unit external member, a design method and a chip, which reduce the power consumption of the chip.
In a first aspect, an embodiment of the present application provides a method for designing a chip clock driving unit suite, including:
determining the longest clock connection length in the chip;
designing a maximum clock driving unit of the chip according to the longest clock connection length, wherein the driving capacity of the maximum clock driving unit is the maximum clock driving capacity required by the chip corresponding to the longest clock connection length;
designing at least one other clock driving unit of the chip, wherein the clock driving capacity of the at least one other clock driving unit is smaller than that of the maximum clock driving unit, the external size and the port of the at least one other clock driving unit are the same as those of the maximum clock driving unit, and the chip clock driving unit suite comprises the maximum clock driving unit and the at least one other clock driving unit.
In a second aspect, an embodiment of the present application provides a chip clock driving unit kit, including:
at least two clock driving units, the clock driving capability of at least two clock driving units is different;
the maximum clock driving unit with the maximum clock driving capacity in the at least two clock driving units is designed according to the maximum clock driving capacity required by the chip, and the maximum clock driving capacity required by the chip is determined according to the longest clock connection length in the chip;
the external sizes and ports of the at least two clock driving units are the same, and the external sizes and ports of the at least two clock driving units are determined according to the largest clock driving unit.
In a third aspect, an embodiment of the present application provides a chip, including: a chip clock driving unit kit as shown in any one of the possible implementations of the second aspect.
Drawings
Fig. 1 is a flowchart of a method for designing a chip clock driving unit kit according to an embodiment;
FIG. 2 is a flowchart illustrating another method for designing a chipset-based clock driving unit package according to an embodiment;
fig. 3 is a schematic structural diagram of a chip clock driving unit kit according to an embodiment.
Detailed Description
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for designing a chip clock driving unit kit according to an embodiment, where as shown in fig. 1, the method according to the embodiment includes the following steps.
Step S1010, determine the longest clock line length in the chip.
The method for designing the chip clock driving unit suite provided by the embodiment is used for designing the clock driving unit in the integrated circuit chip. In order to realize a plurality of different functions in a chip, a plurality of different functional units need to be designed, and the different functional units are all realized by designing different arrangement modes of transistors in the chip. Various different functional units in a chip generally need clock signals to achieve synchronization, and then a clock driving unit needs to be designed in the chip to drive different functional units in the chip in a clock mode. In order to realize timing convergence in a chip, the design of a Clock Tree (Clock Tree) is proposed in the chip design, including H-Tree, X-Tree, balanced-Tree, etc. The design of the clock tree can well control the influence of PVT and cross-corner in the chip. In order to reduce the clock delay at the top layer of the chip, a clock driving unit with large driving capability is required, so that the influence caused by OCV is reduced. However, in the design of the clock driving unit in the chip at present, the clock driving unit with the maximum clock driving capability is designed by considering the maximum clock driving capability required by the chip. And because the clock connecting lines of different functional units in the chip are different in length, the clock driving unit with the maximum clock driving capacity is used for driving all the functional units, so that the consumption on a clock path is increased, and the power consumption of the chip is increased.
Therefore, in this embodiment, a method for designing a chip clock driving unit suite is provided, in which a longest clock line length in a chip is determined first. The length of the clock connecting line in the chip is determined according to the actual length of the connecting line of each functional unit in the chip to the clock driving unit. The unit of the length of the clock line in the chip is generally u, which is 10-6Rice, i.e. 1 u-1 micron. After the chip completes the design layout of the functional units, the clock connection length of each functional unit can be determined, and the longest clock connection length of the chip is selected as the longest clock connection length of the chip.
In step S1020, a maximum clock driving unit of the chip is designed according to the longest clock connection length, and a driving capability of the maximum clock driving unit is a maximum clock driving capability required by the chip corresponding to the longest clock connection length.
The clock driving capability required by various functional units in the chip is determined according to the clock connection length of the functional units, and the longer the clock connection length of the functional units is, the farther the clock driving unit is, which means that the clock driving unit with the larger driving capability can drive the functional unit. Then, in order to drive all the functional units in the chip, the clock driving unit required for designing the functional unit meeting the requirement of the maximum clock driving capability is necessarily required in the chip, that is, the maximum clock driving unit of the chip is designed according to the longest clock connection length in the chip. Therefore, after the longest clock line length in the chip is determined, the maximum clock driving unit of the chip can be designed according to the longest clock line length. The maximum clock driving unit of the chip only needs to satisfy the maximum clock driving capability required by the chip, and the specific design method thereof is a conventional technical means for those skilled in the art, and is not described herein again.
Step S1030, designing at least one other clock driving unit of the chip, where the clock driving capability of the at least one other clock driving unit is smaller than that of the maximum clock driving unit, the external size and the port of the at least one other clock driving unit are the same as those of the maximum clock driving unit, and the chip clock driving unit kit includes the maximum clock driving unit and the at least one other clock driving unit.
In the chip, the clock driving unit with large driving capability is used to drive the functional unit with short clock line, which increases the power consumption consumed on the clock path. The clock driving unit suite of the chip at least needs to include a maximum clock driving unit and at least one other clock driving unit except the maximum clock driving unit. That is, at least two clock driving units are included in the clock driving unit kit. The clock driving capability of at least one other clock driving unit is smaller than that of the maximum clock driving unit. Therefore, the clock driving units with different clock driving capacities can be adopted to carry out clock driving in the chip according to the clock connection lengths of the different functional units, so that power consumption on a clock path caused by driving all the functional units by using the clock driving unit with the largest driving capacity is avoided.
As long as at least two clock driving units are designed in the chip, wherein one maximum clock driving unit is designed according to the maximum clock driving capacity required by the chip, and the clock driving capacity of at least one other clock driving unit is smaller than that of the maximum clock driving unit, part of the functional units in the chip can be driven by the other clock driving units, so that the power consumption consumed on a clock path is reduced.
For example, there are 3 functional units in the chip that need to be clocked, respectively A, B, C, with clock connection lengths of 1000u, 500u and 200u, respectively. Then the clock driving unit a is designed according to the longest clock line length, i.e. 1000u, and then a clock driving unit b capable of driving the clock line length to 500u is designed. Then functional unit a can be driven using clock driver unit a and functional units B and C can be driven using clock driver unit B. This significantly reduces power consumption on the clock path compared to driving all functional units of the chip with the clock driving unit of maximum clock driving capability. Of course, a clock driving unit C capable of driving a clock connection line with a length of 200u may be designed, the clock driving unit a may be used to drive the functional unit a, the clock driving unit B may be used to drive the functional unit B, and the clock driving unit C may be used to drive the functional unit C. Thereby further reducing power consumption on the clock path.
The number of the at least one other clock driving unit may be one or more, and the clock driving capability of the at least one other clock driving unit may be any clock driving capability smaller than that of the maximum clock driving unit. After the clock driving unit suite comprising at least two clock driving units is designed, different clock driving units can be adopted for different functional units in a chip more reasonably to carry out clock driving, and the clock driving unit meeting the clock driving capacity requirement of the functional unit can be selected according to the clock connecting line length of the different functional units.
In addition, in the design process of the chip, different functional units may be continuously adjusted, so that the clock connection lengths of the different functional units may be changed, that is, the clock driving capabilities of the clock driving units required by the different functional units may need to be adjusted at any time in the chip. Therefore, after the clock driving unit suite comprising at least two clock driving units is designed for the chip, when the clock driving capacity required by each functional unit in the chip is changed, a proper clock driving unit is selected from the clock driving unit suite, and a new clock driving unit does not need to be redesigned, so that the chip design efficiency is improved. Considering again that when the clock driving unit in the chip needs to be changed, the position and the port of the clock driving unit are prevented from being redesigned, and the external size and the interface of at least one other clock driving unit can be designed according to the external size and the port of the largest clock driving unit, so that all the clock driving units in the clock driving unit suite have the same external size and port. Therefore, when the functional unit in the chip is changed and the clock driving unit needs to be replaced, the clock driving unit meeting the changed functional unit is selected from the clock driving unit suite again to replace the original clock driving unit, and other parts of the chip do not need to be redesigned, so that the chip design efficiency is further improved.
In one embodiment, the external dimensions and ports of at least one other clock driver unit are the same as the largest clock driver unit, including: the external dimensions, port location, port shape, port size, port metal layer of at least one other clock driving unit are the same as the largest clock driving unit. The same external dimensions can avoid the influence of the replacement of the clock driving unit on the design of other functional units in the chip, the same port positions, port shapes, port sizes and port metal layers can be used, and the connection mode of other functional units does not need to be changed when the clock driving unit is replaced.
The method for designing a chip clock driving unit suite provided by this embodiment first determines the longest clock connection length in the chip, determining the maximum clock driving capability required by the chip according to the longest clock connection length and designing the maximum clock driving unit of the chip according to the maximum clock driving capability, then at least one other clock driving unit of the chip is designed, the clock driving capability of the at least one other clock driving unit is smaller than that of the maximum clock driving unit, and the external dimensions and ports of at least one other clock driving unit are the same as the largest clock driving unit, the maximum clock driving unit and at least one other clock driving unit form a clock driving unit suite of the chip, power consumption consumed on a clock path in the chip is reduced, power consumption of the whole chip is reduced, and design efficiency of the chip is improved.
Fig. 2 is a flowchart of another method for designing a chip clock driving unit kit according to an embodiment, and as shown in fig. 2, the method according to the embodiment includes the following steps.
Step S2010, determining the longest clock line length in the chip.
The method for designing the chip clock driving unit suite provided by the embodiment is used for designing the clock driving unit in the integrated circuit chip. In order to realize a plurality of different functions in a chip, a plurality of different functional units need to be designed, and the different functional units are all realized by designing different arrangement modes of transistors in the chip. Various different functional units in a chip generally need clock signals to achieve synchronization, and then a clock driving unit needs to be designed in the chip to drive different functional units in the chip in a clock mode. In order to realize timing convergence in a chip, the design of a Clock Tree (Clock Tree) is proposed in the chip design, including H-Tree, X-Tree, balanced-Tree, etc. The design of the clock tree can well control the influence of PVT and cross-corner in the chip. In order to reduce the clock delay at the top layer of the chip, a clock driving unit with large driving capability is required, so that the influence caused by OCV is reduced. However, in the design of the clock driving unit in the chip at present, the clock driving unit with the maximum clock driving capability is designed by considering the maximum clock driving capability required by the chip. And because the clock connecting lines of different functional units in the chip are different in length, the clock driving unit with the maximum clock driving capacity is used for driving all the functional units, so that the consumption on a clock path is increased, and the power consumption of the chip is increased.
Therefore, in this embodiment, a method for designing a chip clock driving unit suite is provided, in which a longest clock line length in a chip is determined first. The length of the clock connecting line in the chip is determined according to the actual length of the connecting line of each functional unit in the chip to the clock driving unit. The unit of the length of the clock line in the chip is generally u, which is 10-6Rice, i.e. 1 u-1 micron. After the chip completes the design layout of the functional units, the clock connection length of each functional unit can be determined, and the longest clock connection length of the chip is selected as the longest clock connection length of the chip.
In step S2020, the maximum clock driving unit of the chip is designed according to the longest clock connection length, and the driving capability of the maximum clock driving unit is the maximum clock driving capability required by the chip corresponding to the longest clock connection length.
The clock driving capability required by various functional units in the chip is determined according to the clock connection length of the functional units, and the longer the clock connection length of the functional units is, the farther the clock driving unit is, which means that the clock driving unit with the larger driving capability can drive the functional unit. Then, in order to drive all the functional units in the chip, the clock driving unit required for designing the functional unit meeting the requirement of the maximum clock driving capability is necessarily required in the chip, that is, the maximum clock driving unit of the chip is designed according to the longest clock connection length in the chip. Therefore, after the longest clock line length in the chip is determined, the maximum clock driving unit of the chip can be designed according to the longest clock line length. The maximum clock driving unit of the chip only needs to satisfy the maximum clock driving capability required by the chip, and the specific design method thereof is a conventional technical means for those skilled in the art, and is not described herein again.
In step S2030, a minimum clock driving unit of the chip is designed according to the shortest clock connection length in the chip, and the driving capability of the minimum clock driving unit is the minimum clock driving capability required by the chip corresponding to the shortest clock connection length.
In this embodiment, after the maximum clock driving unit of the chip is designed according to the maximum clock driving capability required by the chip, the minimum clock driving unit of the chip may be designed according to the minimum clock driving capability required by the chip. The minimum clock driving unit of the chip is used for providing clock driving for the functional unit with the minimum requirement on the clock driving capacity in the chip. Similar to the method for determining the maximum clock driving unit, the minimum clock driving unit of the chip is first designed according to the shortest clock connection length. The minimum clock driving unit of the chip only needs to satisfy the minimum clock driving capability required by the chip. After the minimum clock driving unit of the chip is determined, the maximum clock driving unit and the minimum clock driving unit may be used to provide clock driving for the chip. The external size and ports of the minimum clock driving unit are the same as those of the maximum clock driving unit. The chip clock driving unit kit may include a maximum clock driving unit and a minimum clock driving unit.
Step S2040, at least one intermediate clock driving unit of the chip is designed, and the clock driving capability of the at least one intermediate clock driving unit is smaller than that of the maximum clock driving unit and larger than that of the minimum clock driving unit.
Optionally, after the maximum clock driving unit and the minimum clock driving unit of the chip are designed, at least one intermediate clock driving unit of the chip may also be designed. The clock driving capability of the at least one intermediate clock driving unit is located between the maximum clock driving unit and the minimum clock driving unit, i.e. smaller than the clock driving capability of the maximum clock driving unit and larger than the clock driving capability of the minimum clock driving unit. The number of the at least one intermediate clock driving unit may be one or more. The clock driving capability of the at least one intermediate clock driving unit may be linearly distributed or non-linearly distributed between a maximum clock driving capability required by the chip and a minimum clock driving capability required by the chip. For example, a plurality of clock driving capabilities may be determined according to the clock connection length of a designed functional unit in a chip, and then a maximum clock driving unit, a minimum clock driving unit, and a plurality of intermediate clock driving units are designed correspondingly to form a clock driving unit suite. The external dimensions and ports of at least one intermediate clock driving unit are the same as the largest clock driving unit. The chip clock driving unit kit may include a maximum clock driving unit, a minimum clock driving unit, and at least one intermediate clock driving unit.
In addition, at least one intermediate clock driving capability can be selected between the maximum clock driving capability and the minimum clock driving capability of the chip according to a preset step length, and then at least one intermediate clock driving unit can be designed according to the at least one intermediate clock driving capability. That is, after determining the maximum clock driving capability and the minimum clock driving capability of the chip and designing the maximum clock driving unit and the minimum clock driving unit, selecting an appropriate step size and determining one or more intermediate clock driving capabilities between the maximum clock driving capability and the minimum clock driving capability. And then designing one or more corresponding intermediate clock driving units according to the one or more intermediate clock driving capabilities, and finally forming a clock driving unit suite by the maximum clock driving unit, the minimum clock driving unit and the one or more intermediate clock driving units. Then, in the chip, according to the clock driving capability required by different functional units, a suitable clock driving unit can be selected from the clock driving unit suite, and when the clock driving capability required by each functional unit changes, a suitable other clock driving unit can be selected from the clock driving unit suite. The preset step length can be set according to requirements. For example, the longest clock line length in the chip is determined to be 1000u, the minimum clock line length is determined to be 200u, and the maximum clock driving unit m and the minimum clock driving unit n are correspondingly designed respectively. Then, the preset step size is determined to be 200u, and then the intermediate clock driving units respectively corresponding to the minimum clock connection lengths of 800u, 600u and 400u are correspondingly designed.
In an embodiment, after the maximum clock driving unit of the chip is designed, the number of transistors in the maximum clock driving unit may be reduced on the basis of the maximum clock driving unit to obtain at least one other clock driving unit. The clock driving unit in the chip also realizes the function of the clock driving unit through different arrangement combinations and connection modes of a plurality of transistors, and the larger the clock driving capacity required by the clock driving unit is, the more the number of required transistors is. The number of transistors in the largest clock driving unit in the chip where the clock driving capability is the largest is also the largest. Therefore, after the maximum clock driving unit is designed, the design of at least one other clock driving unit can be completed by reducing the number of transistors in the maximum clock driving unit on the basis of the maximum clock driving unit. This eliminates the need to redesign the other clock driver units and advantageously ensures that the external dimensions and ports of at least one other clock driver unit are the same as the largest clock driver unit.
After the design of the chip clock driving unit suite is completed according to the embodiment, a circuit design link can be performed, the size of the replaced size of the P/N in each clock driving unit is determined through pre-simulation, and then the size is adjusted through simulation.
After the circuit design is completed and the circuit diagram of each clock driving unit is obtained, the layout design can be carried out, and the method comprises the following steps: 1) the layout architecture and the size of the maximum clock driving unit are firstly determined, the maximum clock driving unit needs to be completed firstly, and the layout sizes of all clock driving units in the whole clock driving unit suite are consistent, so that the size of the maximum clock driving unit is very important. The wiring needs to be laid out by considering the special rule of the layout under the advanced process, considering the antenna effect, considering the parasitic effect, considering the external influence on the driving unit, considering the electro-Migration (EM) effect and considering the routing of the data flow. And finally, obtaining the size of the maximum clock driving unit and the position, the size and the direction of the input/output port. (the position, size and direction of the input/output port can be customized according to the actual requirement of the chip). 2) And obtaining the layout of at least one other clock driving unit based on the maximum clock driving unit, and determining the layout of at least one other clock driving unit through post simulation only by reducing the number of transistors in the maximum clock driving unit and keeping the input/output ports unchanged.
Fig. 3 is a schematic structural diagram of a chip clock driving unit kit according to an embodiment, and as shown in fig. 3, the chip clock driving unit kit according to the embodiment includes:
at least two clock driving units 31, the clock driving capabilities of the at least two clock driving units 31 being different; the maximum clock driving unit with the maximum clock driving capability among the at least two clock driving units 31 is designed according to the maximum clock driving capability required by the chip, and the maximum clock driving capability required by the chip is determined according to the longest clock connection length in the chip; the external sizes and ports of the at least two clock driving units 31 are the same, and the external sizes and ports of the at least two clock driving units 31 are determined according to the maximum clock driving unit. IN the present embodiment, taking 4 clock driving units 31 as an example, each clock driving unit 31 has the same input interface IN and output interface OUT and the same external dimensions.
The chip clock driving unit suite provided in this embodiment is designed according to the method for designing the chip clock driving unit suite shown in fig. 1, and specific implementation principles and technical effects thereof have been elaborated in detail in the embodiment shown in fig. 1, and are not described herein again.
In one embodiment, the largest clock driving unit with the smallest clock driving capability among the at least two clock driving units 31 is designed according to the minimum clock driving capability required by the chip, and the minimum clock driving capability required by the chip is determined according to the shortest clock connection length in the chip.
In an embodiment, the at least two clock driving units 31 further include at least one intermediate clock driving unit; the clock driving capability of at least one intermediate clock driving unit is smaller than that of the maximum clock driving unit and larger than that of the minimum clock driving unit.
In one embodiment, the clock driving capability of at least one intermediate clock driving unit is sequentially set between the maximum clock driving capability and the minimum clock driving capability by a preset step size.
In an embodiment, at least one other clock driving unit than the largest clock driving unit of the at least two clock driving units 31 is obtained by reducing the number of transistors based on the largest clock driving unit.
In one embodiment, the external dimensions, port locations, port shapes, port sizes, and port metal layers of at least two clock driving units 31 are the same.
The embodiment of the application also provides a chip, which comprises the chip clock driving unit suite as shown in fig. 3.
In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
Embodiments of the application may be implemented by a data processor of a mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages.
Any logic flow block diagrams in the figures of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored on a memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, Read-Only Memory (ROM), Random-Access Memory (RAM), optical storage devices and systems (Digital versatile disks (DVD) or Compact Disks (CD)), etc., the computer-readable medium can comprise a non-transitory storage medium, the data processor can be of any type suitable to the local technical environment, such as, but not limited to, general purpose computers, special purpose computers, microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated circuits (SAICs), Programmable logic devices (FGPAs), and processors based on a multi-core processor architecture.
Claims (13)
1. A method for designing a chip clock driving unit suite is characterized by comprising the following steps:
determining the longest clock connection length in the chip;
designing a maximum clock driving unit of the chip according to the longest clock connection length, wherein the driving capacity of the maximum clock driving unit is the maximum clock driving capacity required by the chip corresponding to the longest clock connection length;
designing at least one other clock driving unit of the chip, wherein the clock driving capability of the at least one other clock driving unit is smaller than that of the maximum clock driving unit, the external size and the port of the at least one other clock driving unit are the same as those of the maximum clock driving unit, and the chip clock driving unit suite comprises the maximum clock driving unit and the at least one other clock driving unit.
2. The method of claim 1, wherein designing at least one other clock driving unit of the chip comprises:
and designing a minimum clock driving unit of the chip according to the shortest clock connection length in the chip, wherein the driving capacity of the minimum clock driving unit is the minimum clock driving capacity required by the chip corresponding to the shortest clock connection length.
3. The method of claim 2, wherein designing at least one other clock driving unit of the chip further comprises:
designing at least one intermediate clock driving unit of the chip, wherein the clock driving capability of the at least one intermediate clock driving unit is smaller than that of the maximum clock driving unit and larger than that of the minimum clock driving unit.
4. The method of claim 3, wherein designing at least one intermediate clock drive unit of the chip comprises:
selecting at least one intermediate clock drive capability between the maximum clock drive capability and the minimum clock drive capability at a preset step length;
designing the at least one intermediate clock driving unit according to the at least one intermediate clock driving capability.
5. The method according to any one of claims 1 to 4, wherein the designing at least one other clock driving unit of the chip comprises:
and on the basis of the maximum clock driving unit, reducing the number of transistors in the maximum clock driving unit to obtain the at least one other clock driving unit.
6. The method of any of claims 1 to 4, wherein the at least one other clock driving unit has the same external dimensions and ports as the largest clock driving unit, comprising:
the external dimensions, port locations, port shapes, port sizes, port metal layers of the at least one other clock driving unit are the same as the largest clock driving unit.
7. A chip clock drive unit kit, comprising:
at least two clock driving units, the clock driving capabilities of the at least two clock driving units being different;
the maximum clock driving unit with the maximum clock driving capacity in the at least two clock driving units is designed according to the maximum clock driving capacity required by the chip, and the maximum clock driving capacity required by the chip is determined according to the length of the longest clock connecting line in the chip;
the external dimensions and ports of the at least two clock driving units are the same, and the external dimensions and ports of the at least two clock driving units are determined according to the maximum clock driving unit.
8. The chip clock driving unit kit according to claim 7, wherein the largest clock driving unit with the smallest clock driving capability among the at least two clock driving units is designed according to the minimum clock driving capability required by the chip, and the minimum clock driving capability required by the chip is determined according to the shortest clock connection length in the chip.
9. The chip clock driving unit kit according to claim 8, wherein the at least two clock driving units further comprise at least one intermediate clock driving unit;
the clock driving capability of the at least one intermediate clock driving unit is smaller than that of the maximum clock driving unit and larger than that of the minimum clock driving unit.
10. The chip clock driving unit kit as claimed in claim 9, wherein the clock driving capability of the at least one intermediate clock driving unit is sequentially set at a preset step size between the maximum clock driving capability and the minimum clock driving capability.
11. The chip clock driving unit kit according to any one of claims 7 to 10, wherein at least one other clock driving unit other than the largest clock driving unit of the at least two clock driving units is obtained by reducing the number of transistors based on the largest clock driving unit.
12. The kit of chip clock driving units according to any one of claims 7 to 10, wherein the external dimensions, port positions, port shapes, port sizes, and port metal layers of the at least two clock driving units are the same.
13. A chip, comprising: the chip clock driving unit kit as claimed in any one of claims 7 to 12.
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| CN202010899703.8A CN114117974A (en) | 2020-08-31 | 2020-08-31 | Chip clock driving unit external member and design method and chip |
| PCT/CN2021/114567 WO2022042611A1 (en) | 2020-08-31 | 2021-08-25 | Clock driving unit assembly of chip, design method therefor, and chip |
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| CN202010899703.8A CN114117974A (en) | 2020-08-31 | 2020-08-31 | Chip clock driving unit external member and design method and chip |
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- 2020-08-31 CN CN202010899703.8A patent/CN114117974A/en active Pending
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| JPH10199985A (en) * | 1997-01-09 | 1998-07-31 | Yamaha Corp | Semiconductor integrated circuit and layout design method therefor |
| JP2003332430A (en) * | 2002-05-13 | 2003-11-21 | Kawasaki Microelectronics Kk | Semiconductor integrated circuit |
| TW200428240A (en) * | 2004-08-18 | 2004-12-16 | Univ Chang Gung | A clock tree synthesizing tool synchronously considering low clock skew and low power consumption |
| CN101290639A (en) * | 2007-04-16 | 2008-10-22 | 松下电器产业株式会社 | Semiconductor integrated circuit and layout method for the same |
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| WO2022042611A1 (en) | 2022-03-03 |
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