CN114093952A - High-symmetry bidirectional TVS diode and preparation method thereof - Google Patents
High-symmetry bidirectional TVS diode and preparation method thereof Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 16
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000002347 injection Methods 0.000 claims abstract description 20
- 239000007924 injection Substances 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 238000009413 insulation Methods 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims abstract description 4
- 230000000149 penetrating effect Effects 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 70
- 230000015556 catabolic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- 238000000206 photolithography Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
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- NUHSROFQTUXZQQ-UHFFFAOYSA-N isopentenyl diphosphate Chemical compound CC(=C)CCO[P@](O)(=O)OP(O)(O)=O NUHSROFQTUXZQQ-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
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Abstract
The invention discloses a high-symmetry bidirectional TVS diode and a preparation method thereof, and belongs to the field of semiconductor protection devices. Providing an N-type substrate, and sequentially forming a P-type epitaxial layer and an oxide layer on the surface of the N-type substrate; forming an N + injection region through ion injection and diffusion annealing, and removing the damaged oxide layer in the process; forming a Trench on the N-type substrate by deep groove etching and penetrating through the P-type epitaxial layer, wherein LPTEOS with insulation property is completely filled in the Trench; forming an opening on LPTEOS to form an ohmic contact region; depositing metal on the front surface to form a front electrode, depositing a passivation layer on the surface of the front electrode, and opening a hole on the passivation layer to expose a metal lead hole, thereby facilitating subsequent testing and packaging and routing; and depositing multiple layers of metal on the back surface to form a back electrode. An N + injection region is directly formed on the P-type epitaxial layer to achieve a longitudinal NPN bidirectional TVS structure, the Trench isolation replaces the traditional PN junction isolation, the primary heat treatment process is reduced, and meanwhile the active region area of the chip is increased.
Description
Technical Field
The invention relates to the technical field of semiconductor protection devices, in particular to a high-symmetry bidirectional TVS diode and a preparation method thereof.
Background
The TVS (Transient Voltage Suppressor) is a clamping overvoltage protection device, and is connected with a protected circuit in parallel on a circuit board, so that surge Voltage can be fixed at a lower Voltage level within a short time, a rear-stage circuit is prevented from being impacted by electrostatic discharge or Transient surge Voltage, and the circuit is prevented from being damaged.
The TVS device is mainly applied to various interface circuits, such as mobile phones, flat panels, televisions and computer hosts, and is provided with a large number of TVS protection devices, wherein the TVS devices and the protected chips are in parallel connection, and under the normal working condition, the TVS presents a high impedance state. When electrostatic discharge or surge voltage enters from the IO end of the circuit, the TVS device is triggered to be preferentially conducted, current is released to the ground through the TVS device, and voltage is clamped at a lower level, so that a rear-stage circuit is effectively protected. With the rapid development of technology, the integrated circuit is continuously developed to low voltage, low power consumption, and high speed transmission, and higher performance requirements are also imposed on the corresponding TVS protection device, which requires that the TVS has a sufficiently high endurance and a clamping voltage as low as possible.
Disclosure of Invention
The invention aims to provide a high-symmetry bidirectional TVS diode and a preparation method thereof, so as to solve the problems in the background art.
In order to solve the above technical problem, the present invention provides a highly symmetric bidirectional TVS diode, including:
an N-type substrate;
the P-type epitaxial layer is formed on the surface of the N-type substrate;
the N + injection region is formed on the surface of the P-type epitaxial layer;
the Trench Trench penetrates through the P-type epitaxial layer and is completely filled with LPTEOS with insulating property;
a front electrode formed by depositing a metal on the surface of the N + injection region;
the passivation layer is positioned on the surface of the front electrode, and an opening is formed in the passivation layer;
and the back electrode is formed on the back of the N-type substrate.
Optionally, the P-type epitaxial layer includes a first P-type epitaxial layer located on the N-type substrate and a second P-type epitaxial layer located on the first P-type epitaxial layer, and the thickness of the first P-type epitaxial layer is 1 to 5 times that of the second P-type epitaxial layer.
Optionally, the first P-type epitaxial layer and the second P-type epitaxial layer are both doped P + type, and the doping concentration of the first P-type epitaxial layer is higher than that of the second P-type epitaxial layer; the doping concentration of the first P type epitaxial layer is 2E18cm-3～7E18cm-3The doping concentration of the second P type epitaxial layer is 3E17cm-3～1E18cm-3。
The invention also provides a preparation method of the high-symmetry bidirectional TVS diode, which comprises the following steps:
providing an N-type substrate, and sequentially forming a P-type epitaxial layer and an oxide layer on the surface of the N-type substrate;
forming an N + injection region through ion injection and diffusion annealing, and removing the damaged oxide layer in the process;
forming a Trench on the N-type substrate by deep groove etching and penetrating through the P-type epitaxial layer, wherein LPTEOS with insulation property is completely filled in the Trench;
forming an opening on LPTEOS to form an ohmic contact region;
depositing metal on the front surface to form a front electrode, depositing a passivation layer on the surface of the front electrode, and opening a hole on the passivation layer to expose a metal lead hole, so that subsequent testing and packaging routing are facilitated;
and depositing multiple layers of metal on the back surface to form a back electrode.
Optionally, the N-type substrate has a <100> crystal orientation, is doped with As, has a resistivity of 0.002-0.004 ohm.cm, and has a thickness of 625 μm.
Optionally, the N + implantation region is formed by implanting ions As with a doping concentration of 1E15cm-3～1E16cm-3(ii) a The diffusion annealing activates the injected ions, the temperature of the furnace tube is 1000-1200 ℃, and the time is 30-90 min.
Optionally, the Trench has a feature size of 0.5 μm to 1.0 μm, and the LPTEOS has a thickness of 0.8 μm to 1.5 μm in order to ensure that LPTEOS is completely filled in the Trench.
Optionally, forming an opening on the LPTEOS to form an ohmic contact region includes: and defining an ohmic contact region by photoetching, and corroding LPTEOS on the surface by a wet process to connect the subsequent front electrode with the N + injection region.
Optionally, depositing a plurality of layers of metal on the back side to form the back electrode includes: thinning the N-type substrate, manufacturing back metal through an evaporation process, and forming a back electrode; wherein the back metal is TiNiAg or TiNiSnCuAg.
Optionally, the passivation layer is located on the front electrode, and the opening region is etched through a photoetching and dry etching process, so that subsequent packaging and routing are facilitated; wherein the passivation layer is Si3N4, and the thickness is 0.3-0.6 μm.
The high-symmetry bidirectional TVS diode and the preparation method thereof have the following beneficial effects:
(1) an N + injection region is directly formed by commonly injecting As on the P-type epitaxial layer, and compared with a conventional NPN longitudinal TVS diode, the N + injection region has the advantages that one photoetching process is reduced, the production circulation period is shortened, and the manufacturing cost is reduced;
(2) the Trench isolation region replaces the traditional PN junction isolation, so that the thermal process and the transverse diffusion effect of the device are reduced, the overall leakage level of the device is reduced, the area of an active region is increased, and the limit performance of the device is improved;
(3) the P-type epitaxial layers P1-epi and P2-epi serving as the base electrodes are manufactured by an epitaxial process, on one hand, the good uniformity of the P-type epitaxial layers can eliminate the weak point of the device which is broken down in advance, the reliability of the product is improved, on the other hand, the thickness and the resistivity of the two layers of the epitaxial layers can be reasonably adjusted, the forward and reverse bidirectional breakdown voltage bias is reduced through flexible combination, and the high symmetry between the breakdown voltage and the forward and reverse performance of the device is achieved;
(4) and a titanium layer is added at the interface between the N + injection region and the metal to form good ohmic contact, so that the contact resistance is reduced, and the aluminum puncture phenomenon can be effectively avoided.
Drawings
FIG. 1 is a schematic view of a thin oxide layer formed on the surface of a P-type epitaxial layer on the front side of an N-type substrate;
FIG. 2 is a schematic view of forming an N + implantation region on the surface of the second P-type epitaxial layer;
FIG. 3 is a schematic diagram of Trench etching and LPTEOS filling;
FIG. 4 is a schematic diagram of a photolithographic etching of an opening to form an ohmic contact region;
FIG. 5 is a schematic illustration of front side metal deposition to form a front side electrode;
FIG. 6 is a schematic illustration of a passivation layer deposited and opened on the front electrode;
FIG. 7 is a schematic diagram of a back metal deposited on the back of an N-type substrate to form a back electrode.
Detailed Description
The high-symmetry bidirectional TVS diode and the method for manufacturing the same according to the present invention will be further described in detail with reference to the accompanying drawings and the following embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The silicon wafer is an N-type substrate N-sub, a first P-type epitaxial layer P1-epi positioned on the surface of the N-type substrate N-sub and a second P-type epitaxial layer P2-epi positioned on the surface of the first P-type epitaxial layer P1-epi, and the N-type substrate is an N-type substrate<100>Crystal orientation, As doping, resistivity of 0.002-0.004 ohm.cm and thicknessThe degree is 625 μm; the thickness of the first P-type epitaxial layer is 1-5 times that of the second P-type epitaxial layer; the first P-type epitaxial layer and the second P-type epitaxial layer are both doped in a P + type manner, and the doping concentration of the first P-type epitaxial layer is higher than that of the second P-type epitaxial layer; the doping concentration of the first P type epitaxial layer is 2E18cm-3～7E18cm-3The doping concentration of the second P-type epitaxial layer is 3E17cm-3～1E18cm-3。
Growing a 10-20 nm thin oxide layer OX on the upper surface of a second P type epitaxial layer P2-epi on the front surface of the silicon wafer to serve as a masking layer for N + injection, so that the silicon surface is prevented from being damaged, and the structure is shown in figure 1;
forming an N + implantation region with a certain depth and concentration by ion implantation and diffusion annealing, and removing the oxide layer OX on the surface layer damaged in the ion implantation process, wherein the structure is shown in fig. 2; the N + implantation region is formed by implanting ions As with the doping concentration of 1E15cm-3～1E16cm-3(ii) a The diffusion annealing activates the injected ions, the temperature of the furnace tube is 1000-1200 ℃, and the time is 30-90 min;
forming a Trench by photoetching and deep Trench etching, removing etched polymer (polymer) by wet method and sacrificial oxidation, repairing damage, backfilling LPTEOS, and compacting LPTEOS by furnace tube process to form a Trench isolation region with a structure shown in FIG. 3; the Trench is characterized in that the characteristic dimension of the Trench is 0.5-1.0 mu m, and the thickness of the LPTEOS is 0.8-1.5 mu m for ensuring the LPTEOS to be completely filled in the Trench
Forming an ohmic contact region by opening a hole on the LPTEOS by photolithography and wet etching, specifically, defining the ohmic contact region by photolithography, and etching the LPTEOS on the surface by wet etching, so that the subsequent front electrode is connected with the N + injection region, and the structure is as shown in fig. 4;
depositing METAL on the surface to form a front METAL electrode, wherein the METAL covers the N + injection region and part of LPTEOS, the METAL is titanium-aluminum double-layer METAL, titanium is on the bottom layer, aluminum is on the surface layer, the thickness of the titanium METAL is 0.1-0.2 μm, the thickness of the aluminum METAL is 4-8 μm, and the structure is shown in figure 5;
depositing a passivation layer on the METAL METAL, and forming a hole on the passivation layer by photoetching to expose the METAL lead hole, so as to facilitate subsequent testing and packaging routing, wherein the passivation layer is Si3N4, the thickness of the passivation layer is 0.3-0.6 μm, and the structure is shown in FIG. 6;
grinding and thinning the back surface of the N-sub substrate to 150 mu m, and then depositing a plurality of layers of METAL (METAL) on the back surface of the N-sub substrate to form a back electrode, wherein the plurality of layers of METAL are TiNiAg or TiNiSnCuAg, and the structure is shown in figure 7.
According to the invention, the P-type epitaxial layer containing the N-type substrate is adopted, and the N + injection region is directly formed by commonly injecting As on the P-type epitaxial layer, so that a photoetching process is reduced compared with a conventional NPN longitudinal TVS diode, the production circulation period is shortened, and the manufacturing cost is reduced; on the basis of the scheme, the TVS diode device forms a Trench isolation region on the N-type substrate, the isolation region is guaranteed to penetrate through the P-type epitaxial layer by controlling the etching depth of the deep Trench, the LPTEOS dielectric layer with the insulation characteristic is completely filled in the isolation region, electrical isolation is formed electrically, a leakage channel is prevented from being formed at the edge of the device, and the whole leakage level of the device product is effectively reduced. Compared with the traditional PN junction isolation, the scheme reduces one thermal process, has no PN junction lateral diffusion effect, increases the active area of the device on the same scale, and improves the performance of the device. The Trench is subjected to ion etching, the side face is steep, the surface defects are repaired by wet process, sacrificial oxide layer and other processes after etching, the steep groove interface can enable subsequent LPTEOS backfill to be more sufficient, and gaps are basically not formed in the middle.
The P-type epitaxial layer of the invention selects a double-layer epitaxial layer, and the appropriate thickness and resistivity of the first P-type epitaxial layer and the second P-type epitaxial layer are selected by considering the dynamic parameter capabilities of the TVS diode such as IPP, Cj and the like during the design, so as to meet the requirements of the device product on the dynamic capability. When the forward and reverse breakdown voltage is debugged, the bidirectional TVS device cannot be independently seen as two PN diode structures due to the longitudinal NPN structure, the influence of the triode needs to be fully considered, the concentration distribution of the P-type epitaxial layer can influence the base region concentration of the triode, the amplification factor of the triode can be influenced, and the forward and reverse breakdown voltage can also be influenced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A highly symmetric bidirectional TVS diode comprising:
an N-type substrate;
the P-type epitaxial layer is formed on the surface of the N-type substrate;
the N + injection region is formed on the surface of the P-type epitaxial layer;
the Trench Trench penetrates through the P-type epitaxial layer and is completely filled with LPTEOS with an insulating property;
a front electrode formed by depositing a metal on the surface of the N + injection region;
the passivation layer is positioned on the surface of the front electrode, and an opening is formed in the passivation layer;
and the back electrode is formed on the back of the N-type substrate.
2. The highly symmetric bidirectional TVS diode of claim 7, wherein said P-type epitaxial layer comprises a first P-type epitaxial layer on said N-type substrate and a second P-type epitaxial layer on said first P-type epitaxial layer, said first P-type epitaxial layer having a thickness of 1 to 5 times that of said second P-type epitaxial layer.
3. The highly symmetric bidirectional TVS diode of claim 2, wherein said first P-type epitaxial layer and said second P-type epitaxial layer are both P + type doped and wherein a doping concentration of said first P-type epitaxial layer is higher than a doping concentration of said second P-type epitaxial layer; the doping concentration of the first P type epitaxial layer is 2E18cm-3～7E18cm-3The doping concentration of the second P-type epitaxial layer is 3E17cm-3～1E18cm-3。
4. A preparation method of a high-symmetry bidirectional TVS diode is characterized by comprising the following steps:
providing an N-type substrate, and sequentially forming a P-type epitaxial layer and an oxide layer on the surface of the N-type substrate;
forming an N + injection region through ion injection and diffusion annealing, and removing the damaged oxide layer in the process;
forming a Trench on the N-type substrate by deep groove etching and penetrating through the P-type epitaxial layer, wherein LPTEOS with insulation property is completely filled in the Trench;
forming an opening on LPTEOS to form an ohmic contact region;
depositing metal on the front surface to form a front electrode, depositing a passivation layer on the surface of the front electrode, and opening a hole on the passivation layer to expose a metal lead hole, so that subsequent testing and packaging routing are facilitated;
and depositing multiple layers of metal on the back surface to form a back electrode.
5. The method of claim 4, wherein the N-type substrate has a <100> crystal orientation, is doped with As, has a resistivity of 0.002-0.004 ohm.cm, and has a thickness of 625 μm.
6. The method As claimed in claim 4, wherein the N + implantation region is formed by implanting As ions with a doping concentration of 1E15cm-3～1E16cm-3(ii) a The diffusion annealing activates the injected ions, the temperature of the furnace tube is 1000-1200 ℃, and the time is 30-90 min.
7. The method of claim 4, wherein the Trench Trench has a feature size of 0.5 μm to 1.0 μm, and the LPTEOS has a thickness of 0.8 μm to 1.5 μm to ensure complete filling of LPTEOS in the Trench Trench.
8. The method of claim 4, wherein forming the opening on the LPTEOS to form the ohmic contact region comprises: and defining an ohmic contact region by photoetching, and corroding LPTEOS on the surface by a wet process to connect the subsequent front electrode with the N + injection region.
9. The method of claim 4, wherein the step of depositing a plurality of metal layers on the back side to form the back electrode comprises: thinning the N-type substrate, manufacturing back metal through an evaporation process, and forming a back electrode; wherein the back metal is TiNiAg or TiNiSnCuAg.
10. The method of claim 4, wherein the passivation layer is disposed on the front electrode and etched to form an opening region for subsequent wire bonding and packaging; wherein the passivation layer is Si3N4, and the thickness is 0.3-0.6 μm.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117174761A (en) * | 2023-11-02 | 2023-12-05 | 富芯微电子有限公司 | Voltage asymmetric bidirectional TVS device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117174761A (en) * | 2023-11-02 | 2023-12-05 | 富芯微电子有限公司 | Voltage asymmetric bidirectional TVS device and manufacturing method thereof |
| CN117174761B (en) * | 2023-11-02 | 2024-01-05 | 富芯微电子有限公司 | Voltage asymmetric bidirectional TVS device and manufacturing method thereof |
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