CN114078798A - 包括接合焊盘金属层结构的半导体器件 - Google Patents
包括接合焊盘金属层结构的半导体器件 Download PDFInfo
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- CN114078798A CN114078798A CN202110947964.7A CN202110947964A CN114078798A CN 114078798 A CN114078798 A CN 114078798A CN 202110947964 A CN202110947964 A CN 202110947964A CN 114078798 A CN114078798 A CN 114078798A
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- layer structure
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Abstract
公开了包括接合焊盘金属层结构的半导体器件。提出了一种半导体器件(100)。半导体器件(100)包括布线金属层结构(102)。半导体器件(100)进一步包括被直接布置在布线金属层结构(102)上的电介质层结构(104)。半导体器件(100)进一步包括被至少部分地直接布置在电介质层结构(104)上的接合焊盘金属层结构(106)。电介质层结构(104)的层厚度(td)在布线金属层结构(102)的层厚度(tw)的1%至30%的范围内。布线金属层结构(102)和接合焊盘金属结构(106)被通过电介质层结构(104)中的开口(108)电连接。
Description
技术领域
本公开涉及一种半导体器件,特别是涉及一种包括接合焊盘金属层结构的半导体器件。
背景技术
半导体器件技术目的在于针对包括功率半导体器件(诸如包括绝缘栅双极晶体管(IGBT)或二极管的芯片)的产品的更好的效率和更高的可靠性要求。半导体器件(例如模块或模制封装)在大小上缩小的同时应当实现甚至更高的电流密度和更低的电阻。缩小半导体器件伴随着接合管脚密度的增加。由于材料加热与所使用的布线接合材料(例如铝(Al))的热膨胀的组合,布线接合可能在电流密度上受限制。
功率循环和温度循环是在评估半导体器件的可靠性当中使用的常见的热加速测试。功率循环测试是加速测试,其中对给至半导体器件的功率进行开关(导通和断开),从而器件中的温度将变化(循环)。功率循环测试包括传导和开关,并且接近于器件的实际操作。
半导体器件的功率循环能力可能受金属焊盘/布线接合连接限制。例如,焊盘和布线的机械参数(例如硬度)不能被自由地调节并且存在针对施加到***的最大能量的限制以确保鲁棒的互连。在布线到焊盘的界面处可能出现不合期望的裂缝,在功率循环期间传播。
合期望的是改进半导体器件的可靠性并且提供其制造方法。
发明内容
本公开的示例涉及一种半导体器件。半导体器件包括布线金属层结构。半导体器件进一步包括被直接布置在布线金属层结构上的电介质层结构。半导体器件进一步包括被至少部分地直接布置在电介质层结构上的接合焊盘金属层结构。电介质层结构的层厚度范围从布线金属层结构的层厚度的1%至30%。布线金属层结构和接合焊盘金属结构被通过电介质层结构中的开口电连接。接合焊盘金属层结构是由铝按至少50%的物质的量构成的。
本公开的另一示例涉及一种制造半导体器件的方法。方法包括形成布线金属层结构。方法进一步包括形成被直接布置在布线金属层结构上的电介质层结构。方法进一步包括形成被至少部分地直接布置在电介质层结构上的接合焊盘金属层结构。电介质层结构的层厚度范围从布线金属层结构的层厚度的1%至30%。布线金属层结构和接合焊盘金属结构被通过电介质层结构中的开口电连接。接合焊盘金属层结构或其一部分包括按至少50%的物质的量的Al(铝)。
本领域技术人员在阅读以下详细描述并且查看随附附图时将认识到附加的特征和优点。
附图说明
随附附图被包括以提供对实施例的进一步的理解,并且被合并在本说明书中并且构成本说明书的一部分。附图图示半导体器件的实施例(例如竖向功率半导体器件)并且与描述一起用于解释实施例的原理。在以下的详细描述和权利要求中描述了进一步的实施例。
图1是用于图示包括被布置在布线金属层结构和接合焊盘金属层结构之间的电介质层结构的半导体器件的示例的示意性横截面视图。
图2A至图2E是用于图示电介质层结构的布局的示意性平面视图。
图3A至图3C是用于图示在半导体本体上的包括布线金属层结构、电介质层结构和接合焊盘金属层结构的布线区域的布局的示意性横截面视图。
具体实施方式
在以下的详细描述中参照随附附图,随附附图形成详细描述的一部分并且在附图中通过图示的方式示出其中可以实践本发明的具体实施例。要理解,在不脱离本发明的范围的情况下可以利用其它实施例并且可以作出结构或逻辑上的改变。例如,针对一个实施例图示或描述的特征可以被使用在其它实施例上或者与其它实施例结合使用以产生又一进一步的实施例。意图的是本发明包括这样的修改和变化。使用特定语言描述了示例,特定语言不应当被解释为限制所附权利要求的范围。附图并非按比例并且仅用于说明的目的。为了清楚起见,如果没有另外声明,则在不同附图中相同的要素已经由对应的标号指明。
术语“具有”、“包含”、“包括”、和“包括有”等是开放的,并且术语指示所声明的结构、要素或特征的存在但是不排除附加的要素或特征的存在。数量词“一”、“一个”和指代词“该”意图包括复数以及单数,除非上下文另外清楚地指示。
针对物理尺寸给出的范围包括边界值。例如,用于参数y的从a到b的范围读作为a≤y≤b。具有至少为c的值的参数y读作为c≤y,并且具有至多为d的值的参数y读作为y≤d。
术语“在…上”不应被解释为仅意味着“直接在…上”。相反,如果一个要素位于另一要素“上”(例如一层在另一层“上”或者在衬底或半导体本体“上”),则进一步的组件(例如进一步的层)可以位于两个要素之间(例如如果一层在衬底“上”,则进一步的层可以位于所述一层和所述衬底之间)。
半导体器件的示例可以包括布线金属层结构。半导体器件可以进一步包括直接布置在布线金属层结构上的电介质层结构。半导体器件可以进一步包括被至少部分地直接布置在电介质层结构上的接合焊盘金属层结构。电介质层结构的层厚度可以在布线金属层结构的层厚度的1%至30%、或3%至25%、或5%至20%、或5%至15%、或10%至20%的范围内。布线金属层结构和接合焊盘金属结构可以被通过电介质层结构中的开口电连接。
接合焊盘金属层结构或接合焊盘金属层结构的一部分可以是由铝按至少50%、至少70%、至少85%、或者甚至至少94%的物质的量构成的。物质的量可以指代在接合焊盘金属层结构中的原子的数量。例如,在接合焊盘金属层结构或其一部分中的原子的至少50%、至少70%、至少85%或者甚至至少94%可以是铝原子。
布线金属层结构或布线金属层结构的一部分可以是由铝按至少50%、至少70%、至少85%、或者甚至至少94%的物质的量构成的。物质的量可以指代在布线金属层结构中的原子的数量。例如,布线金属层结构或其一部分中的原子的至少50%、至少70%、至少85%或者甚至至少94%可以是铝原子。
半导体器件可以是例如集成电路或分立半导体器件或半导体模块。半导体器件可以是或包括功率半导体器件,例如具有在器件的第一侧处的第一负载端子和在与第一侧相对的第二侧处的第二负载端子之间的负载电流流动的竖向功率半导体器件,或者具有在器件的同一侧处的负载端子之间的负载电流流动的横向功率半导体器件。半导体器件可以是或者包括功率半导体IGBT(绝缘栅双极晶体管),或者功率半导体反向导通(RC)IGBT,或者诸如功率半导体IGFET(绝缘栅场效应晶体管,例如金属氧化物半导体场效应晶体管)的功率半导体晶体管,或者功率半导体二极管。功率半导体器件可以被配置为传导大于1A或大于10A或者甚至大于30A的电流,并且可以进一步被配置为阻断在几百到几千伏特的范围内(例如400V、650V、1.2kV、1.7kV、3.3kV、4.5kV、5.5kV、6kV、6.5kV)的负载端子之间的电压,例如IGBT的发射极和集电极之间的电压,或MOSFET的漏极和源极之间的电压。例如,阻断电压可以对应于在功率半导体器件的数据表中指定的电压等级。
布线金属层结构可以被布置在半导体本体上,半导体本体可以包括来自如下的半导体材料或者由来自如下的半导体材料构成:IV族元素半导体、IV-IV族化合物半导体材料、III-V族化合物半导体材料、或II-VI族化合物半导体材料。来自IV族元素半导体的半导体材料的示例除了其它之外还包括硅(Si)和锗(Ge)。IV-IV族化合物半导体材料的示例除了其它之外还包括碳化硅(SiC)和硅锗(SiGe)。III-V族化合物半导体材料的示例除了其它之外还包括砷化镓(GaAs)、氮化镓(GaN)、磷化镓(GaP)、磷化铟(InP)、氮化铟镓(InGaN)和砷化铟镓(InGaAs)。II-VI族化合物半导体材料的示例除了其它之外还包括碲化镉(CdTe)、碲镉汞(CdHgTe)和碲镁镉(CdMgTe)。例如,半导体本体可以是磁性直拉(MCZ)或浮置区带(FZ)或外延沉积的硅半导体本体。
例如,布线金属层结构可以对应于在半导体本体或半导体衬底上的布线区域的一个布线层级或者是其一部分。在一些示例中,在多个布线层级的情况下,包括布线金属层的一个布线层级可以被定位为最接近半导体本体。在一些其它示例中,一个或多个进一步的布线层级可以被布置在包括布线金属层的一个布线层级和半导体本体之间。布线区域可以包括两个、三个、四个或者甚至更多的布线层级。每个布线层级可以是由单一的一个导电层或者导电层的堆叠形成的,例如(多个)金属层和/或诸如高掺杂多晶硅的高掺杂半导体材料。例如,可以平版印刷图案化一些或所有的布线层级。通过图案化布线层级,可以形成任何的布线线路、接合焊盘、接触区域或者其任何组合。在堆叠的布线层级之间,可以布置有中间电介质。(多个)接触插塞和/或(多个)接触线路可以被形成在中间电介质中的开口中,以将不同布线层级的部分(例如布线线路或接触区域)彼此电连接。例如,电介质层也可以被布置在半导体本体和最接近半导体本体的布线层级之间。(多个)接触插塞和/或(多个)接触线路可以被形成在电介质层中的开口中,以电连接最接近半导体本体的布线层级的部分(例如布线线路或接触区域)和半导体本体中的有源区域,例如半导体本体中的掺杂区,诸如二极管的阳极区或阴极区或者IGBT的发射极区、基极区或集电极区或者IGFET的源极区、本体区或漏极区。
类似于布线金属层结构,接合焊盘金属层结构可以对应于在半导体本体或半导体衬底上的布线区域的另一布线层级或者是其一部分。例如,与布线金属层结构的布线层级相比接合焊盘金属层结构的布线层级可以具有更大的距半导体本体的竖向距离。例如,接合焊盘金属层结构可以是如下的金属布线层级的一部分或者对应于如下的金属布线层级:该金属布线层级例如在布线区域中的布线层级当中具有最大的到半导体本体的竖向距离。例如,接合焊盘金属层结构可以是连续的金属结构。
电介质层结构可以包括一层或各层的组合,例如电介质层的层堆叠,例如氧化物层(诸如热氧化物层或沉积的氧化物层),例如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、氮氧化物或氮化物层、高k电介质层或低k电介质层、未掺杂的或本征的半导体材料(诸如未掺杂的多晶硅)。电介质层结构可以构成或形成在竖向上被布置在布线层级之间的一个中间电介质层的一部分。在一些示例中,电介质层结构的形成方法包括物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(或PECVD)、旋涂、以及其它适用的方法。
布线区域的任何层(例如电介质层结构、或接合焊盘金属层结构、或布线金属层结构)的层厚度可以对应于相应的层的竖向延伸,例如是沿着垂直于半导体本体的主表面层级的竖向方向测量的。
例如,电介质层结构可以充当应力吸收和结构调节层。虽然典型的中间电介质层关注于相邻的布线层级之间的电隔离,但是电介质层结构更薄,并且将使得能够有在接合焊盘金属层结构和布线金属层结构之间的低电阻电连接。
此外,如将在下面描述的那样,电介质层结构可以使得能够有许多技术益处。
例如,当通过图案化相应的布线层级来形成接合焊盘金属层结构时,电介质层结构可以用作为蚀刻停止层。因此,这可以允许在所要求的区域(例如接合焊盘)中具有更厚的金属化,并且保护进一步下方的金属布线(例如包括布线金属层结构的布线层级)免受蚀刻。由此,如果电介质层被形成得足够厚以提供被覆盖的结构的侧壁覆盖,则切口中的金属结构(例如处理控制监控器、PCM结构)或非接合焊盘区域中的金属结构(例如金属路由或栅极流道)可以被形成为仅具有只包括金属布线层结构的布线层的厚度。由此,锯切通过结构成为可能,并且可以避免双切口或块PCM(其减少每个晶片的有源区域的量并且增加芯片成本)的实施。芯片上的例如用于路由的非接合焊盘金属结构可以仅保持在布线金属层结构的厚度上。因此,可以降低修改临界尺寸的要求。由于(多个)钝化层可以仅覆盖形貌台阶直到布线金属层结构的厚度,因此分离地图案化布线金属层结构和接合焊盘金属层结构的可能性也可以有利于(多个)厚的硬钝化层的使用。由此,可以避免在高形貌台阶处出现的薄钝化区域、裂缝和层中断的形成。
在布线金属层结构和接合焊盘金属层结构之间的电介质层结构可以是被单独地调节的。例如,由于电介质层结构是足够厚以具有机械相关性的,因此电介质层结构可以吸收接合力。该布局可以被适配于不同接合处理的要求,例如布线材料、接合管脚数量。
由于布线金属层结构和接合焊盘金属层结构之间的界面的仅一部分被覆盖有电介质层结构,因此即使电介质层结构的厚度太厚而不导电,也不存在电流的减少或者存在可忽略的电流减少。电介质层结构的厚度可以被平衡以提供充分的针对接合力的缓冲能力,同时在没有空隙形成的情况下沉积接合焊盘金属层结构仍然是可能的。因此,电介质层结构的厚度可以取决于电介质层结构的内部部分(例如中心部分)的布局。
与单个的厚金属化层相比,提供电介质层结构可以允许减小接合焊盘金属层结构的材料的晶粒大小。如果沉积基于铝的金属化层,则在金属退火期间生长的平均晶粒大小可以在整个层厚度的范围内。例如,与具有在布线金属层结构和接合焊盘金属层结构之间的电介质层结构的堆叠相比,在没有任何中间层的情况下沉积的厚金属层可能具有更大的平均晶粒大小。此外,图案化的电介质层结构的边缘、角部和形貌可以充当用于金属晶粒生长的起始点。这可以造成更小的晶粒和更高的金属晶粒总数。这可以再次改进接合力的吸收能力。考虑到电介质层结构的设计的灵活性,可以例如设定对称性以使得能够进行接合焊盘金属层结构的晶粒大小和晶粒定向的特定调节。
可以在接合焊盘金属层结构和钝化层结构之间的重叠区域处形成中间电介质,例如作为电介质层结构的一部分的保护性电介质框架。该中间电介质可以充当对于在封装之外的化学侵蚀或离子污染的附加保护。
例如,电介质层结构的层厚度可以在从50nm至1μm的范围内。例如,电介质层结构的层厚度可以小于500nm。
例如,电介质层结构的横向端部可以在横向上突出接合焊盘金属层结构的横向端部。这可以允许电介质层结构在通过图案化相应的布线层级来形成接合焊盘金属层结构时用作为蚀刻停止层。
例如,半导体器件可以进一步包括钝化层结构,其在电介质层结构的外周部分中布置在电介质层结构和布线金属层结构之间。例如,外周部分可以部分地或完全地在横向上围绕电介质层结构。例如,钝化层结构可以覆盖布线金属层结构的边缘部分。形成钝化层结构以保护形成在半导体本体中的集成电路元件或分立半导体器件并且还保护布线金属层结构的边缘部分。在一些示例中,钝化层结构是气密层以防止湿气接触到器件元件(例如pn结或布线)。在一些示例中,钝化层结构是由聚合物(诸如聚酰亚胺或聚苯并噁唑)、氧化物、氮氧化物、氮化物或其它电介质材料中的任何一种或其任何组合形成的。在一些示例中,附加的钝化层被形成在布线区域(未示出)之上并且在接合焊盘金属层结构同一层级处或者在其上方。在一些示例中,钝化层结构具有在从大约0.1μm至大约3μm的范围内的厚度。在一些示例中,形成方法包括物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(或PECVD)、旋涂和其它适用方法。
例如,布线金属层结构或接合焊盘金属层结构中的至少之一(典型地,布线金属层结构和接合焊盘金属层结构)可以包括如下中的至少之一:纯金属,金属合金或金属化合物。在一些示例中,布线金属层和/或接合焊盘金属层结构可以由纯金属、金属合金或金属化合物构成(除了杂质)。布线金属层结构和/或接合焊盘金属层结构可以包括或者可以是金属层堆叠。例如,布线金属层结构和/或接合焊盘金属层结构可以包括如下中的至少之一:Al、Cu、铝铜合金(例如AlCu)、AlSi或AlSiCu。典型地,布线金属层结构和/或接合焊盘金属层结构包括铝。布线金属层结构和/或接合焊盘金属层结构可以包括相同的金属化合物或不同的金属化合物。
例如,布线金属层结构或其一部分包括至少Cu和Al的第一金属化合物或AlSiCu。
例如,接合焊盘金属层结构或其一部分包括至少Cu与Al的第二金属化合物。第一金属化合物和第二金属化合物可以是相同的或不同的。
例如,布线金属层结构或其一部分包括AlSiCu,并且接合焊盘金属层结构或其一部分包括AlCu。
第一金属化合物可以是由铝按至少50%、至少70%、至少85%、或者甚至至少94%的物质的量构成的。第二金属化合物可以是由铝按至少50%、至少70%、至少85%或者甚至至少94%的物质的量构成的。物质的量可以指代在相应的金属化合物中的原子的数目。例如,第一金属化合物中的原子的至少50%、至少70%、至少85%或者甚至至少94%可以是铝原子。例如,第一金属化合物中的原子的至少50%、至少70%、至少85%或者甚至至少94%可以是铝原子。在相应的金属化合物中的原子的剩余百分比可以是例如Si原子和/或Cu原子。
AlCu可以是例如仅包括铝和铜的金属化合物。AlSiCu可以是例如仅包括铝、硅和铜的金属化合物。AlSiCu可以比AlCu软。AlCu可以呈现比AlSiCu大的硬度。
例如,电介质层结构可以是氧化物层、氧氮化硅或氮化硅层和未掺杂(例如非意图地掺杂的或本征的)多晶硅层中的任何一个或任何组合(例如堆叠组合)。
例如,接合焊盘金属层结构可以包括中心部分和外周部分。接合焊盘金属层结构上的任何布线接合可以位于中心部分中。
例如,接合焊盘金属层结构上的布线接合的数量可以等于两个或更多,例如三个、四个、五个或者甚至更多。
例如,电介质层结构可以包括闭合的外周部分。例如,电介质层结构可以采用闭合环的形式。电介质层结构可以进一步包括在闭合环内部和/或至少部分地被闭合环围绕的一个或多个电介质层部分。例如,在闭合环内部和/或由闭合环围绕的一个或多个电介质层部分可以在横向上与闭合环间隔开和/或与闭合环合并。例如,闭合的外周部分可以邻接接合焊盘金属层结构的外周部分。
例如,电介质层结构可以包括中心部分(例如自由浮置氧化物结构),其被通过电介质层结构中的分离的开口与闭合的外周部分横向地间隔开。例如,分离的开口也可以采用闭合环的形式。这可以允许降低在接合焊盘区域之外(例如钝化层)的裂缝传播的风险。可以允许自由浮置氧化物结构在接合处理期间断裂而不影响外部区域。对接合力的吸收可以允许在接合期间的更高的超声功率而没有针对下面的半导体本体的材料(例如硅)的风险。这可以造成用于布线接合处理条件的窗口的展宽,使得能够还通过使用更硬的接合材料(例如AlMg)来实现更高的功率循环能力。
例如,电介质层结构的中心部分中的开口的最大横向延伸可以小于布线金属层结构的层厚度和接合焊盘金属层结构的层厚度的总和。例如,电介质层的中心部分中的开口可以被填充有导电材料,例如接合焊盘金属层结构的导电材料的一部分,其电连接接合焊盘金属层结构和布线层金属结构。在一些其它示例中,电介质层结构的中心部分中的开口的最大横向延伸可以小于电介质层结构的层厚度以及布线金属层结构的层厚度以及接合焊盘金属层结构的层厚度的总和。
例如,电介质层结构的中心部分中的开口的最小横向延伸可以等于或大于电介质层结构的层厚度的两倍。
例如,电介质层结构可以覆盖接合焊盘金属层结构的中心部分中的接合焊盘金属层结构的底部的25%至90%、或35%至80%、或50%至70%。
制造半导体器件的方法的示例可以包括形成布线金属层结构。方法可以进一步包括形成被直接布置在布线金属层结构上的电介质层结构。方法可以进一步包括形成被至少部分地直接布置在电介质层结构上的接合焊盘金属层结构。电介质层结构的层厚度可以在布线金属层结构的层厚度的1%至30%的范围内。布线金属层结构和接合焊盘金属结构可以被通过电介质层结构中的开口电连接。
例如,方法可以包括在形成电介质层结构之前在布线金属层结构的至少一部分上形成钝化层结构。在一些示例中,钝化层结构可以被形成为具有在从大约0.1μm到大约3μm的范围内的厚度。在一些示例中,钝化层结构可以是通过如下之一或通过如下的任何组合形成的:物理气相沉积(PVD)、化学气相沉积(CVD)、等离子体增强CVD(或PECVD)、旋涂以及其它适用的方法。
例如,形成电介质层结构和形成接合焊盘金属层结构可以包括在布线金属层结构上以及在钝化层结构上形成电介质层。可以例如通过一个或多个的(多个)掩模蚀刻处理来在接合焊盘区域的中心部分中图案化电介质层。此后,可以在电介质层上形成接合焊盘金属层。
例如,方法可以进一步包括通过图案化接合焊盘金属层来形成接合焊盘金属层结构。图案化接合焊盘金属层可以包括使用电介质层作为蚀刻停止层的蚀刻处理。
例如,方法可以进一步包括在形成接合焊盘金属层之后在围绕接合焊盘区域的中心部分的部分中图案化电介质层。
在上面和下面描述的示例和特征可以被组合。
关于上面的示例描述的功能和结构细节将同样适用于在各图中图示并且在下面进一步描述的示例性示例。
下面,与随附附图有关地解释半导体器件的进一步的示例。关于上面的示例描述的功能和结构细节将同样适用于在各图中图示并且在下面进一步描述的示例性实施例。
图1示意性地并且示例性地示出半导体器件100的横截面视图的区段。
半导体器件100包括布线金属层结构102。电介质层结构被直接布置在布线金属层结构102的至少一部分上。钝化层结构114的至少一部分被布置在电介质层结构104和在电介质层结构104的外周部分中的布线金属层结构102之间。接合焊盘金属层结构106被至少部分地直接布置在电介质层结构104上。接合焊盘金属层结构106包括中心部分1181和外周部分1182。
钝化层结构114可以是在形成接合焊盘金属层结构106的金属层之后通过在围绕接合焊盘金属层结构106的中心部分1181的部分中图案化电介质层结构104的电介质层而形成的。
电介质层结构104的层厚度td在布线金属层结构102的层厚度tw的1%至30%、或3%至25%、或5%至20%、或5%至15%、或10%至20%的范围内。布线金属层结构102和接合焊盘金属结构106被通过电介质层结构104中的开口108电连接。
电介质层结构104的横向端部110在横向上突出接合焊盘金属层结构106的横向端部112。
图2A至图2E示意性地和示例性地示出半导体器件的平面视图的区段以用于图示电介质层结构104的示例性布局。
参照图2A、图2B的示意性平面视图,电介质层结构104包括中心部分1042,其被通过电介质层结构104中的分离的开口120与闭合的外周部分1041在横向上间隔开。虽然在图2A中图示的示例中电介质层结构104的中心部分1042是连续的,但是在图2B中图示的示例中电介质层结构104的中心部分1042包括多个电介质岛状部10421。
电介质层结构104的中心部分1042中的开口108的最大横向延伸l可以小于布线金属层结构102的层厚度tw与接合焊盘金属层结构106的层厚度的总和。
例如,由电介质层结构104对接合焊盘金属层结构106的中心部分1181的底部的覆盖可以在25%至90%或35%至80%或50%至70%的范围内。
参照图2C、图2D、图2E的示意性平面视图,电介质层结构104的中心部分1042与电介质层结构104的闭合外周部分1041合并。在一些示例中,中心部分1042中的开口108可以如在图2C、图2D中图示的那样规则地布置。在一些其它示例中,例如,一些开口108可以关于形状和布置而与其它开口不同。例如,可以关于接合焊盘金属层结构106的特定区域上的机械稳定性和/或为了使得能够有在接合焊盘金属层结构106中的特定晶粒大小和定向来选取电介质层结构104的中心部分1041的布局。
图3A至图3C示意性地并且示例性地示出半导体器件100的横截面视图的区段以用于图示包括布线金属层结构102、电介质结构104以及接合焊盘金属层结构106的布线区域的示例性配置。接合焊盘金属层结构106上的布线接合121的数目等于二或更多。
在图3A的示例中,布线金属层结构102直接邻接半导体本体124的表面122。在半导体本体124中,形成分立的半导体或集成电路的器件元件,例如掺杂区、电介质、沟槽。
在图3B的示例中,层间电介质126被布置在布线金属层结构102和半导体本体124的表面122之间。接触插塞或接触线路128延伸通过层间电介质126以用于将布线金属层结构102电连接到半导体本体124。
在图3C的示例中,一个或多个的(多个)层间电介质和一个或多个的(多个)布线层级可以被布置在布线金属层结构和半导体本体124的表面122之间。
连同先前描述的示例和各图中的一个或多个一起提及和描述的方面和特征也可以与其它示例中的一个或多个组合以便替代其它示例的类似特征或者以便附加地将特征引入到其它示例。
虽然已经在此图示和描述了具体实施例,但是本领域普通技术人员将领会,在不脱离本发明的范围的情况下,各种各样的替换和/或等同的实现可以代替所示出和描述的具体实施例。本申请意图覆盖在此讨论的具体实施例的任何适配或变化。因此意图的是本发明仅受权利要求及其等同物限制。
Claims (23)
1.一种半导体器件(100),包括:
布线金属层结构(102);
电介质层结构(104),其被直接布置在布线金属层结构(102)上;
接合焊盘金属层结构(106),其被至少部分地直接布置在电介质层结构(104)上,其中
电介质层结构(104)的层厚度(td)在布线金属层结构(102)的层厚度(tw)的1%至30%的范围内,
布线金属层结构(102)和接合焊盘金属结构(106)被通过电介质层结构(104)中的开口(108)电连接,并且
接合焊盘金属层结构(106)或其一部分包括按至少50%的物质的量的Al。
2.根据前项权利要求所述的半导体器件(100),其中布线金属层结构(102)或其一部分包括按至少50%的物质的量的Al。
3.根据前述权利要求中的任何一项所述的半导体器件(100),其中布线金属层结构(102)或其一部分包括至少Cu和Al的第一金属化合物或AlSiCu。
4.根据前述权利要求中的任何一项所述的半导体器件(100),其中接合焊盘金属层结构(106)或其一部分包括至少铜和铝的第二金属化合物。
5.根据前述权利要求中的任何一项所述的半导体器件(100),其中布线金属层结构(102)或其一部分包括AlSiCu,并且接合焊盘金属层结构(106)或其一部分包括AlCu。
6.根据前述权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)的层厚度(td)在从50nm至1μm的范围内。
7.根据前述权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)的横向端部(110)在横向上突出接合焊盘金属层结构(106)的横向端部(112)。
8.根据前述权利要求中的任何一项所述的半导体器件(100),进一步包括钝化层结构(114),钝化层结构(114)被布置在电介质层结构(104)和电介质层结构(104)的外周部分(116)中的布线金属层结构(102)之间。
9.根据前述权利要求中的任何一项所述的半导体器件(100),进一步包括半导体本体,其中布线金属层结构(102)直接邻接半导体本体的表面。
10.根据前述权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)包括如下中的任何一个或如下中的任何组合:氧化物层、氧氮化硅层、或氮化物层、或未掺杂的多晶硅层。
11.根据前述权利要求中的任何一项所述的半导体器件(100),其中所述半导体器件(100)是功率半导体器件。
12.根据前述权利要求中的任何一项所述的半导体器件(100),其中接合焊盘金属层结构(106)包括中心部分(1181)和外周部分(1182),并且接合焊盘金属层结构(106)上的任何布线接合位于中心部分(1181)中。
13.根据前项权利要求所述的半导体器件(100),其中接合焊盘金属层结构(106)上的布线接合的数目等于二或更大。
14.根据前述两项权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)包括闭合的外周部分(1041)。
15.根据前项权利要求所述的半导体器件(100),其中电介质层结构(104)包括中心部分(1042),中心部分(1042)被通过电介质层结构(104)中的分离的开口(120)与闭合的外周部分(1041)在横向上间隔开。
16.根据前述两项权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)的中心部分(1042)中的开口的最大横向延伸(l)小于布线金属层结构(102)的层厚度(tw)和接合焊盘金属层结构(106)的层厚度的总和。
17.根据前述三项权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)的中心部分(1042)中的开口(108)的最小横向延伸等于或大于电介质层结构(104)的层厚度(td)的两倍。
18.根据前述三项权利要求中的任何一项所述的半导体器件(100),其中电介质层结构(104)覆盖接合焊盘金属层结构(106)的中心部分(1181)中的接合焊盘金属层结构(106)的底部的25%至90%。
19.一种制造半导体器件(100)的方法,包括:
形成布线金属层结构(102);
形成被直接布置在布线金属层结构(102)上的电介质层结构(104);
形成被至少部分地直接布置在电介质层结构(104)上的接合焊盘金属层结构(106),其中
电介质层结构(104)的层厚度(td)在布线金属层结构(102)的层厚度(tw)的1%至30%的范围内,以及
布线金属层结构(102)和接合焊盘金属结构(106)被通过电介质层结构(104)中的开口(108)电连接。
20.根据前项权利要求所述的方法,进一步包括:
在形成电介质层结构(104)之前在布线金属层结构(102)的至少一部分上形成钝化层结构(114)。
21.根据前项权利要求所述的方法,其中形成电介质层结构(104)和形成接合焊盘金属层结构(106)包括:
在布线金属层结构上以及在钝化层结构(114)上形成电介质层;
在接合焊盘区域的中心部分中图案化电介质层;并且此后
在电介质层上形成接合焊盘金属层。
22.根据前项权利要求所述的方法,进一步包括:
通过图案化接合焊盘金属层来形成接合焊盘金属层结构(106),其中图案化接合焊盘金属层包括使用电介质层作为蚀刻停止层的蚀刻处理。
23.根据前述两项权利要求中的任何一项所述的方法,进一步包括:
在形成接合焊盘金属层之后在围绕接合焊盘区域的中心部分的部分中图案化电介质层。
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