CN114068698A

CN114068698A - Power semiconductor element and forming method thereof

Info

Publication number: CN114068698A
Application number: CN202110890138.3A
Authority: CN
Inventors: 陈志濠; 敦俊儒; 沈依如
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2020-08-04
Filing date: 2021-08-04
Publication date: 2022-02-18
Also published as: TWI788692B; TW202207472A

Abstract

The invention discloses a power semiconductor element and a forming method thereof, wherein the power semiconductor element comprises: a substrate; a stack on the substrate, comprising, in order, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure; a first electrode on the stack layer and forming an ohmic contact with the stack layer; a second electrode on the lamination layer and forming Schottky contact with the lamination layer; and a group V element supply layer under the second electrode, covering a part of the surface of the III-V semiconductor barrier structure.

Description

Power semiconductor element and forming method thereof

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device.

Background

A High Electron Mobility Transistor (HEMT) is a Field Effect Transistor (FET). The gate metal layer of the hemt is mostly in contact with the underlying epitaxial layer with nickel metal, which is also called Schottky contact. The hemt has physical characteristics of high breakdown voltage (breakdown voltage) and high energy gap, and can be operated at high temperature or under high voltage and high current. When the Schottky contact between the gate metal layer and the epitaxial layer is not perfect, the device is prone to failure and has a short lifetime.

Disclosure of Invention

A power semiconductor component, comprising: a substrate; a stack on the substrate, wherein the stack comprises, in order, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure; the first electrode is positioned on the lamination layer and forms ohmic contact with the lamination layer; the second electrode is positioned on the lamination layer and forms Schottky contact with the lamination layer; and a group V element supply layer located under the second electrode and covering a portion of the surface of the III-V semiconductor barrier structure.

A method for forming a power semiconductor element comprises the following steps: providing a substrate; forming a stack on a substrate, wherein the stack comprises, in order, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure; forming a first electrode on the stack; forming a group V element supply layer on the stack and covering a portion of the surface of the III-V semiconductor barrier structure; and forming a second electrode on the group V element supply layer.

Drawings

Aspects of the invention will be described in detail below with reference to the attached drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.

FIGS. 1A-1G are schematic cross-sectional views illustrating intermediate stages in the formation of a power semiconductor device according to an embodiment of the invention;

FIGS. 2A-2H are schematic cross-sectional views illustrating intermediate stages in the formation of a power semiconductor device according to another embodiment of the present invention;

fig. 3A-3D are schematic diagrams illustrating structural changes of the surface of a III-V semiconductor layer before and after surface treatment according to some embodiments of the present invention.

Description of the symbols

10,20 power semiconductor element

30 surface of

32 III-V semiconductor layer

34 nitrogen deficient compound layer

36 repair compound layer

38 plasma etching

40: accumulation of group III elements

42 surface treatment

44 substance (or a component thereof)

Deposition process of 46V group element supply layer

48 a supply layer of a V group element

100,200 base plate

110,210 stack

112,212 III-V semiconductor nucleation layer

114,214 group III-V semiconductor buffer structure

116,216 III-V semiconductor channel structure

118,218 III-V semiconductor barrier structures

120,220 dielectric layer

130S,130G,130D,230S,230G,230D, opening

135,235 surface treatment

140,240 first electrode

150,250: third electrode

260 groove

170,270V group element supply layer

280 insulating layer

190,290: second electrode

Detailed Description

The following disclosure provides many embodiments for implementing different features of the invention. Specific examples of components and arrangements are described below, but these examples are not intended to limit the embodiments of the present invention. For example, references in the description to a first feature being formed on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Unless otherwise specified, like reference numerals are used on like elements and are formed from the same or similar materials using the same or similar processes.

Moreover, spatially relative terms, such as "below …", "below", "above …", "above", and the like, may be used herein to describe a relationship of one element or component to another element or component as illustrated. These spatial terms are intended to encompass different orientations of the device in use or operation. When the device is rotated to other orientations (rotated 90 or other orientations), the spatially relative descriptors used herein should be interpreted as such with respect to the rotated orientation.

Embodiments of the present invention provide a power semiconductor device and a method for forming the same, which are particularly suitable for a High Electron Mobility Transistor (HEMT). In some embodiments, a passivation layer (passivation layer) is deposited to protect the epitaxial layers on the substrate prior to the fabrication of any transistor structures. In the process of fabricating the electrode, it is necessary to etch the passivation layer in a predetermined region so that a subsequently formed electrode (e.g., a gate electrode) can be electrically contacted (e.g., Schottky contact) with an underlying epitaxial layer. The structure of the semiconductor compound in the epitaxial layer can be damaged due to the plasma bombardment used to etch the passivation layer, causing defects. The defects of the epitaxial layer under the passivation layer caused by the etching process are repaired by depositing a compound containing a group V element after etching the passivation layer (passivation layer) and before forming the electrode. Therefore, the problem of failure of the semiconductor element is reduced, and the characteristics and the reliability of the semiconductor element are improved.

Fig. 1A-1G are cross-sectional views illustrating intermediate stages in the fabrication of a power semiconductor device 10 according to some embodiments of the present invention. In the present embodiment, the power semiconductor device 10 is a depletion mode (D-mode) HEMT. As shown in fig. 1G, the power semiconductor element 10 includes: substrate 100, stack 110 on substrate 100 includes a group III-V semiconductor nucleation layer 112, a group III-V semiconductor buffer structure 114, a group III-V semiconductor channel structure 116, a group III-V semiconductor barrier structure 118, a dielectric layer 120 on a portion of stack 110, a first electrode (e.g., source) 140 and a third electrode (e.g., drain) 150 on stack 110, respectively, a second electrode (e.g., gate) 190 on stack 110 and between first electrode 140 and third electrode 150, and a group V element supply layer 170 under second electrode 190 covering a portion of a surface of group III-V semiconductor barrier structure 118. The second electrode 190 comprises a metal or metal compound having a higher work function than the group III-V semiconductor barrier structure 118. A high resistance contact, such as a Schottky contact, is formed between the second electrode 190 and the III-V semiconductor barrier structure 118.

In the manufacturing steps of the power semiconductor device 10, as shown in fig. 1A, a stack 110 is first formed on a substrate 100. Formation of stack 110 includes forming a group III-V semiconductor nucleation layer 112 on substrate 100, forming a group III-V semiconductor buffer structure 114 over group III-V semiconductor nucleation layer 112, forming a group III-V semiconductor channel structure 116 over group III-V semiconductor buffer structure 114, and forming a group III-V semiconductor barrier structure 118 over group III-V semiconductor channel structure 116. The III-V semiconductor buffer structure 114 may comprise a single layer or multiple layers (not shown) having multiple sub-layers. In some embodiments, the III-V semiconductor buffer structure includes a superlattice structure (not shown) formed by alternately stacking two sub-layers.

In some embodiments, the substrate 100 is a semiconductor substrate or an insulating substrate. The material of the insulating substrate includes sapphire. The material of the semiconductor substrate includes an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon carbide, gallium nitride, aluminum gallium nitride, or a combination thereof. Alternatively, the substrate 100 may be a multi-layer (multi-layered) substrate, such as a silicon-on-insulator (SOI) substrate. In other embodiments, the stack 110 epitaxially formed on the growth substrate may be bonded to the substrate 100 by a wafer transfer (wafer transfer) process, and the growth substrate may be removed and the subsequent processes may be continued, wherein the substrate 100 may comprise glass, plastic, ceramic, metal, etc. In the present embodiment, the substrate 100 is, for example, a silicon substrate, and has a thickness of about 1000 μm to 1200 μm. Different epitaxial conditions may be used to grow epitaxial structures on silicon substrates having different crystal planes, including, for example, Si (111) or Si (110). The above-described group III-V semiconductor nucleation layer 112, group III-V semiconductor buffer structure 114, group III-V semiconductor channel structure 116, and group III-V semiconductor barrier structure 118 are epitaxially grown on the (111) plane of the silicon substrate and grown along the [0001] direction.

In some embodiments, the materials of the group III-V semiconductor nucleation layer 112, group III-V semiconductor buffer structure 114, group III-V semiconductor channel structure 116, and group III-V semiconductor barrier structure 118 comprise a group III-V compound semiconductor material, such as a group III nitride. The group III nitride includes In_xAl_yGa_1-(x+y)N, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1, such as gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (InAlN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), or combinations thereof. The above-described III-V compound semiconductor materials may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or a combination thereof. The channel structure 116 and the barrier structure 118 may be respectively composed of a single layer or a plurality of sublayers.

The III-V semiconductor nucleation layer 112 has a thickness between about 1nm and about 500nm, for example about 200 nm. The III-V semiconductor nucleation layer 112 may mitigate lattice differences between the substrate 100 and overlying layers to improve epitaxial quality. In other embodiments, the group III-V semiconductor buffer structure 114 may be formed directly on the substrate 100 without disposing the group III-V semiconductor nucleation layer 112, thereby simplifying the process steps and achieving the improved effect.

In some embodiments, the material of the III-V semiconductor buffer structure 114 comprises aluminum gallium nitride. The thickness of the III-V semiconductor buffer structure 114 is between about a few microns (μm) or tens of microns, such as between 4.0 μm and 5.0 μm, such as about 4.5 μm. The material of the III-V semiconductor buffer structure 114 is doped or undoped. In some embodiments, the III-V semiconductor buffer structure 114 is formed of a carbon-doped material to increase the resistance of the III-V semiconductor buffer structure 114, such as carbon-doped aluminum gallium nitride (carbon-doped AlGaN), the carbon doping concentration of which may be gradually changed along the growth thickness direction or may be constant. The III-V semiconductor buffer structure 114 may mitigate strain (strain) caused by lattice mismatch between the substrate 100 and the III-V semiconductor channel structure 116 to prevent defects from forming in the overlying III-V semiconductor channel structure 116.

In some embodiments, the material of the III-V semiconductor channel structure 116 has a first energy level and a first lattice constant, and the material of the III-V semiconductor barrier structure 118 has a second energy level and a second lattice constant. The second energy level is greater than the first energy level and the second lattice constant is different from (e.g., less than) the first lattice constant. In the present embodiment, the III-V semiconductor channel structure 116 and the III-V semiconductor barrier structure 118 are intrinsic semiconductors. The III-V semiconductor channel structure 116 and the III-V semiconductor barrier structure 118 themselves form spontaneous polarization (piezoelectric polarization) and piezoelectric polarization (piezoelectric polarization) due to their different lattice constants, thereby generating a two-dimensional electron gas (not shown) at the heterojunction between the III-V semiconductor channel structure 116 and the III-V semiconductor barrier structure 118. The material of the III-V semiconductor channel structure 116 thus includes gallium nitride, aluminum gallium nitride, indium gallium nitride, or aluminum indium gallium nitride. The III-V semiconductor barrier structure 118 is made of a material including gan, algan, ingan, or alingan, and has a higher energy level than the III-V semiconductor channel structure 116. In the present embodiment, the III-V semiconductor channel structure 116 comprises gallium nitride and the material of the III-V semiconductor barrier structure 118 comprises aluminum gallium nitride. The III-V semiconductor channel structure 116 has a thickness between about 100nm and 300nm, for example about 200 nm. The III-V semiconductor barrier structure 118 (aluminum gallium nitride) has a thickness between about 10nm and 30nm, for example about 20 nm.

According to some embodiments of the present invention, the III-V semiconductor barrier structure 118 includes a layer of high-level material and a capping layer (not shown) on the layer of high-level material. According to an embodiment of the present invention, the cap layer has a material energy level higher than that of the high-energy-level material layer, and the cap layer increases the overall energy level of the III-V semiconductor barrier structure 118, thereby increasing the concentration of the two-dimensional electron gas. According to an embodiment of the invention, the energy level of the high-energy-level material layer is higher than that of the cap layer, and the cap layer may be made of GaN and have a thickness between about 1nm and 50nm, for example, about 20nm to 50nm, or about 1nm to 10 nm. According to some embodiments, the formation of the cap layer helps to avoid current breakdown of the element.

As shown in fig. 1B, one or more dielectric layers 120 (also referred to as passivation layers) are formed over the III-V semiconductor barrier structure 118 to protect the III-V semiconductor barrier structure 118 from oxidation during subsequent processing. The material of the dielectric layer 120 includes an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride or silicon carbonitride), a silicide (e.g., phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG)), an oxynitride (e.g., silicon oxynitride), or a combination thereof. The dielectric layer 120 may be formed by Physical Vapor Deposition (PVD), such as evaporation or sputtering, Chemical Vapor Deposition (CVD), spin-on coating (spin-on coating), or combinations thereof. Although only one dielectric layer 120 is illustrated in fig. 1B, the invention is not limited thereto, and the dielectric layer 120 may be a multi-layer dielectric layer.

As shown in fig. 1C, an opening 130S, an opening 130G, and an opening 130D are formed in the dielectric layer 120 to expose portions of the upper surface of the underlying III-V semiconductor barrier structure 118, respectively. The opening 130S, the opening 130G, and the opening 130D will be locations where the first electrode 140, the second electrode 190, and the third electrode 150 are formed, respectively. The opening 130S, the opening 130G, and the opening 130D may be formed in the same process, or may be formed separately in different processes, such as forming the opening 130S and the opening 130D first, and then forming the opening 130G in another process. The formation of the

openings

130S,130G, and 130D includes, but is not limited to, a dry etching process, a wet etching process, or a combination thereof. Wet etchingThe process includes rinsing, spraying, etc. in an acidic solution such as dilute hydrofluoric acid (DHF), hydrofluoric acid (HF) solution, nitric acid (nitroic acid, HNO)₃) And/or acetic acid (CH)₃COOH), or an alkaline solution such as potassium hydroxide (KOH) solution and/or ammonia (ammonia), or other suitable wet etchant. The dry etching process includes plasma etching (ICP), inductively coupled plasma etching (RIE), or a combination thereof. In the present embodiment, the opening 130G is formed using a dry etching process.

As shown in fig. 1D, a first electrode 140 and a third electrode 150 are formed in the opening 130S and the opening 130D, respectively. In some embodiments, low resistance contacts, such as ohmic contacts, are formed between the first and

third electrodes

140, 150 and the III-V semiconductor barrier structure 118. The first electrode 140 and the third electrode 150 include a metal having a work function between 4.1 and 4.3, such as silver, aluminum, tungsten, tantalum, cadmium, zirconium, titanium, or a combination thereof. The material layers of the first electrode 140 and the third electrode 150 may be formed using physical vapor deposition, atomic layer deposition, plating (plating), or a combination thereof. Thereafter, the first electrode 140 and the third electrode 150 are formed using a photolithography process and an etching process. In some embodiments, a rapid thermal annealing process is performed after the first electrode 140 and the third electrode 150 are formed, so that the first electrode 140 and the third electrode 150 are respectively alloyed with the underlying stack 110, thereby reducing the resistance of the ohmic contact.

In some embodiments, a surface treatment 135 is performed in the opening 130G (the region where the second electrode is expected to be formed). The surface treatment 135 includes, but is not limited to, treating the surface of the III-V semiconductor barrier structure 118 with an acidic species. For example, phosphorus pentachloride (PCl) is used for the surface treatment 135₅) Hydrochloric acid (HCl), or combinations thereof, in a dip, spray, or other manner.

The inventors have discovered that in power semiconductor device processing, for example, etching processes (e.g., dry etching) used to form openings in dielectric layer 120 may cause defects to form on the surface of III-V semiconductor barrier structure 118, such as by the etching process causing the surface to lose the group V elements in its composition, thereby causing surface defects, such as the vacancy of group V elements and/or the formation of unwanted aggregates (aggregatates) of group III elements (e.g., gallium or aluminum) on the surface of the portion of III-V semiconductor barrier structure 118 exposed by openings, such as opening 130G. The group V vacancies and group III agglomerates (agglomerations) make the surface of the III-V semiconductor barrier structure 118 uneven. In some embodiments, surface treatment 135 is performed to remove the III-element deposits, to facilitate the coating of subsequent layers, and/or to facilitate the repair of group V voids on the surface of the III-V semiconductor barrier structure 118 by the V-element supply layer 170 formed in subsequent processes. The mechanism of the surface treatment 135 will be described in detail later in a schematic manner.

Fig. 3A-3D are schematic diagrams illustrating structural variations of the III-V semiconductor layer 32, such as the surface 30 of the III-V semiconductor barrier structure 118, before and after the surface treatment 42, in accordance with some embodiments of the present invention.

As shown in fig. 3A, III-V semiconductor layer 32 comprises, for example, aluminum gallium nitride, where aluminum and gallium are group III elements and nitrogen is a group V element. As shown in fig. 3B, the surface 30 of the III-V semiconductor layer 32 may be struck by plasma during a dry etching process, such as plasma etching 38. Since nitrogen has a relatively low atomic mass, the process of plasma etching 38 may knock nitrogen off of the III-V semiconductor layer 32, creating group V vacancies (nitrogen vacancies) at the surface 30 and converting the III-V semiconductor layer 32 into the nitride-deficient compound layer 34. In some embodiments, the surface of the nitrogen-deficient compound layer 34 is present in the form of dangling bonds (dangling bonds).

Surface 30 also has a group III metal buildup 40 (aluminum buildup and gallium buildup) accumulated thereon after the dry etch process. The surface treatment 42 of the surface 30 of the nitride deficient compound layer 34 may remove the group III element deposits 40 using an acidic substance.

Next, as shown in fig. 1E, a group V element supply layer 170 is conformally deposited on the surfaces of the dielectric layer 120, the first electrode 140, and the third electrode 150, and on the sidewalls and bottom surface of the opening 130G where the surface treatment 135 is completed. According to some embodiments of the present invention, the group V element vacancy is repaired by depositing the group V element supply layer 170 before forming the second electrode 190, which will be described in detail later in the schematic view (fig. 3C and 3D).

In some embodiments, the group V element supply layer 170 is a low dielectric constant (low k) dielectric layer, such as not greater than the dielectric constant of silicon dioxide, such as not greater than 3.7. In some embodiments, the material of group V element supply layer 170 includes a group V element compound such as a nitride. In some embodiments, the nitride comprises a metal nitride containing a metal element, such as a group III metal, e.g., titanium or indium. In the present embodiment, the material of the group V element supply layer 170 includes titanium nitride (TiN). According to some embodiments of the invention, the thickness of the group V element supply layer 170 may be between

And

between, e.g. about

And

in the meantime. If the thickness of the group V element supply layer 170 is less than

The film is not easily formed because the thickness is too small. If the thickness of the group V element supply layer 170 is greater than

It causes band discontinuity and produces a capacitance effect to lower the breakdown voltage. Physical vapor deposition (e.g., evaporation or sputtering), chemical vapor deposition, spin-on coating, combinations thereof, or the like can be usedThe group V element supply layer 170 is formed.

As shown in fig. 3C, in some embodiments, a substance (or component thereof) 44 formed by the surface treatment 42, such as a negatively charged ion of an acidic substance, is temporarily present at the stack surface 30, such as by temporarily bonding the negatively charged ion to a dangling bond of the surface. A group V element supply layer deposition process 46 is then performed on the surface 30 of the nitride deficient compound layer 34 to form a group V element supply layer 48 on the surface 30. As shown in fig. 3D, in the present embodiment, when the group V element supply layer 48 (e.g., titanium nitride) is deposited on the surface 30, the acidic material (or its component) 44 is displaced from the surface 30, and the group V element (e.g., nitrogen element) of the group V element supply layer 48 enters the crystal structure of the surface 30 and forms a chemical bond with the group III element of the surface 30 to form the repairing compound layer 36. In other words, the group V element-providing layer deposition process 46 on the stack surface 30 may provide a group V element (e.g., nitrogen element) to repair the group V element vacancies at the surface of the nitride-deficient compound layer 34. In some embodiments, the group III element (e.g., gallium) is chemically bonded to the group V element of the group V element supply layer 48 with a chemical displacement of 0.5 eV.

Furthermore, in some embodiments, after the step of performing the surface treatment 42 as described in fig. 3A to 3B, the step of depositing the group V element supply layer 170 may be omitted, and the second electrode 190 may be directly deposited on the III-V semiconductor barrier structure 118 in a region corresponding to the opening 130G. In other embodiments, the surface treatment 42 as described in fig. 3A-3B may be omitted, and the group V element supply layer 170 may be deposited directly on the III-V semiconductor barrier structure 118 in the region corresponding to the opening 130G, followed by deposition of the second electrode 190.

Next, as shown in fig. 1F, a second electrode 190 is deposited on the group V element supply layer 170 in a region corresponding to the opening 130G. In some embodiments, the material of the second electrode 190 comprises a conductive material, such as a metal, a metal compound, or a combination thereof. For example, the metal includes gold, nickel, platinum, palladium, iridium, titanium, chromium, tungsten, aluminum, copper, silver, alloys thereof, multi-layer structures thereof, or combinations thereof; the metal compound includes a compound of the above-mentioned metal, such as titanium nitride (TiN). In some embodiments, a Schottky contact is formed between the second electrode 190 and the III-V semiconductor barrier structure 118. The second electrode 190 is composed of a metal or a metal compound having a work function of more than 4.5 eV. The second electrode 190 may be formed in the same manner as the first electrode 140 or the third electrode 150. In some embodiments, the defects of the III-V semiconductor barrier structure 118 are repaired by the group V element supply layer 170, so that the Schottky contact characteristics between the second electrode 190 and the III-V semiconductor barrier structure 118 are better, the leakage current of the power semiconductor device 10 is reduced, and the threshold voltage can be maintained within the operable normal range.

In some embodiments, the surface treatment and the formation of the group V element supply layer 170 may be performed simultaneously in the opening 130G, the opening 130S, and the opening 130D. The formation steps of the first electrode 140, the third electrode 150 and the second electrode 190 can also be formed in the same process. For example, after forming the

openings

130S,130G, and 130D, a surface treatment is performed on the openings 130G, and/or the

openings

130S and 130D. Then, after the group V element supply layer 170 is formed on the opening 130G, the first electrode 140, the third electrode 150 and the second electrode 190 are formed on the positions corresponding to the opening 130S, the opening 130D and the opening 130G in the same process or different processes.

Next, as shown in fig. 1G, the exposed portion of the group V element supply layer 170 (the portion not covered by the second electrode 190) is removed using a dry etching process, a wet etching process, or a combination thereof as described above. According to some embodiments of the present invention, the process of the power semiconductor element 10 is completed after removing the exposed portion of the group V element-supplying layer 170.

Although the foregoing embodiments only describe the process to the second electrode 190, the invention is not limited thereto. For example, a planarized passivation layer (not shown) may be further formed on the surface of the power semiconductor device 10, and then an opening (not shown) is formed above the first electrode 140 and the third electrode 150 respectively by a patterning process, and a bonding pad metal (not shown) is deposited in the opening to directly contact the first electrode 140 and the third electrode 150.

Fig. 2A to 2H are schematic cross-sectional views illustrating intermediate stages in the manufacturing process of the power semiconductor device 20 according to another embodiment of the present invention. In the present embodiment, the power semiconductor element 20 is an enhancement mode (E-mode) HEMT. As shown in fig. 2H, the power semiconductor element 20 includes: substrate 200, stack 210 on substrate 200 including a group III-V semiconductor nucleation layer 212, a group III-V semiconductor buffer structure 214, a group III-V semiconductor channel structure 216, and a group III-V semiconductor barrier structure 218, a dielectric layer 220 on a portion of stack 210, a first electrode 240 (e.g., a source) and a third electrode 250 (e.g., a drain) on stack 210, a second electrode 290 (e.g., a gate) on stack 210 and between first electrode 240 and third electrode 250, and a group V element supply layer 270 under second electrode 290. The second electrode 290 comprises a metal or metal compound having a higher work function than the group III-V semiconductor channel structure 218. The power semiconductor device 20 and the power semiconductor device 10 have a difference in structure in that the group V element supply layer 270 of the power semiconductor device 20 covers a portion of the surface of the III-V semiconductor channel structure 216, and further includes an insulating layer 280 between the group V element supply layer 270 and the second electrode 290. A high resistance contact, such as a Schottky contact, is formed between the second electrode 290 and the group III-V semiconductor channel structure 216.

As shown in fig. 2A to 2D, a stack 210 is formed over a substrate 200. Formation of stack 210 includes sequentially forming a group III-V semiconductor nucleation layer 212, a group III-V semiconductor buffer structure 214, a group III-V semiconductor channel structure 216, and a group III-V semiconductor barrier structure 218 on substrate 200. One or more dielectric layers 220 are then formed over the III-V semiconductor barrier structure 218, and

openings

230S,230G, and 230D are formed over the dielectric layers 220 to expose portions of the upper surface of the underlying III-V semiconductor barrier structure 218, respectively. Then, the first electrode 240 and the third electrode 250 are formed in the opening 230S and the opening 230D, respectively.

In the present embodiment, the substrate 200, the group III-V semiconductor nucleation layer 212, the group III-V semiconductor buffer structure 214, the group III-V semiconductor channel structure 216, the group III-V semiconductor barrier structure 218, the dielectric layer 220, the opening 230S, the opening 230G, the opening 230D, the first electrode 240, and the third electrode 250 of the power semiconductor device 20 may be formed using the same materials and processes as the substrate 100, the group III-V semiconductor nucleation layer 112, the group III-V semiconductor buffer structure 114, the group III-V semiconductor channel structure 116, the group III-V semiconductor barrier structure 118, the dielectric layer 120, the opening 130S, the opening 130G, the opening 130D, the dielectric layer 120, the first electrode 140, and the third electrode 150 of the power semiconductor device 10, and therefore are not repeated.

Referring to fig. 2E, the difference between the power semiconductor device 20 and the power semiconductor device 10 is that a recess 260 is etched in the III-V semiconductor barrier structure 218 through the opening 230G, the recess 260 extending down along the opening 230G and exposing a portion of the upper surface of the III-V semiconductor channel structure 216. In some embodiments, the sidewalls of the recess 260 are formed by the sides of the group III-V semiconductor barrier structure 218 and the bottom of the recess 260 is formed by a portion of the upper surface of the group III-V semiconductor channel structure 216. In other embodiments, the sidewalls of the recess 260 are formed by the sides of the III-V semiconductor barrier structure 218 and the III-V semiconductor channel structure 216.

In some embodiments, the recess 260 functions to remove a portion of the III-V semiconductor barrier 218 to reduce the concentration of the two-dimensional electron gas thereunder or to leave no two-dimensional electron gas thereunder, so that the power semiconductor element 20 is in a non-conducting state (normally off) in a state where the second electrode 290 is not biased. The process for forming the recess 260 may be formed using a dry etching process, a wet etching process, or a combination thereof as described above, and will not be described herein. According to a specific embodiment, the formation of the recess 260 includes performing an anisotropic (anistropic) dry etching process followed by an isotropic (anistropic) wet etching process. The anisotropic dry etch process may use an argon plasma, while the isotropic wet etch process may use hydrogen chloride, an oxyacid (e.g., phosphoric acid or sulfuric acid), or a combination thereof.

In some embodiments, the differences in material and etch selectivity of the III-V semiconductor nucleation layer 212, the III-V semiconductor buffer structure 214, the III-V semiconductor channel structure 216, and the III-V semiconductor barrier structure 218 in the stack 210 are not significant. Therefore, it is difficult to precisely control the etching depth in the dry etching process, for example, when etching the III-V semiconductor barrier structure 218, a significant portion of the underlying III-V semiconductor channel structure 216 is likely to be etched away altogether. In other embodiments, a wet etching process is used in combination with an existing dry etching process to form the structure of the recess 260. In the predetermined depth of the groove 260, a dry etching process is first used to recess a predetermined depth of between about 60% and 80%, and then a wet etching process is used to recess the remaining predetermined depth of between about 20% and 40%. In some embodiments, the profile of the recess 260 has straight sidewalls on the top due to the anisotropic dry etching process and non-straight sidewalls on the bottom due to the isotropic wet etching process. The portion of the upper surface of the III-V semiconductor channel structure 216 exposed by the recess 260 may retain some integrity.

Referring to fig. 2E, in some embodiments, the sidewalls (i.e., the sides of the III-V semiconductor barrier structure 218) and/or the bottom surface (i.e., the upper surface of the III-V semiconductor channel structure 216) of the recess 260 are subjected to a surface treatment 235. The surface treatment 235 of the power semiconductor device 20 is the same as the surface treatment 135 of the power semiconductor device 10, and therefore is not repeated here. Referring also to the structural changes before and after the surface treatment 42 is performed on the surface 30 shown in fig. 3A-3D, in the present embodiment, the surface 30 is a side surface of the III-V semiconductor barrier structure 218 and/or an upper surface of the III-V semiconductor channel structure 216. Surface defects, such as group V vacancies, on the sides of the group III-V semiconductor barrier structure 218 and/or on the top surface of the group III-V semiconductor channel structure 216 caused by the etching process can be more effectively repaired by the group V element-supplying layer 270 through the surface treatment 235 step.

As shown in fig. 2F, a group V element supply layer 270 is conformally deposited on the surfaces of the dielectric layer 220, the first electrode 240, and the third electrode 250, and on the sidewalls and/or bottom surface of the recess 260. The material of the group V element supply layer 270 is the same as that of the group V element supply layer 170 of the foregoing embodiment. Next, an insulating layer 280 is conformally deposited on the group V element supply layer 270. In some embodiments, the insulating layer 280 is a high dielectric constant (high k) dielectric layer, which effectively prevents the threshold voltage from shifting, so that the power semiconductor device 20 remains normally off in the operating range. The insulating layer 280 may be formed in the same manner as the group V element supply layer 270. In addition, in other embodiments, after the surface treatment 235 is performed, the deposition of the group V element supply layer 270 may be omitted, and the insulating layer 280 may be directly deposited on the sidewalls and the bottom surface of the groove 260.

As shown in fig. 2G to 2H, the second electrode 290 is deposited on the insulating layer 280, corresponding to the region of the groove 260 and filling the groove 260, and the dry etching process, the wet etching process or the combination thereof is used to remove the group V element supply layer 270 and the portion of the insulating layer 280 not covered by the second electrode 290, thereby completing the process of the power semiconductor device 20.

Although the foregoing embodiments only describe the process to the second electrode 290, the invention is not limited thereto. For example, a planarized passivation layer (not shown) may be further formed on the surface of the power semiconductor device 20, an opening (not shown) may be formed above the first electrode 240 and the third electrode 250 by a patterning process, and a bonding pad metal (not shown) may be deposited in the opening to directly contact the first electrode 240 and the third electrode 250.

The power semiconductor device 20 has a mixed dielectric layer structure composed of a low-k dielectric layer (e.g., the group V element supply layer 270) and a high-k dielectric layer (e.g., the insulating layer 280) under the second electrode 290. The mixed dielectric layer structure of the power semiconductor device 20 can repair the sidewall and/or bottom of the recess 260 due to the vacancy of the group V element generated by the etching process, and maintain the threshold voltage within the normal range of operation.

According to some embodiments, the power semiconductor element 20 has a lower leakage current than the power semiconductor element 10. The

power semiconductor devices

10 and 20 of the above embodiments are transistors with three terminals (three terminals), i.e., three electrodes with first electrodes 140 and 240 (e.g., sources), third electrodes 150 and 250 (e.g., drains), and second electrodes 190 and 290 (e.g., gates). In other embodiments, the group V element supply layer described in the above embodiments can also be applied to a Diode (Diode) having two terminals (two terminal), such as a Schottky Barrier Diode (SBD) having a first electrode (e.g., an ohmic electrode) and a second electrode (e.g., a Schottky electrode). For example, Schottky barrier diodes may be constructed similar to

power semiconductor elements

10 and 20, and may include a substrate, a group III-V semiconductor nucleation layer, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, a group III-V semiconductor barrier structure, a dielectric layer, a group V element supply layer, and/or a recess and insulating layer. The difference between the schottky barrier diode and the

power semiconductor devices

10 and 20 is that the schottky barrier diode has only two electrodes, a schottky electrode and an ohmic electrode, on the stack. The material of the schottky electrode comprises the same material as the second electrode 190,290 of the

power semiconductor element

10,20 and forms a schottky contact with the epitaxial layer thereunder, and the material of the ohmic electrode comprises the same material as the

first electrode

140 and 240 and/or the

third electrode

150 and 250 of the

power semiconductor element

10,20 and forms an ohmic contact with the epitaxial layer thereunder. Similarly, a group V element supply layer as described in the previous embodiments may be formed on a surface of the stack (e.g., a surface of a III-V semiconductor barrier structure or a III-V semiconductor channel structure), and a Schottky electrode may be deposited on the group V element supply layer to improve device characteristics and reliability.

The components of the several embodiments are summarized above so that those skilled in the art to which the present invention pertains can more clearly understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should be understood that the equivalent constructions do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A power semiconductor component, comprising:

a substrate;

a stack on the substrate, wherein the stack comprises, in order, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure;

a first electrode on the stack layer and forming an ohmic contact with the stack layer;

a second electrode on the lamination layer and forming Schottky contact with the lamination layer; and

a group V element supply layer located under the second electrode and covering a portion of the surface of the III-V semiconductor barrier structure and/or the III-V semiconductor channel structure.

2. The power semiconductor device as claimed in claim 1, wherein the group V element supply layer comprises a metal nitride.

3. The power semiconductor device of claim 1, wherein said group V element supply layer has a thickness between about

And

to the thickness of (d) in between.

4. The power semiconductor device as claimed in claim 1, wherein the group V element of the group V element supply layer is chemically bonded to the group III element of the III-V semiconductor barrier structure.

5. The power semiconductor device of claim 1, further comprising a dielectric layer over said stack, wherein said dielectric layer has an opening exposing a portion of the upper surface of said III-V semiconductor barrier structure, said group V element supply layer is conformally disposed on the bottom and sidewalls of said opening, and said second electrode fills said opening.

6. The power semiconductor device as claimed in claim 1, further comprising a dielectric layer over the stack and having an opening, wherein the stack has a recess extending downward along the opening to expose a portion of the upper surface of the III-V semiconductor channel structure, the group V element supply layer is conformally disposed on the bottom and sidewalls of the recess, and the second electrode fills the recess.

7. A method for forming a power semiconductor element comprises the following steps:

providing a substrate;

forming a stack on the substrate, wherein the stack comprises, in order, a group III-V semiconductor buffer structure, a group III-V semiconductor channel structure, and a group III-V semiconductor barrier structure;

forming a group V element supply layer on the stack and covering a portion of the surface of the III-V semiconductor barrier structure; and

forming a second electrode on the group V element supply layer.

8. The method of claim 7, further comprising depositing a dielectric layer over the stack and etching an opening in the dielectric layer to expose a portion of the group III-V semiconductor barrier structure prior to forming the group V element supply layer; and performing a surface treatment on the exposed portion of the III-V semiconductor barrier structure; wherein the group V element supply layer is formed on the portion of the III-V semiconductor barrier structure after the surface treatment.

9. The method of claim 7, wherein the group V element of the group V element supply layer is chemically bonded to the group III element of the III-V semiconductor barrier structure.

10. The method for forming a power semiconductor element according to claim 7, further comprising:

depositing a dielectric layer on the stack before forming the group V element supply layer;

etching a recess through the group III-V semiconductor barrier structure and exposing a portion of a surface of the group III-V semiconductor barrier structure and a portion of an upper surface of the group III-V semiconductor channel structure, wherein sidewalls and a bottom of the recess are comprised of the portion of the surface of the group III-V semiconductor barrier structure and the portion of the upper surface of the group III-V semiconductor channel structure, respectively; and

performing a surface treatment on the bottom and the side wall of the groove;

wherein the V-group element supply layer is deposited on the bottom and the sidewall of the groove after the surface treatment.