CN114050826A - Analog-to-digital converter gain calibration method, circuit and equipment - Google Patents

Abstract

The invention provides a method, a circuit and equipment for calibrating the gain of an analog-to-digital converter, which utilize an extra digital circuit to measure the actual gain of a residual error amplifier and compensate a digital conversion code in an off-chip calibration mode so as to eliminate amplification errors caused by limited gain of the residual error amplifier and finally improve the conversion precision of the whole analog-to-digital converter. Meanwhile, in the analog-to-digital converter gain calibration method, the signal amplified by the amplifier does not enter the next sub-stage any more and returns to the preposed sample-and-hold circuit, namely the sample-and-hold circuit can sample the input signal and can also sample the signal amplified in the conversion process, so that the multiplexing on hardware is realized, and only one residual error amplifier to be calibrated in the whole system is provided, so that the gain of the amplifier in the whole conversion process can be kept unchanged, meanwhile, the problems of insufficient and incomplete calibration of a plurality of operational amplifiers are avoided, and the design of the gain calibration technology is more facilitated.

Description

Analog-to-digital converter gain calibration method, circuit and equipment

Technical Field

The invention relates to the technical field of electronics, in particular to a method, a circuit and equipment for calibrating gain of an analog-to-digital converter.

Background

Analog-to-digital converter (ADC) is used as an interface between the Analog world and the digital world, and is used to convert Analog signals (such as temperature, pressure, sound, fingerprint or image) generated in the real world into digital signals that can be processed more easily. The pipeline analog-to-digital converter (pipeline adc) is widely used due to its characteristics of high sampling precision, relatively fast sampling rate, and the like.

The main structure of the digital signal processing circuit comprises a sampling and holding circuit (sampleand Hold circuits) at the front end, an N-bit low-precision sub-stage analog-to-digital converter (N-bit SADC), an N-bit digital-to-analog converter (N-bit DAC), a residual error amplifier, a weighted accumulator and partial digital logic, wherein M stages are shared, and each stage of circuit provides a certain number of resolutions. The input analog signal is sampled by a preposed sampling and holding circuit, and the sampling value is maintained until the next sampling signal arrives. The sampled signal is quantized by the first sub-stage ADC to obtain a digital conversion code D with low precision₁The digital conversion code D₁And simultaneously, generating a quantized analog signal through an N-bit digital-to-analog converter, and performing difference on the original signal to obtain a quantized residual signal. The quantized residual signal is then amplified 2 by a residual amplifier^N-1Multiple (1 bit redundancy) is used as the input signal of the next sub-stage, and the digital conversion code D obtained by each stage_iFinally, a digital output code of a conversion result is formed through the weighted accumulator, and the specific numerical value of the digital output code meets the following conditions:

wherein, V_doutFor the output voltage of the entire ADC, V_refIs the reference voltage of the system.

The pipeline architecture analog-to-digital converter disperses the total precision requirement of high-bit-number to each sub-stage analog-to-digital converter, and reduces the requirement of the circuit on the sub-stage system precision, so that the architecture is very efficient in a high-resolution high-speed analog-to-digital converter.

And the performance of an operational amplifier (the operational amplifier for amplifying the residual error is called as a residual error amplifier) as a core module of each pipeline sub-stage is characterized by comprising the pairs of open loop gain, offset voltage, noise, set-up time and the likeThe output of the sub-stage has a large impact and thus affects the overall ADC performance. The gain of the operational amplifier directly limits the accuracy of the ADC, and the settling time of the operational amplifier limits the conversion speed of the ADC. When the open loop gain of the op-amp is too low, the actual amplification G is made less than the theoretical amplification (2 in this design)^N-1) Therefore, a certain deviation exists between the output voltage of the final ADC system and a theoretical value, and the accuracy of the whole system is damaged.

In the first prior art, a multi-stage structure is used to increase the open-loop gain of an operational amplifier, thereby reducing the error of residual amplification. The open loop gain requirement of the residual amplifier is at least 104dB for an accuracy requirement of 17 bits. But the prior art increases the bypass current as a result of the additional bypass introduced by the multi-stage structure. In addition, because the multi-stage operational amplifier has a plurality of poles, the multi-stage operational amplifier needs additional power consumption for ensuring the stability of the system on the premise of not losing the transient characteristic. The technique consumes a large amount of power in addition.

Prior art two, in the first stage of pipeline, add equal amount of disturbance Δ D to the output D1 of DAC₁I.e. D' ═ D₁+RΔD₁Wherein R is a pseudo-random number sequence, and R is { -1, 1}, namely the value of R can be taken from-1 and 1 only. Constructing a relation about a first-stage gain G1 by using the characteristic that the statistical mean value of a pseudo-random number sequence is 0, and adjusting a compensation coefficient 1/G by using a continuous iteration method in the process of not stopping normal analog-to-digital (A/D) conversion₁The summation sequence with respect to R is made 0, thereby achieving cancellation of the amplification error. The gain compensation calibration method of the second prior art does not need to stop normal AD conversion, but needs a large number of sampling points for realizing iteration, so that the conversion result in the previous period of time of each ADC operation is false and invalid. The number of iterations required increases greatly as the accuracy of the ADC increases, requiring 3e6 iterations for a 12-bit ADC and 8e7 iterations for a 14-bit ADC, and it is thought that this method is not suitable for high-accuracy analog conversion. In addition, the compensation calibration scheme of the second technology only aims at the operational amplifier in the first substage of the assembly line, and the rest operational amplifiers are considered to be ideal operational amplifiers and storedThe problem of incomplete calibration.

Disclosure of Invention

To solve the problems in the prior art, embodiments of the present invention provide a method, a circuit, and an apparatus for calibrating a gain of an analog-to-digital converter, which can at least partially solve the problems in the prior art.

In a first aspect, the present invention provides a method for calibrating a gain of an analog-to-digital converter, including:

executing signal input operation, inputting an analog signal to a sample-and-hold circuit, and outputting a sampling signal corresponding to the analog signal by the sample-and-hold circuit;

executing a first operation in a first time frame, and executing a second operation in a second time frame, wherein the first operation comprises inputting the sampling signal into a series circuit of an analog-digital converter and a digital-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word into the digital-analog converter to obtain a second analog output quantity;

executing digital code generation operation, performing difference on the currently output analog output quantity and the sampling signal to obtain a residual signal, amplifying the residual signal by adopting an amplifier, and inputting the residual signal to a rear-end analog-digital converter, wherein the rear-end analog-digital converter outputs a digital output code according to the currently input residual signal;

and executing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with the output signal of the amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

Further, the back-end analog-to-digital converter outputs a digital output code according to a currently input residual signal, including:

performing back-end analog-to-digital conversion on the first analog output quantity in a first time frame to obtain a first digital output code;

and performing back-end analog-to-digital conversion on the second analog output quantity at a second time frame to obtain a second digital output code.

Further, the generating of the signal amplification factor according to the digital output code obtained by each iteration includes:

generating a signal amplification factor expression according to the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation, and the combination of the effective digit of the analog-to-digital converter and the reference voltage;

carrying out weighted accumulation correction on the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation to obtain a plurality of conversion results;

and generating the signal amplification factor according to the conversion result and the signal amplification factor expression.

Further, the analog-to-digital converter gain calibration method further includes:

and obtaining a deflection-free conversion result of the analog signal according to the signal amplification factor and the sampling signal.

Further, the analog-to-digital converter is a low-precision sub-stage analog-to-digital converter, and the first operation includes inputting the sampling signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output, including:

and inputting the sampling signal to a series circuit of the low-precision sub-stage analog-to-digital converter and the digital-to-analog converter to obtain the first analog output quantity.

Further, the series circuit further includes a data selector connected between the analog-to-digital converter and the digital-to-analog converter, the data selector being coupled to a word line of the control word, the control word including an on character and a mask character, the first operation being performed in a first time frame, and the second operation being performed in a second time frame, including:

if the current control word is a conducting character and the current time frame is the first time frame, the data selector outputs the digital signal of the sampling signal processed by the analog-to-digital converter, and then the analog-to-digital converter outputs a first analog output quantity corresponding to the digital signal

If the current control word is a shielding character and the current time frame is the second time frame, the data selector outputs the shielding character, and then the analog-to-digital converter outputs a second analog quantity corresponding to the shielding character.

Further, the iteration number of the iteration operation and the effective digit number of the low-precision sub-stage analog-to-digital converter accord with a set rule.

Further, the number of significant bits of the low-precision substage analog-to-digital converter is equal to the number of significant bits of the digital-to-analog converter.

In a second aspect, the present invention provides an analog-to-digital converter gain calibration circuit, including:

the sampling and holding module is used for receiving an analog signal, and the sampling and holding circuit outputs a sampling signal corresponding to the analog signal;

the data conversion module comprises an analog-to-digital converter and a digital-to-analog converter which are connected in series, wherein the input end of the analog-to-digital converter is coupled with the output end of the sampling holding module, the data conversion module is used for executing a first operation in a first time frame and executing a second operation in a second time frame, the first operation comprises inputting the sampling signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word to the digital-to-analog converter to obtain a second analog output quantity;

the subtracter is used for obtaining a residual signal by making a difference between the sampling signal and the analog output quantity;

the amplifier is used for amplifying the residual signal;

the back-end analog-to-digital converter is used for outputting a digital output code according to the currently input residual signal;

the method comprises the steps of performing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with an output signal of an amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

Further, a control word input line that can transmit the control word;

and the data selector comprises two input ends and an output end, wherein one input end is coupled with the control word input line, the other input end is coupled with the output end of the analog-digital converter, and the output end is coupled with the input end of the digital-analog converter.

In a third aspect, the present invention provides an analog-to-digital converter gain calibration apparatus including the above analog-to-digital converter gain calibration circuit.

The invention has the advantages of

The analog-to-digital converter gain calibration method provided by the embodiment of the invention comprises the steps of inputting an analog signal into a sampling and holding circuit, outputting the analog signal into a sampling and holding circuit by the sampling and holding circuit, inputting the sampling signal into an analog-to-digital converter to obtain a digital conversion code, converting the digital conversion code into a corresponding analog signal by the digital-to-analog converter, carrying out difference on a sampled original signal, amplifying an obtained residual signal by an amplifier, inputting the amplified residual signal into a rear-end analog-to-digital converter after amplification processing by the same amplifier, outputting a digital output code group by the rear-end analog-to-digital converter according to the input signal, replacing the analog signal by the output signal of the amplifier, repeatedly executing the step of inputting the analog signal into the sampling and holding circuit for many times, generating a signal amplification factor according to a plurality of obtained digital output code groups, and further calibrating the amplifier. The gain calibration method can be mainly divided into two parts: the digital conversion code is compensated by using an extra digital circuit to measure the actual gain of the residual error amplifier and by means of off-chip calibration, so that the amplification error caused by the limited gain of the residual error amplifier is eliminated, and the conversion precision of the whole analog-to-digital converter is finally improved. The gain calibration technology can greatly reduce the design pressure of the residual error amplifier, further reduce the power consumption of the whole analog-to-digital converter, and realize higher conversion rate and higher conversion precision.

Meanwhile, in the analog-to-digital converter gain calibration method, the signal amplified by the amplifier does not enter the next sub-stage any more and returns to the preposed sample-and-hold circuit, namely the sample-and-hold circuit can sample the input signal and can also sample the signal amplified in the conversion process, so that the multiplexing on hardware is realized, and only one residual error amplifier to be calibrated in the whole system is provided, so that the gain of the amplifier in the whole conversion process can be kept unchanged, meanwhile, the problems of insufficient and incomplete calibration of a plurality of operational amplifiers are avoided, and the design of the gain calibration technology is more facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts. In the drawings:

fig. 1 is a flowchart illustrating a method for calibrating a gain of an analog-to-digital converter according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a conventional pipeline analog-to-digital converter according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of the operation principle (for second conversion) of the back-end analog-to-digital converter according to an embodiment of the present invention.

Fig. 4 is an operation diagram of a gain measurement of the analog-to-digital converter gain calibration circuit according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of a gain calibration circuit of an analog-to-digital converter according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of the operation principle of the front-end "signal generator" according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

In order to facilitate understanding of the technical solutions provided in the present application, the following briefly describes the research background of the technical solutions in the present application. The pipeline analog-to-digital converter (pipeline adc) is widely used due to its characteristics of high sampling speed, high sampling precision, and the like, and its system block diagram is shown in fig. 2: in the pipeline analog-to-digital converter, a residual error amplifier is used for carrying out secondary sampling conversion on a residual error voltage signal so as to improve the precision of the conversion analog-to-digital converter. However, due to the limited open-loop gain of the residual error amplifier, there is a certain deviation between the digital conversion code outputted from the analog-to-digital converter and the ideal value, and the small deviation destroys the performance of the whole analog-to-digital converter. The invention relates to a gain calibration method based on a circulating pipeline analog-to-digital converter, aiming at measuring the actual gain of a residual error amplifier by using an additional digital circuit and compensating a digital conversion code in an off-chip calibration mode so as to eliminate amplification errors caused by limited gain of the residual error amplifier and finally improve the conversion precision of the whole analog-to-digital converter. The gain calibration technology can greatly reduce the design pressure of the residual error amplifier, further reduce the power consumption of the whole analog-to-digital converter, and realize higher conversion rate and higher conversion precision.

Based on this, as shown in fig. 1, the present invention provides a method for calibrating gain of a circular-flow-based pipelined analog-to-digital converter, comprising:

step S100: executing signal input operation, inputting an analog signal to a sample-and-hold circuit, and outputting a sampling signal corresponding to the analog signal by the sample-and-hold circuit;

step S200: executing a first operation in a first time frame, and executing a second operation in a second time frame, wherein the first operation comprises inputting the sampling signal into a series circuit of an analog-digital converter and a digital-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word into the digital-analog converter to obtain a second analog output quantity;

step S300: executing digital code generation operation, performing difference on the currently output analog output quantity and the sampling signal to obtain a residual signal, amplifying the residual signal by adopting an amplifier, and inputting the residual signal to a rear-end analog-digital converter, wherein the rear-end analog-digital converter outputs a digital output code according to the currently input residual signal;

step S400: and executing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with the output signal of the amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

It is understood that sample and Hold Circuits (S & H) are also known as sample and Hold amplifiers. When analog signals are subjected to A/D conversion, a certain conversion time is required, and the analog signals are basically unchanged in the conversion time, so that the conversion precision can be ensured. A sample-and-hold circuit is a circuit that performs this function. The sampling holding circuit outputs the analog signal as a sampling signal, inputs the sampling signal to an analog-to-digital converter to obtain a digital conversion code, converts the digital conversion code into a corresponding analog signal through a digital-to-analog converter (DAC), the DAC is an N-bit DAC, performs difference on the original sampling signal, amplifies the obtained residual signal through an amplifier, inputs the sampling signal and the digital conversion code to the amplifier, the amplifier is a residual amplifier, the amplifier is processed by the amplifier and then inputs the processed signal to a rear-end DAC to obtain a group of digital output code groups, and returns the residual signal output by the amplifier to a preposed sampling holding circuit, namely the sampling holding circuit can sample the input signal and can also sample the amplified residual signal in the conversion process, and the operations are repeated to obtain a plurality of groups of digital output code groups, and obtaining the signal amplification factor of the amplifier according to the digital output code groups, thereby calibrating the amplifier.

As can be seen from the foregoing description, the core idea of the analog-to-digital converter gain calibration method provided in the embodiments of the present application is to measure the actual gain of the residual amplifier in the system through the existing hardware or use as few additional hardware circuits as possible, and compensate the conversion result by using off-chip post-processing, so as to eliminate the deviation on the output voltage caused by the residual amplification. Based on the above mentioned core idea, the core technology of the present invention, gain calibration technology, can be mainly divided into two parts: the two parts can be arranged to work alternately but can not work simultaneously. The actual gain of the residual error amplifier is measured by an extra digital circuit, and the digital conversion code is compensated in an off-chip calibration mode, so that the amplification error caused by the limited gain of the residual error amplifier is eliminated, and the conversion precision of the whole analog-to-digital converter is finally improved. Meanwhile, in the analog-to-digital converter gain calibration method, the signal amplified by the amplifier does not enter the next sub-stage any more and returns to the preposed sample-and-hold circuit, namely the sample-and-hold circuit can sample the input signal and can also sample the signal amplified in the conversion process, so that the multiplexing on hardware is realized, and only one residual error amplifier to be calibrated in the whole system is provided, so that the gain of the amplifier in the whole conversion process can be kept unchanged, meanwhile, the problems of insufficient and incomplete calibration of a plurality of operational amplifiers are avoided, and the design of the gain calibration technology is more facilitated.

In some embodiments, as shown in fig. 3, the back-end adc outputs a digital output code according to a currently input residual signal, including:

performing back-end analog-to-digital conversion on the first analog output quantity in a first time frame to obtain a first digital output code;

and performing back-end analog-to-digital conversion on the second analog output quantity at a second time frame to obtain a second digital output code.

It can be understood that each time frame for executing the first operation to obtain the first digital output code is a first time frame, and each time frame for executing the second operation to obtain the second digital output code is a second time frame; the first analog output quantity is differed with the original sampling signal, the obtained residual signal is amplified by an amplifier, the sampling signal and the digital conversion code are input into the amplifier, the amplifier is a residual amplifier, and the residual amplifier is processed by the amplifier and then input into a rear-end analog-to-digital converter to obtain a first digital output code; and the second analog output quantity is differed with the original sampling signal, the obtained residual signal is amplified by an amplifier, the sampling signal and the digital conversion code are input into the amplifier, the amplifier is a residual amplifier, and the residual amplifier is processed by the amplifier and then input into a rear-end analog-digital converter to obtain a second digital output code.

In some specific embodiments, as shown in fig. 4, the generating a signal amplification factor according to the digital output code obtained in each iteration includes:

generating a signal amplification factor expression according to the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation, and the combination of the effective digit of the analog-to-digital converter and the reference voltage;

carrying out weighted accumulation correction on the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation to obtain a plurality of conversion results;

and generating the signal amplification factor according to the conversion result and the signal amplification factor expression.

It will be appreciated that the input signal V will be_inKept unchanged by the control word Code⁽¹⁾Controlling the output of the data selector when the output digital code of the back-end A/D converter

Satisfies the following conditions:

maintaining the input signal V during the second transition_inUnchanged, change control word Code⁽²⁾Output digital code of the back-end ADC

Satisfies the following conditions:

subtracting the expressions (2) and (3) to eliminate the input signal V_inObtaining:

in some specific embodiment designs, the significant digit N of the low-precision sub-stage adc is 5, and the cycle number is 4 times. In order to ensure that the amplified residual signal does not exceed the input range of the back-end A/D converter in each conversion process, V is set_in＝0,Code⁽²⁾＝1,Code⁽¹⁾When 0, equation (4) degenerates to:

and the digital output code of the back-end analog-digital converter and each conversion result (2 nd, 3 rd and 4 th times) satisfy the following conditions:

by bringing formula (6) into formula (5):

the formula (7) is a unitary cubic equation of G, and since the approximate range of G is [10,17], the formula (7) has only one solution within the range, and the actual amplification factor G of the residual amplifier can be finally obtained by using Newton iteration or cyclic iteration.

In some specific embodiments, the analog-to-digital converter gain calibration method further includes:

and obtaining a deflection-free conversion result of the analog signal according to the signal amplification factor and the sampling signal.

It will be appreciated that after the actual amplification of the residual amplifier is measured by the gain measurement method, the correction calculation can be done during the off-chip post-processing to obtain a no-deflection conversion result:

although the amplification effect is small because of the limited open-loop gain of the residual amplifier, the effect is very small compared to the conversion deviation before calibration, and there is only a small loss in the accuracy of the whole analog-to-digital converter.

In some specific embodiments, the analog-to-digital converter is a low-precision sub-stage analog-to-digital converter, and the first operation includes inputting the sampling signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output quantity, including:

and inputting the sampling signal to a series circuit of the low-precision sub-stage analog-to-digital converter and the digital-to-analog converter to obtain the first analog output quantity.

It can be understood that, after the sample hold circuit outputs the sampling signal, the sampling signal is input to a low-precision Sub-stage analog-to-digital converter (N-bit Sub-ADC), processed by the low-precision Sub-stage ADC, and then input to the N-bit digital-to-analog converter.

In some specific embodiments, the series circuit further includes a data selector connected between the analog-to-digital converter and the digital-to-analog converter, the data selector being coupled to a word line of the control word, the control word including an on character and a mask character, the performing the first operation in a first time frame and the performing the second operation in a second time frame, including:

if the current control word is a conducting character and the current time frame is the first time frame, the data selector outputs the digital signal of the sampling signal processed by the analog-to-digital converter, and then the analog-to-digital converter outputs a first analog output quantity corresponding to the digital signal

If the current control word is a shielding character and the current time frame is the second time frame, the data selector outputs the shielding character, and then the analog-to-digital converter outputs a second analog quantity corresponding to the shielding character.

It is understood that the control word is used to control the data selector to output or mask the processing signal, assuming that the control word is 0 and 1, when the control word is 0, the output signal of the data selector is controlled by using the input control word, the output result of the low-precision sub-stage analog-to-digital converter of the first conversion is temporarily masked, the sampling signal is used as the input signal of the N-bit digital-to-analog converter, when the control word is 1, the output signal of the data selector is masked by using the input control word, and the output result of the low-precision sub-stage analog-to-digital converter of the first conversion is used as the input signal of the N-bit digital-to-analog converter.

In some specific embodiments, the number of times of repeatedly performing the step of inputting the analog signal to the sample-and-hold circuit and the number of valid bits of the low-precision substage analog-to-digital converter meet a set rule.

It can be understood that the low-precision sub-stage analog-to-digital converter has N significant digits, the N-bit digital-to-analog converter has the same significant digit as the low-precision sub-stage analog-to-digital converter, an output signal of the N-bit digital-to-analog converter replaces an analog signal, the output signal is circularly input to the sample and hold circuit, and the operation is repeatedly performed for multiple times, so that multiple digital output code groups are obtained, wherein the number of times of repeated operation is less than 1 of the significant digit.

As shown in fig. 5, the analog-to-digital converter gain calibration circuit specifically includes the following components:

the sampling and holding module is used for receiving an analog signal, and the sampling and holding circuit outputs a sampling signal corresponding to the analog signal;

the data conversion module comprises an analog-to-digital converter and a digital-to-analog converter which are connected in series, wherein the input end of the analog-to-digital converter is coupled with the output end of the sampling holding module, the data conversion module is used for executing a first operation in a first time frame and executing a second operation in a second time frame, the first operation comprises inputting the sampling signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word to the digital-to-analog converter to obtain a second analog output quantity;

the subtracter is used for obtaining a residual signal by making a difference between the sampling signal and the analog output quantity;

the amplifier is used for amplifying the residual signal;

the back-end analog-to-digital converter is used for outputting a digital output code according to the currently input residual signal;

the method comprises the steps of performing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with an output signal of an amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

It is understood that when analog signals are a/D converted, a certain conversion time is required, during which the analog signals are kept substantially unchanged, so that the conversion accuracy is ensured. The sampling and holding module is used for keeping the analog signal basically unchanged, converting the analog signal into a sampling signal, taking the sampling signal as the input of the data conversion module, the data conversion module inputs the sampling signal into the analog-to-digital converter to obtain a digital conversion code, converting the digital conversion code into the corresponding analog signal through the digital-to-analog converter, the digital-to-analog converter is an N-bit digital-to-analog converter (N-bit DAC), the subtractor subtracts the analog signal from the original sampling signal to obtain a residual signal, the residual signal is processed by the amplifier and then input into the rear-end analog-to-digital converter to obtain a group of digital output code groups, and the residual signal output by the amplifier is returned to be input into the preposed sampling and holding circuit, namely the sampling and holding circuit can sample the input signal and can also sample the amplified residual signal in the conversion process and repeat the operations, and obtaining a plurality of groups of digital output code groups, and obtaining the signal amplification factor of the amplifier according to the digital output code groups so as to calibrate the amplifier.

As can be seen from the above description, the analog-to-digital converter gain calibration circuit provided in the embodiment of the present application utilizes an additional digital circuit to measure the actual gain of the residual error amplifier and compensates the digital conversion code by means of off-chip calibration, so as to eliminate the amplification error caused by the limited gain of the residual error amplifier, and finally improve the conversion accuracy of the whole analog-to-digital converter. Meanwhile, in the analog-to-digital converter gain calibration method, the signal amplified by the amplifier does not enter the next sub-stage any more and returns to the preposed sample-and-hold circuit, namely the sample-and-hold circuit can sample the input signal and can also sample the signal amplified in the conversion process, so that the multiplexing on hardware is realized, and only one residual error amplifier to be calibrated in the whole system is provided, so that the gain of the amplifier in the whole conversion process can be kept unchanged, meanwhile, the problems of insufficient and incomplete calibration of a plurality of operational amplifiers are avoided, and the design of the gain calibration technology is more facilitated.

In some specific embodiments, the data conversion module further includes:

a control word input line that can transmit the control word;

and the data selector comprises two input ends and an output end, wherein one input end is coupled with the control word input line, the other input end is coupled with the output end of the analog-digital converter, and the output end is coupled with the input end of the digital-analog converter.

It will be appreciated that the gain measurement circuit splits the entire analog-to-digital converter system in the time domain into two parts, the first conversion being considered as the front-end and used as the "signal generator", as shown in fig. 6, to generate a specific output signal, and the second, third and fourth conversions being considered as the back-end and used to quantize the specific output signal generated by the front-end.

The data selector comprises two input ends and an output end, the two input ends are respectively coupled with the control word input circuit and the output end of the low-precision substage analog-to-digital converter, and the output end is coupled with the input end of the digital-to-analog converter.

The front end inserts a data selector (MUX) in the low-precision sub-level analog-to-digital converter and the N-bit digital-to-analog converter, an output signal of the data selector is controlled by an input control word (Code) to serve as the input of the N-bit digital-to-analog converter, and the output result of the low-precision sub-level analog-to-digital converter which is converted for the first time is temporarily shielded, so that the function of a 'signal generator' is realized. In order to ensure normal quantization operation, a data selector is needed at the rear end, so that an input signal of the N-bit digital-to-analog converter comes from a digital conversion code of the low-precision sub-level analog-to-digital converter, namely when the data selector is shielded by a control word, a processing signal is input to the N-bit digital-to-analog converter, and the N-bit digital-to-analog converter outputs a first digital conversion code; when the control word masks the processing signal, the control word is used as the output of the data selector and is input to the N-bit digital-to-analog converter, and the N-bit digital-to-analog converter outputs a second digital conversion code.

The present application provides an embodiment of an analog-to-digital converter gain calibration apparatus for performing all or part of the method for calibrating the gain of an analog-to-digital converter, the analog-to-digital converter gain calibration apparatus specifically includes the analog-to-digital converter gain calibration circuit as described above.

The analog-to-digital converter gain calibration method, the circuit and the equipment provided by the embodiment of the invention provide a calibration idea of utilizing an actual amplification factor G instead of a theoretical amplification factor, realize a foreground test scheme of the actual amplification factor G through the existing circuit structure according to the idea, and in order to better accord with the scheme, improve the structure of the traditional pipelined analog-to-digital converter, change a chain structure into a circular structure, realize hardware multiplexing, save the area, ensure that the actual amplification factor G of a residual error amplifier is one and only one in the whole conversion process, avoid the problem of incomplete calibration, and essentially eliminate a gain error in the conversion process. The gain calibration method can be mainly divided into two parts: the digital conversion code is compensated by using an extra digital circuit to measure the actual gain of the residual error amplifier and by means of off-chip calibration, so that the amplification error caused by the limited gain of the residual error amplifier is eliminated, and the conversion precision of the whole analog-to-digital converter is finally improved. The gain calibration technology can greatly reduce the design pressure of the residual error amplifier, further reduce the power consumption of the whole analog-to-digital converter, and realize higher conversion rate and higher conversion precision.

The foreground calibration scheme provided by the invention can greatly reduce the open loop gain requirement of the system on the residual error amplifier, is greatly beneficial to the design of a high-precision analog-to-digital converter, reduces the open loop gain requirement of the residual error amplifier from 104dB to 50dB in terms of the precision requirement of 17 bits,

compared with the traditional calibration scheme, the method does not need to use a large number of extra sampling points to solve the problems of convergence calculation and the like of the amplification factor G, and the scheme can greatly utilize the existing hardware and can realize the measurement of the actual amplification factor without a large number of extra hardware circuits. And with regard to the numerical calculation of equation (7), only 3 newton iterations or 7 simple loop iterations are required to obtain an accurate solution meeting the requirement without excessive iterations.

Meanwhile, in the analog-to-digital converter gain calibration method, the signal amplified by the amplifier does not enter the next sub-stage any more and returns to the preposed sample-and-hold circuit, namely the sample-and-hold circuit can sample the input signal and can also sample the signal amplified in the conversion process, so that the multiplexing on hardware is realized, and only one residual error amplifier to be calibrated in the whole system is provided, so that the gain of the amplifier in the whole conversion process can be kept unchanged, meanwhile, the problems of insufficient and incomplete calibration of a plurality of operational amplifiers are avoided, and the design of the gain calibration technology is more facilitated.

In the description herein, reference to the description of the terms "one embodiment," "a particular embodiment," "some embodiments," "for example," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (11)

1. A method for calibrating gain of an analog-to-digital converter, comprising:

executing signal input operation, inputting an analog signal to a sample-and-hold circuit, and outputting a sampling signal corresponding to the analog signal by the sample-and-hold circuit;

executing a first operation in a first time frame, and executing a second operation in a second time frame, wherein the first operation comprises inputting the sampling signal into a series circuit of an analog-digital converter and a digital-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word into the digital-analog converter to obtain a second analog output quantity;

executing digital code generation operation, performing difference on the currently output analog output quantity and the sampling signal to obtain a residual signal, amplifying the residual signal by adopting an amplifier, and inputting the residual signal to a rear-end analog-digital converter, wherein the rear-end analog-digital converter outputs a digital output code according to the currently input residual signal;

and executing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with the output signal of the amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

2. The method of calibrating gain of an analog-to-digital converter according to claim 1, wherein the back-end analog-to-digital converter outputs a digital output code according to a currently input residual signal, comprising:

performing back-end analog-to-digital conversion on the first analog output quantity in a first time frame to obtain a first digital output code;

and performing back-end analog-to-digital conversion on the second analog output quantity at a second time frame to obtain a second digital output code.

3. The method of calibrating gain of an analog-to-digital converter according to claim 1, wherein said generating signal amplification from the digital output code obtained from each iteration comprises:

generating a signal amplification factor expression according to the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation, and the combination of the effective digit of the analog-to-digital converter and the reference voltage;

carrying out weighted accumulation correction on the first digital output code and the second digital output code which are obtained for the first time and the first digital output code which is obtained by each iteration operation to obtain a plurality of conversion results;

and generating the signal amplification factor according to the conversion result and the signal amplification factor expression.

4. The analog-to-digital converter gain calibration method of claim 1, further comprising:

and obtaining a deflection-free conversion result of the analog signal according to the signal amplification factor and the sampling signal.

5. The method of calibrating gain of an analog-to-digital converter according to claim 1, wherein the analog-to-digital converter is a low-precision substage analog-to-digital converter, and the first operation comprises inputting the sampled signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output, comprising:

and inputting the sampling signal to a series circuit of the low-precision sub-stage analog-to-digital converter and the digital-to-analog converter to obtain the first analog output quantity.

6. The method of calibrating gain of an analog-to-digital converter according to claim 1, wherein the series circuit further comprises a data selector connected between the analog-to-digital converter and the digital-to-analog converter, the data selector being coupled to a word line of the control word, the control word comprising a turn-on word and a mask word, the first operation being performed in a first time frame and the second operation being performed in a second time frame, the method comprising:

if the current control word is a conducting character and the current time frame is the first time frame, the data selector outputs the digital signal of the sampling signal processed by the analog-to-digital converter, and then the analog-to-digital converter outputs a first analog output quantity corresponding to the digital signal

If the current control word is a shielding character and the current time frame is the second time frame, the data selector outputs the shielding character, and then the analog-to-digital converter outputs a second analog quantity corresponding to the shielding character.

7. The method of claim 5, wherein the number of iterations of the iterative operation and the number of significant bits of the low-precision substage analog-to-digital converter meet a predetermined rule.

8. The method of calibrating gain of an analog-to-digital converter according to claim 7, wherein the number of significant bits of the low-precision substage analog-to-digital converter is equal to the number of significant bits of the digital-to-analog converter.

9. An analog-to-digital converter gain calibration circuit, comprising:

the sampling and holding module is used for receiving an analog signal, and the sampling and holding circuit outputs a sampling signal corresponding to the analog signal;

the data conversion module comprises an analog-to-digital converter and a digital-to-analog converter which are connected in series, wherein the input end of the analog-to-digital converter is coupled with the output end of the sampling holding module, the data conversion module is used for executing a first operation in a first time frame and executing a second operation in a second time frame, the first operation comprises inputting the sampling signal to a series circuit of the analog-to-digital converter and the digital-to-analog converter to obtain a first analog output quantity, and the second operation comprises inputting a control word to the digital-to-analog converter to obtain a second analog output quantity;

the subtracter is used for obtaining a residual signal by making a difference between the sampling signal and the analog output quantity;

the amplifier is used for amplifying the residual signal;

the back-end analog-to-digital converter is used for outputting a digital output code according to the currently input residual signal;

the method comprises the steps of performing at least one iteration operation, wherein the iteration operation comprises replacing the analog signal with an output signal of an amplifier, repeating the signal input operation, the first operation and the digital code generation operation, generating a signal amplification factor according to the digital output code obtained by each iteration, and further calibrating the amplifier.

10. The analog-to-digital converter gain calibration circuit of claim 9, wherein the data conversion module further comprises:

a control word input line that can transmit the control word;

and the data selector comprises two input ends and an output end, wherein one input end is coupled with the control word input line, the other input end is coupled with the output end of the analog-digital converter, and the output end is coupled with the input end of the digital-analog converter.

11. An analog-to-digital converter gain calibration apparatus comprising an analog-to-digital converter gain calibration circuit as claimed in claim 9 or 10.

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