CN118018021A - Foreground calibration system of pipelined ADC (analog-to-digital converter) and implementation method - Google Patents
Foreground calibration system of pipelined ADC (analog-to-digital converter) and implementation method Download PDFInfo
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Abstract
The invention discloses a foreground calibration system and an implementation method of a pipeline ADC (analog-to-digital converter), and belongs to the field of calibration of pipeline ADCs. The system comprises a pipeline ADC circuit, a switch control module, a state machine module and a calibration core module, wherein the pipeline ADC circuit receives a switch code and a thermometer code of the switch control module and sends an output code word to the calibration core module; the state machine module generates a state control signal and inputs the state control signal to the switch control module; the switch control module receives the state control signal and decodes the state control signal into a switch code and a thermometer code respectively; the calibration core module receives the original output code words from the pipeline ADC circuit to carry out code word synthesis, obtains error parameters during foreground calibration, compensates errors by utilizing the error parameters in the normal conversion process, and obtains the calibrated digital output code. The calibration system has simple structure and high efficiency; complexity is optimized, hardware cost is reduced, and the method has the characteristics of high efficiency, rapidness and accuracy.
Description
Technical Field
The invention belongs to the field of calibration of pipeline ADC (analog-to-digital converter), and particularly relates to a foreground calibration system and an implementation method of a pipeline ADC.
Background
Analog-to-Digital Converter (ADC) is an important ring in modern electronic systems as one of the key technologies for the connection of the Analog world to the digital world system. For applications such as software radio, digital image processing, etc., there is a high requirement for the speed and accuracy of the analog-to-digital converter. The pipelined analog-to-digital converter has stronger advantages in speed, precision, power consumption and area than analog-to-digital converters of other structures, so the high-speed high-precision pipelined analog-to-digital converter is one of the current ADC research hotspots. However, the calibration research on ADC error is an important part of the current research pipeline ADC by considering the influence of various error sources such as comparator offset, interstage gain error, DAC error and the like on the performance of ADC effective bit number, linearity and the like.
At present, the redundancy correction algorithm for the offset of the comparator and various calibration techniques for the inter-stage gain are relatively mature, while for the calibration of DAC errors, the existing methods are deficient, and the existing calibration methods based on the statistical principle are not suitable for high-bit quantized DAC in structure. In addition, although the capacitive mismatch calibration technology based on DEM (DYNAMIC ELEMENT MATCHING ) can effectively inhibit harmonic distortion generated by mismatch errors, the implementation complexity of the completely random DEM technology is increased sharply along with the increase of digits, and the conversion time of dynamic element matching is longer. Other calibration methods can realize pure background calibration by using pseudo-random injection to calibrate capacitance mismatch, but extra circuits are needed to be introduced, and pseudo-random codes increase white noise of the circuits and increase the complexity of calibration.
Disclosure of Invention
Aiming at the defects of the prior art on DAC error calibration, the invention provides a foreground calibration system and an implementation method of a pipelined ADC, and the specific technical scheme comprises the following steps:
in a first aspect of the present invention, the present invention provides a foreground calibration system for a pipelined ADC, comprising: the system comprises a pipeline ADC circuit, a state machine module, a switch control module and a calibration core module;
The pipeline ADC circuit is used for receiving the switch code and the thermometer code of the switch control module and sending an output code word to the calibration core module;
the state machine module is used for generating a state control signal and inputting the state control signal to the switch control module;
The switch control module is used for receiving a state control signal generated by the state machine module and respectively decoding the state control signal into a switch code and a thermometer code, wherein the switch code is used for controlling the threshold voltage of the input comparator, and the thermometer code is used for controlling the output digital code corresponding to the threshold voltage;
the calibration core module is used for receiving an original output code word from the pipeline ADC circuit to carry out code word synthesis, obtaining error parameters during foreground calibration, compensating errors by utilizing the error parameters in a normal conversion process, and finally obtaining a calibrated digital output code.
Further, the pipelined ADC circuit comprises a multi-stage pipelined ADC and a flash ADC, wherein the multi-stage pipelined ADC and the flash ADC are sequentially connected in series, and the flash ADC is connected in series at the tail end.
Further, each stage of pipelined ADC in the multi-stage pipelined ADC includes: the device comprises a sub ADC unit and an MDAC unit, wherein the sub ADC unit is connected with the MDAC unit; the MDAC unit includes a sub-DAC unit, an adder, and a gain amplifier.
Further, the sub ADC unit quantizes the current input signal, and the quantized result is output as an integral ADC digital code; the sub DAC unit converts the quantized result of the sub ADC unit into corresponding analog signals; the adder performs subtraction on the input signal and the analog signal to obtain a residual signal; the gain amplifier amplifies the residual signal to be used as a residual signal and outputs the residual signal to a next-stage pipelined ADC (analog-to-digital converter) as an input signal of the next stage to be continuously quantized; the input signal of the first stage of the pipelined ADC is the threshold voltage of the input comparator, and the residual signal of the last stage of pipelined ADC is directly output to the flash ADC.
Further, the calibration core module comprises a codeword synthesis unit, an error register, a multiplexer and at least two adders; the input end of the multiplexer is connected with the code word synthesizing unit, the error register and one adder; the output end of the multiplexer is connected with another adder; and the codeword synthesis unit, one of the adders and the error register are sequentially connected.
Further, the codeword synthesis unit performs codeword synthesis on the output codeword of the pipeline ADC circuit, where the one adder superimposes the synthesized codeword, and obtains an error parameter during foreground calibration; the error register stores the error parameters; the multiplexer selects the error parameters; and the additional adder is used for superposing the selected error parameter and the digital code to obtain a calibrated digital output code.
In a second aspect of the present invention, the present invention also proposes, for the first aspect, a method for implementing a foreground calibration system of a pipelined ADC, the method comprising the steps of:
Step 1: the threshold voltage of the comparator is controlled by a switch code of a switch control module, a thermometer code of the switch control module controls a digital code of a subinterval at the left side of an output voltage, and the total digital output is finally obtained through a calibration core module;
Step 2: the threshold voltage of the comparator which is controlled and input by the switch code of the switch control module is kept unchanged, the thermometer code of the switch control module controls the digital code of the subinterval on the right side of the output voltage, and the total digital output is finally obtained through the calibration core module;
Step 3: subtracting the total digital output obtained in the step 1 and the step 2 to obtain a calibration error parameter, and registering the calibration error parameter;
Step 4: changing the value of the threshold voltage of the comparator in the step 1, repeating the operations in the steps 1 to 3 for a plurality of times, and finally obtaining error parameters corresponding to the threshold voltage points of the comparator for a plurality of times;
Step 5: when the ADC works normally, in the calibration core module, according to the section where the input signal is located, the original digital output D out_raw is compensated correspondingly through the adder to obtain a calibrated digital output code D out_cal.
Furthermore, a pipelined ADC of the pipelined ADC circuit employs two's complement.
The beneficial effects of the invention include:
The foreground calibration system and the implementation method of the pipelined ADC can effectively calibrate the influence caused by DAC errors, and simultaneously, the calibration method can also calibrate the nonlinear problem of the pipelined ADC caused by interstage gain, thereby effectively improving the precision of the pipelined ADC. In addition, the calibration system only uses a plurality of simple circuits such as a multiplexer, an adder and the like to complete the calibration, the hardware complexity is low, and the calibration effect is obvious.
Drawings
FIG. 1 is a block diagram of a foreground calibration system for pipelined ADCs employed in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a pipeline ADC circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a transmission curve of a first-stage digital-to-analog converter (MDAC) according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of error compensation of a calibration core module employed in an embodiment of the present invention;
FIG. 5 shows graphs of the input and output transmission of DAC errors before and after calibration, (a) the input and output transmission of DAC errors before calibration, and (b) the input and output transmission of DAC errors after calibration;
FIG. 6 is a comparison chart of FFT analysis before and after calibration, wherein (a) is the result of FFT analysis before DAC error calibration and (b) is the result of FFT analysis after calibration;
FIG. 7 is a flow chart of a calibration method of the present invention employed in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention will now be further described with reference to the accompanying drawings. The embodiment provides a foreground calibration system of a pipelined ADC, as shown in fig. 1, including a pipelined ADC circuit, a switch control module, a state machine module, and a calibration core module, where:
The pipeline ADC circuit is used for receiving the switch code and the thermometer code of the switch control module and sending an output code word to the calibration core module;
the state machine module is used for generating a state control signal and inputting the state control signal to the switch control module;
The switch control module is used for receiving a state control signal generated by the state machine module and respectively decoding the state control signal into a switch code and a thermometer code, wherein the switch code is used for controlling the threshold voltage of the input comparator, and the thermometer code is used for controlling the output digital code corresponding to the threshold voltage;
the calibration core module is used for receiving an original output code word from the pipeline ADC circuit to carry out code word synthesis, obtaining error parameters during foreground calibration, compensating errors by utilizing the error parameters in a normal conversion process, and finally obtaining a calibrated digital output code.
In this embodiment, the foreground calibration system based on the pipelined ADC may calibrate the error of the pipelined ADC of any multiple stages, where the pipelined ADC circuit includes a multi-stage pipelined ADC and a flash ADC, where the multi-stage pipelined ADC and the flash ADC are sequentially connected in series, and the flash ADC is connected in series at the tail end.
The sub ADC unit quantizes the current input signal, and the quantized result is output as an integral ADC digital code; the sub DAC unit converts the quantized result of the sub ADC unit into corresponding analog signals; the adder performs subtraction on the input signal and the analog signal to obtain a residual signal; the gain amplifier amplifies the residual signal to be used as a residual signal and outputs the residual signal to a next-stage pipelined ADC (analog-to-digital converter) as an input signal of the next stage to be continuously quantized; the input signal of the first stage of the pipelined ADC is the threshold voltage of the input comparator, and the residual signal of the last stage of pipelined ADC is directly output to the flash ADC.
For convenience of description, the pipeline ADC according to the present invention adopts a 6-stage pipeline structure, as shown in fig. 2, where the first 5 stages are 3-bit pipeline stages of each stage, and the last stage is a 4-bit flash ADC. In the first 5 pipelined sub-stages, each stage is comprised of a sub-ADC unit and an MDAC unit, where the MDAC unit includes a sub-DAC unit, a summer, and a gain amplifier.
Taking a first stage as an example to illustrate the operation mode of each stage of pipeline stage, the sub-ADC unit quantizes an input signal V in to obtain a digital code D 1 for output, meanwhile, the digital code enters the sub-DAC unit and is converted into an analog signal V dac1, the input signals V in and V dac1 enter the adder for subtraction, the obtained result is amplified by the gain amplifier to obtain a residual error V res1 of the first stage, the residual error signal is taken as an input signal of the next stage and is quantized by the sub-ADC unit of the next stage to obtain a digital code D2, and so on, the digital code D 1～D6 is finally obtained, all the digital codes are input into the front digital calibration module, and finally, the digital code output of 14 bits is obtained.
As shown in fig. 3, the transmission curve of the first-stage MDAC and the digital codes corresponding to the subintervals are plotted, wherein the upper half of fig. 3 is an ideal transmission curve, and the lower half of fig. 3 is a transmission curve after adding the DAC error, and it is known by comparison that the transmission curve of the MDAC is shifted up and down under the influence of the DAC error.
The ordinate V res1 of the MDAC transmission curve shown in fig. 3 is the residual signal in fig. 2, and its value is:
Vres1＝G1(Vin-Vdac1) (1)
Wherein: g 1 is the amplification factor of the first stage gain amplifier, V in is the input voltage, V dac1 is the output of the sub-DAC cell, and its value is:
Wherein: d 1 is a digital code output by a sub ADC unit of the first stage pipeline stage, and the decimal equivalent value is-4 to 4; v Ref is the reference voltage of the pipelined ADC, k1 is the first stage output bit number, here 3.
In an embodiment of the present invention, the state machine module generates a set of state control signals. The state machine module may be constituted by a state machine controlled by a clock signal and a reset signal, and during calibration, a certain idle time needs to be left after each state in order to leave sufficient computation time for the subsequent calibration core module. Here 30 clock cycles are envisaged. Thus, at calibration, the calibration core module samples the input 24-bit source code once every 30 cycles for updating of the error value.
In the embodiment of the invention, the switch control module comprises a decoder 1 and a decoder 2, wherein the decoder 1 can generate a switch code, and the decoder 2 can generate a thermometer code.
The switch control module receives the state control signals of the state machine module, decodes the state control signals into a group of selection switch codes and a group of thermometer codes through the decoder, and both the two groups of signals are connected with the pipeline ADC circuit. The switch code is controlled to be input into the threshold voltage V j of the comparator, the thermometer code forcedly controls the sub-ADC to output a codeword as a digital code of a subinterval on the left side of the threshold voltage, the original digital code D 1～D6 is obtained through the work of the pipeline ADC circuit shown in fig. 1, and the digital code D 1～D6 enters the calibration core module to synthesize the codeword to obtain the total digital output D out1,j. Then, the value of the threshold voltage V j of the input comparator is kept unchanged, and the thermometer code force control sub-ADC outputs a codeword as a digital code of a subinterval on the right side of the threshold voltage, thereby obtaining a total digital output D out2,j. The deviation degree of digital output can be determined through the digital codes of the subintervals at the left side and the right side, so that the compensation correction of the digital codes is realized.
In the embodiment of the invention, the calibration core module comprises a codeword synthesis unit, an error register, a multiplexer and at least two adders; the input end of the multiplexer is connected with the code word synthesizing unit, the error register and one adder; the output end of the multiplexer is connected with another adder; and the codeword synthesis unit, one of the adders and the error register are sequentially connected.
The code word synthesis unit performs code word synthesis on the output code word of the pipeline ADC circuit, wherein one adder is used for superposing the synthesized code word, and error parameters are obtained during foreground calibration; the error register stores the error parameters; the multiplexer selects the error parameters; the additional adders superimpose the selected error parameters with the digital codes to obtain calibrated digital output codes, wherein the additional adders can be one or a plurality of adders.
As shown in fig. 4, when the calibration core module of the present invention performs error compensation, the specific principle is implemented by a simple multiplexer, where a plurality of adders are connected to the multiplexer, and S 1～S8 in fig. 4 is the calibration error parameter, and the multiplexer uses the digital code output by the sub-ADC as a determination condition.
As shown in fig. 5, fig. 5 (a) is a pipeline ADC input-output curve after adding a DAC error, when a comparator threshold voltage V j＝Vx＝VY is input, the value of the calibration error parameter S j corresponding to the threshold voltage point, j=1, 2, …, N, represents the number of input threshold voltages, that is, the number of threshold voltages corresponding to the break points of the transmission curve in fig. 5, taking j=1 as an example, specifically:
Where Vx is quantized to the left interval and V Y is quantized to the right interval, in this way, changing the value of the input threshold voltage V j, the corresponding calibration error parameters at the remaining threshold voltage points can be calculated.
In the embodiment of the present invention, the calibration error parameter S 1～S8 obtained above is registered in the error register of the calibration core module, and when the pipeline ADC works normally, error compensation is performed by the multiplexer and the adder, so as to obtain the calibrated output codeword dout_cal.
The fifth sub-section in fig. 5 (a), i.e. the middle sub-section, is used as a reference to calibrate each section in turn, the error compensation value of the fifth sub-section is always 0, and the other sub-section compensation modes are as follows:
After the calibration in the above way, the input-output curve of the pipelined ADC is shown in fig. 5 (b), and the linearity of the whole pipelined ADC is greatly improved.
As shown in fig. 6 (a), before calibration, the digital output dout_raw of the entire pipelined ADC is subjected to FFT analysis, and as a result, it can be seen that the effective bit number of the ADC is only 7.33 bits, and as a result, as shown in fig. 6 (b), the calibrated output codeword dout_cal is subjected to FFT analysis, and as a result, it can be seen that the effective bit number ENOB reaches 13.60 bits. As can be seen from a comparison of fig. 6 (a) and (b), the signal-to-noise distortion ratio SNDR of the pipelined ADC increases from 45.91dB to 83.64dB, and the spurious-free dynamic range SFDR increases from 51.74dB to 91.49dB.
FIG. 7 is a flow chart of a calibration method of the present invention, as shown in FIG. 7, as employed by an embodiment of the present invention, the method comprising:
Step 1: the threshold voltage V j of the comparator is controlled and input by the switch code of the switch control module, the thermometer code of the switch control module controls the digital code of the subinterval at the left side of the output voltage, and the total digital output D out1,j is finally obtained through the calibration core module;
Step 2: the threshold voltage V j of the comparator which is controlled and input by the switch code of the switch control module is kept unchanged, the thermometer code of the switch control module controls the digital code of the subinterval on the right side of the output voltage, and the total digital output D out2,j is finally obtained through the calibration core module;
Step 3: d out1,j is subtracted from D out2,j to obtain a calibration error parameter S j, and the calibration error parameter is registered;
step 4: changing the value of the threshold voltage V j of the comparator in the step 1, repeating the operations from the step 1 to the step 3 for a plurality of times, and finally obtaining error parameters corresponding to the threshold voltage points of the comparator for a plurality of times;
Step 5: when the ADC works normally, in the calibration core module, according to the section where the input signal is located, the original digital output D out_raw is compensated correspondingly through the adder to obtain a calibrated digital output code D out_cal.
In summary, the DAC error in the pipelined ADC can be effectively calibrated, the defects of complex traditional algorithm and low precision in the high-speed high-precision pipelined ADC are overcome, the calibration can be realized by only simple logic operation, the calibration effect is obvious, and the performance of the pipelined ADC is effectively improved.
The above description is only illustrative of the technical principles of the present invention, and other skilled in the art can make various corresponding changes according to the method of the present invention, which fall within the scope of the claims of the method of the present invention.
Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program to instruct related hardware, the program may be stored in a computer readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, etc.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The foreground calibration system of the pipelined ADC is characterized by comprising a pipelined ADC circuit, a switch control module, a state machine module and a calibration core module, wherein:
The pipeline ADC circuit is used for receiving the switch code and the thermometer code of the switch control module and sending an output code word to the calibration core module;
the state machine module is used for generating a state control signal and inputting the state control signal to the switch control module;
The switch control module is used for receiving a state control signal generated by the state machine module and respectively decoding the state control signal into a switch code and a thermometer code, wherein the switch code is used for controlling the threshold voltage of the input comparator, and the thermometer code is used for controlling the output digital code corresponding to the threshold voltage;
the calibration core module is used for receiving an original output code word from the pipeline ADC circuit to carry out code word synthesis, obtaining error parameters during foreground calibration, compensating errors by utilizing the error parameters in a normal conversion process, and finally obtaining a calibrated digital output code.
2. The foreground calibration system of a pipelined ADC of claim 1, wherein said pipelined ADC circuit comprises a multi-stage pipelined ADC and a flash ADC, said multi-stage pipelined ADC and flash ADC being serially connected in sequence, and said flash ADC being serially connected at an end.
3. The foreground calibration system of a pipelined ADC of claim 2, wherein each of said multi-stage pipelined ADCs comprises: the device comprises a sub ADC unit and an MDAC unit, wherein the sub ADC unit is connected with the MDAC unit; the MDAC unit includes a sub-DAC unit, an adder, and a gain amplifier.
4. A foreground calibration system of a pipelined ADC according to claim 3, wherein said sub-ADC unit quantizes the current input signal, the quantized result being output as an overall ADC digital code; the sub DAC unit converts the quantized result of the sub ADC unit into corresponding analog signals; the adder performs subtraction on the input signal and the analog signal to obtain a residual signal; the gain amplifier amplifies the residual signal to be used as a residual signal and outputs the residual signal to a next-stage pipelined ADC (analog-to-digital converter) as an input signal of the next stage to be continuously quantized; the input signal of the first stage of the pipelined ADC is the threshold voltage of the input comparator, and the residual signal of the last stage of pipelined ADC is directly output to the flash ADC.
5. The foreground calibration system of a pipelined ADC of claim 1, wherein said calibration core module comprises a codeword synthesis unit, an error register, a multiplexer, and at least two adders; the input end of the multiplexer is connected with the code word synthesizing unit, the error register and one adder; the output end of the multiplexer is connected with another adder; and the codeword synthesis unit, one of the adders and the error register are sequentially connected.
6. The foreground calibration system of a pipelined ADC of claim 5, wherein said codeword synthesis unit performs codeword synthesis on output codewords of said pipelined ADC circuit, and wherein said one adder superimposes the synthesized codewords to obtain error parameters during foreground calibration; the error register stores the error parameters; the multiplexer selects the error parameters; and the additional adder is used for superposing the selected error parameter and the digital code to obtain a calibrated digital output code.
7. A method of implementing a foreground calibration system employing a pipelined ADC as recited in any one of claims 1-6, comprising the steps of:
Step 1: the threshold voltage of the comparator is controlled by a switch code of a switch control module, a thermometer code of the switch control module controls a digital code of a subinterval at the left side of an output voltage, and the total digital output is finally obtained through a calibration core module;
Step 2: the threshold voltage of the comparator which is controlled and input by the switch code of the switch control module is kept unchanged, the thermometer code of the switch control module controls the digital code of the subinterval on the right side of the output voltage, and the total digital output is finally obtained through the calibration core module;
Step 3: subtracting the total digital output obtained in the step 1 and the step 2 to obtain a calibration error parameter, and registering the calibration error parameter;
Step 4: changing the value of the threshold voltage of the comparator in the step 1, repeating the operations in the steps 1 to 3 for a plurality of times, and finally obtaining error parameters corresponding to the threshold voltage points of the comparator for a plurality of times;
step 5: when the ADC works normally, in the calibration core module, according to the section where the input signal is located, the original digital output D outraw is compensated correspondingly through the adder to obtain a calibrated digital output code D out_cal.
8. The method of claim 7, wherein the pipelined ADC of the pipelined ADC circuit employs two's complement codes.
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