CN114035710B - External trigger touch sensing array and preparation method thereof - Google Patents
External trigger touch sensing array and preparation method thereof Download PDFInfo
- Publication number
- CN114035710B CN114035710B CN202111230664.3A CN202111230664A CN114035710B CN 114035710 B CN114035710 B CN 114035710B CN 202111230664 A CN202111230664 A CN 202111230664A CN 114035710 B CN114035710 B CN 114035710B
- Authority
- CN
- China
- Prior art keywords
- electrode
- thin film
- film transistor
- double
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 93
- 239000010408 film Substances 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 238000002161 passivation Methods 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000004642 Polyimide Substances 0.000 claims description 27
- 229920001721 polyimide Polymers 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 20
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 18
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 18
- -1 polydimethylsiloxane Polymers 0.000 claims description 18
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 18
- 230000001960 triggered effect Effects 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 11
- 150000004706 metal oxides Chemical class 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 10
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 10
- 230000009977 dual effect Effects 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 229920001940 conductive polymer Polymers 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 239000011112 polyethylene naphthalate Substances 0.000 claims description 6
- 239000004814 polyurethane Substances 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000002082 metal nanoparticle Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 239000002105 nanoparticle Substances 0.000 claims description 5
- 239000002070 nanowire Substances 0.000 claims description 5
- 229920002635 polyurethane Polymers 0.000 claims description 5
- 239000002041 carbon nanotube Substances 0.000 claims description 4
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- AXKZIDYFAMKWSA-UHFFFAOYSA-N 1,6-dioxacyclododecane-7,12-dione Chemical compound O=C1CCCCC(=O)OCCCCO1 AXKZIDYFAMKWSA-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000000741 silica gel Substances 0.000 claims description 3
- 229910002027 silica gel Inorganic materials 0.000 claims description 3
- KKEYFWRCBNTPAC-UHFFFAOYSA-L terephthalate(2-) Chemical compound [O-]C(=O)C1=CC=C(C([O-])=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-L 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 92
- 238000000034 method Methods 0.000 description 33
- 238000007650 screen-printing Methods 0.000 description 27
- 238000001755 magnetron sputter deposition Methods 0.000 description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 16
- 238000001259 photo etching Methods 0.000 description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 14
- 235000012239 silicon dioxide Nutrition 0.000 description 14
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 12
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000007738 vacuum evaporation Methods 0.000 description 9
- 238000007641 inkjet printing Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 8
- 239000011787 zinc oxide Substances 0.000 description 8
- 238000001035 drying Methods 0.000 description 7
- 238000005286 illumination Methods 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 6
- 239000004372 Polyvinyl alcohol Substances 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 6
- 239000008367 deionised water Substances 0.000 description 6
- 229910021641 deionized water Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229920002451 polyvinyl alcohol Polymers 0.000 description 6
- 229920000036 polyvinylpyrrolidone Polymers 0.000 description 6
- 239000001267 polyvinylpyrrolidone Substances 0.000 description 6
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 238000007646 gravure printing Methods 0.000 description 5
- 238000004506 ultrasonic cleaning Methods 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 238000010345 tape casting Methods 0.000 description 4
- 239000004800 polyvinyl chloride Substances 0.000 description 3
- FMZQNTNMBORAJM-UHFFFAOYSA-N tri(propan-2-yl)-[2-[13-[2-tri(propan-2-yl)silylethynyl]pentacen-6-yl]ethynyl]silane Chemical compound C1=CC=C2C=C3C(C#C[Si](C(C)C)(C(C)C)C(C)C)=C(C=C4C(C=CC=C4)=C4)C4=C(C#C[Si](C(C)C)(C(C)C)C(C)C)C3=CC2=C1 FMZQNTNMBORAJM-UHFFFAOYSA-N 0.000 description 3
- 239000004793 Polystyrene Substances 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- UVAMFBJPMUMURT-UHFFFAOYSA-N 2,3,4,5,6-pentafluorobenzenethiol Chemical compound FC1=C(F)C(F)=C(S)C(F)=C1F UVAMFBJPMUMURT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229920005839 ecoflex® Polymers 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002048 multi walled nanotube Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920000172 poly(styrenesulfonic acid) Polymers 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 229940005642 polystyrene sulfonic acid Drugs 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002109 single walled nanotube Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
Abstract
The invention relates to an external trigger touch sensing array and a preparation method thereof. The external trigger touch sensing array includes: a substrate; the double-gate thin film transistor array is positioned on the surface of the substrate and comprises a plurality of double-gate thin film transistors which are arranged in an array manner; the lower isolation column is positioned on the surface of the double-gate thin film transistor array, which is away from the substrate; the bottom flexible antistatic film is positioned above the lower isolation column, the bottom surface of the bottom flexible antistatic film, which faces the lower isolation column, is provided with a coplanar electrode, and the top surface of the bottom flexible antistatic film, which faces away from the lower isolation column, is provided with a triggering row electrode; the upper isolation column is positioned on the surface of the trigger row electrode, which is away from the substrate; the top layer flexible antistatic film is positioned above the upper isolation column, and the bottom surface of the top layer flexible antistatic film, which faces the upper isolation column, is provided with a coplanar top electrode. The invention improves the refresh rate of the sensing array and reduces the power consumption of the sensing array.
Description
Technical Field
The invention relates to the technical field of sensing, in particular to an external trigger touch sensing array and a preparation method thereof.
Background
In recent years, with rapid development of wearable products, a flexible sensor assembly has become one of hot spot subjects explored by researchers. Among them, the flexible touch sensor is particularly widely focused, and has very broad market prospects in the fields of artificial electronic skin, flexible touch screens, intelligent robots, medical health and the like.
Currently, the research on flexible touch sensors may be based on various working principles, mainly including capacitive, resistive, piezoelectric and thin film transistor. For a large-area thin film touch sensing array, due to the rapid increase of the number of pixels, the problems of high power consumption, complex driving circuit, long time delay, serious signal crosstalk and the like exist, and the application requirements of complex scenes are difficult to meet. And the traditional full array row-by-row scanning mode is adopted to realize the response and identification of the touch control on the surface of the touch control sensing array, so that remarkable power consumption is brought, and the touch control sensing array depends on a peripheral complex silicon chip control circuit.
Therefore, how to reduce the delay of the touch sensor under the condition of meeting the low power consumption, thereby realizing the design optimization of the array integrated structure, the circuit performance and the power consumption is a technical problem to be solved currently.
Disclosure of Invention
The invention provides an external trigger touch sensing array and a preparation method thereof, which are used for solving the problems of higher power consumption and long time delay of the traditional touch sensing array.
In order to solve the above problems, the present invention provides an external trigger touch sensing array, including:
a substrate;
the double-gate thin film transistor array is positioned on the surface of the substrate and comprises a plurality of double-gate thin film transistors which are arranged in an array manner;
the lower isolation column is positioned on the surface of the double-gate thin film transistor array, which is away from the substrate;
the bottom flexible antistatic film is positioned above the lower isolation column, the bottom surface of the bottom flexible antistatic film, which faces the lower isolation column, is provided with a coplanar electrode, and the top surface of the bottom flexible antistatic film, which faces away from the lower isolation column, is provided with a triggering row electrode;
the upper isolation column is positioned on the surface of the trigger row electrode, which is away from the substrate;
the top layer flexible antistatic film is positioned above the upper isolation column, and the bottom surface of the top layer flexible antistatic film, which faces the upper isolation column, is provided with a coplanar top electrode.
Optionally, the dual gate thin film transistor includes:
a bottom gate electrode on the surface of the substrate;
an insulating layer covering the bottom gate electrode;
the source electrode and the drain electrode are positioned on the surface of the insulating layer;
a semiconductor layer covering the source electrode and the drain electrode;
a passivation layer covering the semiconductor layer;
and a top gate electrode covering the passivation layer.
Optionally, in the dual-gate thin film transistor array, the bottom gate electrodes of all the dual-gate thin film transistors in the same row are connected with the same row driving line;
in the double-gate thin film transistor array, the drain electrodes of all the double-gate thin film transistors in the same column are connected with the same column of scanning data lines;
in the double-gate thin film transistor array, the source electrodes of all the double-gate thin film transistors are connected with the same common electrode line.
Optionally, the number of the trigger row electrodes is plural, and plural trigger row electrodes are connected with plural row driving lines in one-to-one correspondence.
Optionally, the method further comprises:
and the pressure-sensitive film or the photosensitive film is positioned between the double-gate thin film transistor and the coplanar electrode.
Optionally, in a direction perpendicular to the substrate, a projected area of the top gate electrode in the same dual gate thin film transistor is greater than or equal to a projected area of the bottom gate electrode.
Optionally, the upper isolation column and the lower isolation column are made of polydimethylsiloxane, poly (butylene adipate/terephthalate) blend, polyurethane or photoresist.
Optionally, the height of the lower isolation columns is 1-50 micrometers, and the distance between two adjacent lower isolation columns is 1-50 sensing pixels;
the height of the upper isolation columns is 1-50 micrometers, and the distance between two adjacent upper isolation columns is 1-50 sensing pixels.
Optionally, the double-gate thin film transistor is an organic thin film transistor, a carbon nanotube thin film transistor, an amorphous oxide thin film transistor, an amorphous silicon thin film transistor, or a polysilicon thin film transistor.
Optionally, the materials of the bottom flexible antistatic film and the top flexible antistatic film are polyurethane, polyimide, polyethylene terephthalate, polyethylene naphthalate, polydimethylsiloxane or platinum catalyzed silica gel.
Optionally, the materials of the bottom gate electrode, the source electrode, the drain electrode, the top gate electrode, the coplanar electrode, the trigger row electrode, and the coplanar top electrode are all conductive polymers, carbon-based conductors, metals, metal oxides, metal nanowires, metal nanoparticles, or metal oxide nanoparticles.
In order to solve the above problems, the present invention further provides a method for preparing the external trigger touch sensor array according to any one of the above, which includes the following steps:
providing a substrate;
forming a bottom gate electrode and a row driving line on the surface of the substrate;
forming an insulating layer covering the bottom gate electrode, the row driving line, and the substrate surface;
forming a source electrode, a drain electrode, a column scanning data line and a common electrode line on the surface of the insulating layer;
forming a semiconductor layer covering the source electrode, the drain electrode, and the insulating layer;
forming a passivation layer covering the semiconductor layer;
forming a top gate electrode on the surface of the passivation layer;
forming a coplanar electrode on the bottom surface of the bottom flexible antistatic film, and forming a trigger row electrode on the top surface of the bottom flexible antistatic film, wherein the surface of the coplanar electrode, which is away from the bottom flexible antistatic film, is provided with a lower isolation column;
attaching the bottom flexible antistatic film to the surface of the passivation layer, so that the passivation layer is in contact with the lower isolation column, and a plurality of trigger row electrodes are in one-to-one correspondence connection with a plurality of row driving lines;
forming a coplanar top electrode on the bottom surface of the top flexible antistatic film, wherein the surface of the coplanar top electrode, which is away from the top flexible antistatic film, is provided with an upper isolation column;
and attaching the top-layer flexible antistatic film to the surface of the bottom-layer flexible antistatic film, so that the upper isolation column is contacted with the trigger row electrode.
According to the external trigger touch sensing array and the preparation method thereof, the trigger row electrode and the coplanar top electrode are arranged in the touch sensing array, so that when external force or illumination conditions are changed, the bias voltages of the bottom gate electrode and the top gate electrode of the double-gate thin film transistor in the touch sensing array can be regulated and controlled, the performance of the double-gate thin film transistor device can be regulated and controlled, and the stressed position and the unstressed position or illumination and non-illumination double-gate thin film transistor device currents are obviously different. And the circuit system obtains the information of the touch position, even the information of the touch force by utilizing a row signal output by a trigger row and a column signal output by a double-gate thin film transistor array. The sensing and signal reading mode does not need to adopt a scanning mode to read signals, so that the refresh rate of the sensing array is improved, and the power consumption of the sensing array is reduced.
Drawings
FIG. 1 is a schematic diagram of a unit pixel in an externally triggered touch sensor array according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of an externally triggered touch sensor array in accordance with an embodiment of the present invention;
FIG. 3 is a flowchart of a method for manufacturing an external trigger touch sensor array according to an embodiment of the present invention;
fig. 4 to fig. 12 are schematic structural views of the embodiment of the present invention in the process of preparing the external trigger touch sensor array.
Detailed Description
The following describes a specific embodiment of a touch sensing array and a preparation method thereof in detail with reference to the accompanying drawings.
In this embodiment, an external trigger touch sensing array is provided, fig. 1 is a schematic structural diagram of unit pixels in the external trigger touch sensing array in the embodiment of the present invention, and fig. 2 is an equivalent circuit diagram of the external trigger touch sensing array in the embodiment of the present invention. As shown in fig. 1 and 2, the external trigger touch sensing array includes:
a substrate 100;
the double-gate thin film transistor array is positioned on the surface of the substrate 100 and comprises a plurality of double-gate thin film transistors arranged in an array manner;
a lower isolation pillar 108 located on a surface of the array of double gate thin film transistors facing away from the substrate 100;
a bottom flexible antistatic film 110 located above the lower isolation column 108, wherein a coplanar electrode 109 is arranged on the bottom surface of the bottom flexible antistatic film 110 facing the lower isolation column 108, and a trigger row electrode 111 is arranged on the top surface of the bottom flexible antistatic film 110 facing away from the lower isolation column 108;
upper isolation columns 112 located on the surface of the trigger row electrode 111 facing away from the substrate 100;
a top flexible antistatic film 114 is located above the upper isolation column 112, and the bottom surface of the top flexible antistatic film 114 facing the upper isolation column 112 is provided with a coplanar top electrode 113.
Optionally, the dual gate thin film transistor includes:
a bottom gate electrode 101 located on the surface of the substrate 100;
an insulating layer 102 covering the bottom gate electrode 101;
a source electrode 104 and a drain electrode 103 located on the surface of the insulating layer 102;
a semiconductor layer 105 covering the source electrode 104 and the drain electrode 103;
a passivation layer 106 covering the semiconductor layer 105;
a top gate electrode 107 overlying the passivation layer 106.
In this embodiment, the number of the elements is two or more. The bottom surface in this embodiment refers to the surface facing the substrate 100, and the top surface refers to the surface facing away from the substrate 100 and opposite to the bottom surface. Specifically, the material of the substrate 100 may be one or a combination of two or more of glass, polyimide, polyethylene terephthalate, polyethylene naphthalate, parylene, and polydimethylsiloxane. The substrate 100 serves as a carrier base for the external trigger touch sensor array.
The insulating layer 102 is used as a gate insulating layer of the dual-gate thin film transistor, and the material of the insulating layer 102 may be polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyvinyl alcohol (PVA), aluminum oxide, zirconium oxide, silicon dioxide (SiO) 2 ) Or silicon nitride (SiN) x ) Etc.
The material of the semiconductor layer 105 is an organic semiconductor material, or a carbon nanotube, or an inorganic zinc oxide, indium gallium zinc oxide, amorphous silicon, or polysilicon material. The organic semiconductor material is small organic molecules, polymers or a material obtained by blending small organic molecules and insulating polymers. For example, the material of the semiconductor layer 105 is a blend material of 6, 13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) and Polystyrene (PS); alternatively, for another example, the material of the semiconductor layer 105 is indium gallium zinc oxide.
The passivation layer 106 material may be polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyvinyl alcohol (PVA), silicon dioxide (SiO) 2 ) Or silicon nitride (SiN) x ) Etc.
Optionally, in the dual gate thin film transistor array, the bottom gate electrodes 101 of all the dual gate thin film transistors in the same row are connected to the same row driving line 205;
in the array of double-gate thin film transistors, the drain electrodes 103 of all the double-gate thin film transistors in the same column are connected with the same column of scanning data lines 206;
in the array of the double-gate thin film transistors, the source electrodes 104 of all the double-gate thin film transistors are connected to the same common electrode line 203.
Optionally, the number of the trigger row electrodes 111 is plural, and plural trigger row electrodes 111 are connected to plural row driving lines 205 in one-to-one correspondence.
Specifically, as shown in fig. 2, the external trigger touch sensor array includes a plurality of row driving lines 205, a plurality of column scanning data lines 206, a plurality of trigger row electrodes 111, and one common electrode line 203. The row driver 201 is connected to a plurality of the row driving lines 205 for driving each of the row driving lines 205, respectively. The column driver 202 is connected to a plurality of the column scan data lines 206, and is used for driving each of the column scan data lines 206. The trigger line driver 204 is connected to the plurality of trigger line electrodes 111, and is configured to receive the trigger line signal output by each of the trigger line electrodes 111. The trigger row electrodes 111 and the row driving lines 205 are respectively in one-to-one correspondence with the rows of the double-gate thin film transistor array, and the column scanning data lines 206 are respectively in one-to-one correspondence with the columns of the double-gate thin film transistor array. The plurality of the present embodiments is two or more, and the plurality is two or more. The coplanar electrode 109 is used to apply a fixed bias to the top gate electrode 107 of the double gate thin film transistor. The coplanar top electrode 113 is used to apply a fixed bias to the trigger row electrode 111. The bias voltages on the coplanar electrode 109 and the coplanar top electrode 113 include positive and negative voltages, and the bias voltages on the coplanar electrode 109 and the coplanar top electrode 113 may be the same or different, and may be selected by those skilled in the art according to actual needs.
When a certain position on the surface of the external trigger touch sensing array is touched, the trigger row electrode 111 contacts the coplanar top electrode 113 with a given bias voltage, so that voltage signals in the trigger row electrode 111 and the row driving line 205 connected with the trigger row electrode are changed, and row voltage signals are output. Meanwhile, the voltage of the top gate electrode 107 of the double gate thin film transistor in the unit sensing pixel located below the touched position changes, and only the voltage of the bottom gate electrode 101 in the double gate thin film transistor in the unit sensing pixel in the unstressed position (i.e., the untouched position) of the same row changes. The double-gate thin film transistors at the same row of touch positions and the same column of non-touch positions have obvious differences in current under the same bottom gate voltage, so that the column current signals of the touch position columns and the non-touch position columns have obvious differences, and the column current signals are output and converted into column voltage signals. The circuit system reads the output row voltage signals and the output column voltage signals to obtain information of touch positions, and obtains information of touch force according to the magnitude of the column voltage signals. By adopting the sensing and signal reading modes, the signal reading is not required to be performed in a scanning mode, the refresh rate of the sensing array is improved, and the power consumption of the column touch sensing array is reduced.
Optionally, the external trigger touch sensing array further includes:
a pressure sensitive or photosensitive film is located between the double gate thin film transistor and the coplanar electrode 109.
Specifically, the lower isolation pillar 108 is located on the surface of the passivation layer 106, and is used to form a first gap between the top gate electrode 107 and the coplanar electrode 109, so as to isolate the top gate electrode 107 and the coplanar electrode 109. The coplanar electrode 109 is capable of contacting the top gate electrode 107 when a unit sensing pixel is stressed. The first gap between the coplanar electrode 109 and the top gate electrode 107 of the dual gate thin film transistor may be filled with a capacitive or resistive pressure sensitive film or a photosensitive film, for changing the voltage of the top gate electrode 107 when the unit sensing pixels in the external trigger touch sensing array are stressed or the illumination condition is changed.
Alternatively, the projected area of the top gate electrode 107 in the same double gate thin film transistor is greater than or equal to the projected area of the bottom gate electrode 101 in a direction perpendicular to the substrate 100.
Specifically, the projected area of the top gate electrode 107 in the same dual-gate thin film transistor is greater than or equal to the projected area of the bottom gate electrode 101, which can enable: when the capacitive pressure-sensitive film is integrated between the double-gate thin film transistor and the coplanar electrode 109, the electrode area (capacitance) of the capacitive pressure-sensitive film is increased, the matching degree with the capacitance of the top gate insulating layer is improved, and the sensing sensitivity is improved; when a resistive pressure-sensitive film is integrated between the double gate thin film transistor and the coplanar electrode 109, the contact area of the pressure-sensitive film and the top gate electrode is increased, and uniformity is improved.
Alternatively, the materials of the upper isolation column 112 and the lower isolation column 108 are Polydimethylsiloxane (PDMS), poly (butylene adipate/terephthalate) blend (Ecoflex), polyurethane (PU), or photoresist.
Optionally, the height of the lower isolation pillars 108 is 1 to 50 micrometers, and the interval between two adjacent lower isolation pillars 108 is 1 to 50 sensing pixels;
the height of the upper isolation pillars 112 is 1-50 micrometers, and the distance between two adjacent upper isolation pillars 112 is 1-50 sensing pixels.
Specifically, the upper isolation column 112 is located on the upper surface of the bottom flexible antistatic film 110, and is used to form a second gap between the trigger line electrode 111 and the coplanar top electrode 113, thereby isolating the trigger line electrode 111 and the coplanar top electrode 113. The sensor pixel described in this embodiment includes a double-gate thin film transistor and a structure located above the double-gate thin film transistor. The size of the sensing pixels is the row size of the external trigger touch sensing array (i.e., the size of the sensing pixels is the size of one row in the external trigger touch sensing array) divided by the number of pixels on one row; alternatively, the size of the sensing pixels is the column size of the external trigger touch sensing array (i.e., the size of the sensing pixels is the size of one column in the external trigger touch sensing array) divided by the number of pixels on one column.
Optionally, the double-gate thin film transistor is an organic thin film transistor, a carbon nanotube thin film transistor, an amorphous oxide thin film transistor, an amorphous silicon thin film transistor, or a polysilicon thin film transistor.
For example, the amorphous oxide thin film transistor may be, but is not limited to, a zinc oxide thin film transistor, an indium gallium zinc oxide thin film transistor.
Optionally, the materials of the bottom flexible antistatic film 110 and the top flexible antistatic film 114 are polyurethane, polyimide, polyethylene terephthalate, polyethylene naphthalate, polydimethylsiloxane or platinum catalyzed silica gel.
Optionally, the materials of the bottom gate electrode 101, the source electrode 104, the drain electrode 103, the top gate electrode 107, the coplanar electrode 109, the trigger row electrode 111, and the coplanar top electrode 113 are all conductive polymers, carbon-based conductors, metals, metal oxides, metal nanowires, metal nanoparticles, or metal oxide nanoparticles. The conductive polymer can be poly (3, 4-ethylenedioxythiophene), polystyrene sulfonic acid, polyaniline, polythiophene or polypyrrole with acidic or neutral pH value, the carbon-based conductor can be single-layer or multi-layer graphene, graphite, carbon black, single-wall or multi-wall carbon nano tubes and the like, the metal can be gold, silver, copper, aluminum or molybdenum, and the metal oxide can be indium tin oxide or fluorine doped tin oxide and the like.
Furthermore, the present embodiment also provides a method for manufacturing the external trigger touch sensor array according to any one of the above. Fig. 3 is a flowchart of a method for manufacturing an external trigger touch sensor array according to an embodiment of the present invention, and fig. 4 to fig. 12 are schematic structural diagrams of the external trigger touch sensor array according to an embodiment of the present invention in the process of manufacturing the external trigger touch sensor array. The schematic structural diagram of the external trigger touch sensor array prepared in this embodiment can be seen in fig. 1 and fig. 2. As shown in fig. 1 to 12, the preparation method of the external trigger touch sensing array includes the following steps:
in step S31, a substrate 100 is provided.
In step S32, a bottom gate electrode 101 and a row driving line 205 are formed on the surface of the substrate 100, as shown in fig. 4.
Specifically, before forming the bottom gate electrode 101 and the line driving line 205, the substrate 100 may be ultrasonically cleaned using an ethanol solution, an acetone solution, and deionized water, and dried after cleaning, and the surface of the substrate 100 is treated with oxygen plasma or ultraviolet light/ozone.
In this embodiment, the bottom gate electrodes 101 of all the double-gate thin film transistors in the double-gate thin film transistor array are formed simultaneously, the same number of the row driving lines 205 as the number of the rows of the double-gate thin film transistor array are formed, and the bottom gate electrodes 101 of all the double-gate thin film transistors located in the same row of the double-gate thin film transistor array are electrically connected to one row driving line 205 corresponding to the row.
The material of the row driving lines 205 and the bottom gate electrode 101 may be a conductive polymer, a carbon-based conductive material, a metal oxide, a metal nanowire, a metal nanoparticle, or a metal oxide nanoparticle. The row driving lines 205 and the bottom gate electrode 101 may be formed on the surface of the substrate 100 by vacuum evaporation, magnetron sputtering, photolithography, inkjet printing, screen printing, or gravure printing.
In step S33, an insulating layer 102 is formed to cover the bottom gate electrode 101, the row driving line 205, and the surface of the substrate 100, as shown in fig. 5.
Specifically, the material of the insulating layer 102 may be an organic insulating layer material, such as polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), or polyvinyl alcohol (PVA), or may be inorganic silica (SiO 2 ) Silicon nitride (SiN) x ) Etc. The method for forming the insulating layer 102 includes: the insulating film is formed by vacuum evaporation, plasma enhanced chemical vapor deposition, spin coating, knife coating or ink jet printing. After the organic insulating layer material is formed into a film, ultraviolet light with the wavelength of 195-365 nm is used for irradiation or cross-linking and drying treatment are carried out under the heating condition, so that the insulating layer 102 is formed.
In step S34, the source electrode 104, the drain electrode 103, the column scan data line 206 and the common electrode line 203 are formed on the surface of the insulating layer 102, as shown in fig. 6.
Specifically, the column scan data line 206, the common electrode line 203, the source electrode 104 and the drain electrode 103 are formed on the surface of the insulating layer 102, the drain electrodes 103 of all the double-gate thin film transistors in the same column in the double-gate thin film transistor array are connected to the corresponding same column scan data line 206, and the source electrodes 104 of all the double-gate thin film transistors in the double-gate thin film transistor array are connected to the common electrode line 203.
The materials of the column scan data line 206, the common electrode line 203, the source electrode 104, and the drain electrode 103 may be conductive polymers, carbon-based conductors, metals, metal oxides, metal nanowires, metal nanoparticles, or metal oxide nanoparticles. The column scan data lines 206, the common electrode lines 203, the source electrodes 104, and the drain electrodes 103 may be formed on the surface of the insulating layer 102 by vacuum evaporation, magnetron sputtering, photolithography, inkjet printing, screen printing, or gravure printing.
In step S35, a semiconductor layer 105 is formed to cover the source electrode 104, the drain electrode 103, and the insulating layer 102, as shown in fig. 7.
Specifically, the semiconductor layer 105 may be formed on the surfaces of the insulating layer 102, the source electrode 104, and the drain electrode 103 using a plasma enhanced chemical vapor deposition, spin coating, knife coating, lift-off, or inkjet printing process.
In other embodiments, the semiconductor layer 105 may be formed on the surface of the insulating layer 102, and then the column scan data line 206, the common electrode line 204, the source electrode 104, and the drain electrode 103 may be formed by photolithography and etching processes.
In step S36, a passivation layer 106 is formed to cover the semiconductor layer 105, as shown in fig. 8.
Specifically, the passivation layer 106 may be formed using a plasma enhanced chemical vapor deposition, spin coating, knife coating, lift-off, or inkjet printing process.
In step S37, a top gate electrode 107 is formed on the passivation layer 106, as shown in fig. 9.
Specifically, the top gate electrode 107 may be formed on the surface of the passivation layer 106 by vacuum evaporation, magnetron sputtering, photolithography, inkjet printing, screen printing, or gravure printing.
In step S38, a coplanar electrode 109 is formed on the bottom surface of the bottom flexible antistatic film 110, and a trigger row electrode 111 is formed on the top surface of the bottom flexible antistatic film 110, where the surface of the coplanar electrode 109 facing away from the bottom flexible antistatic film 110 has a lower isolation column 108, as shown in fig. 10.
Specifically, the coplanar electrodes 109 may be formed on the bottom surface of the bottom flexible antistatic film 110 and the trigger row electrodes 111 may be formed on the top surface of the bottom flexible antistatic film 110 by vacuum evaporation, magnetron sputtering, photolithography, inkjet printing, screen printing, or gravure printing. The lower isolation posts 108 may be formed on the surface of the coplanar electrode 109 facing away from the underlying flexible antistatic film 110 by photolithography, dispensing, or screen printing.
In step S39, the bottom flexible antistatic film 110 is attached to the surface of the passivation layer 106, so that the passivation layer 106 contacts the lower isolation pillars 108, and the plurality of trigger row electrodes 111 are connected to the plurality of row driving lines 205 in a one-to-one correspondence manner, as shown in fig. 11.
In step S40, a coplanar top electrode 113 is formed on the bottom surface of the top flexible antistatic film 114, and an upper isolation column 112 is provided on the surface of the coplanar top electrode 113 facing away from the top flexible antistatic film 114.
In step S41, the top flexible antistatic film 114 is attached to the surface of the bottom flexible antistatic film 110, so that the upper isolation column 112 contacts with the trigger row electrode 111, as shown in fig. 12.
Specifically, the coplanar top electrode 113 may be formed by vacuum evaporation, magnetron sputtering, photolithography, inkjet printing, screen printing, or gravure printing. The upper isolation column 112 may be formed by photolithography, dispensing, screen printing.
According to the external trigger touch sensing array and the preparation method thereof, the trigger row electrode and the coplanar top electrode are arranged in the touch sensing array, so that when external force or illumination conditions are changed, bias voltages of the bottom gate electrode and the top gate electrode of the double-gate thin film transistor in the touch sensing array can be regulated and controlled, the performance of the double-gate thin film transistor device is regulated and controlled, and the stressed position and the unstressed position or illumination and non-illumination double-gate thin film transistor device currents are obviously different. And the circuit system obtains the information of the touch position, even the information of the touch force by utilizing a row signal output by a trigger row and a column signal output by a double-gate thin film transistor array. The sensing and signal reading mode does not need to adopt a scanning mode to read signals, so that the refresh rate of the sensing array is improved, and the power consumption of the sensing array is reduced.
The following are 5 examples of forming the external trigger touch sensor array.
Example 1
(1) Respectively carrying out ultrasonic cleaning on a polyethylene terephthalate (PET) substrate by using an ethanol solution, an acetone solution and deionized water, drying after cleaning, and treating the surface of the substrate by adopting oxygen plasma or ultraviolet light/ozone;
(2) Preparing a line driving line and a bottom gate electrode of a double-gate thin film transistor array on a polyimide substrate by adopting a vacuum evaporation mode;
(3) Preparing a PVCN insulating layer film on the bottom gate electrode by adopting a spin coating process, and then carrying out ultraviolet crosslinking heating and drying;
(4) Preparing a column scanning data line, a common electrode line and source and drain electrodes of a double-gate thin film transistor array on a substrate by adopting a vacuum evaporation mode;
(5) Modifying a monolayer PFBT on the surfaces of a source electrode and a drain electrode of the double-gate thin film transistor in a self-assembly mode so as to improve the contact between the source electrode, the drain electrode and a semiconductor layer;
(6) Forming a blend layer of an organic semiconductor material TIPS-pentacene and an insulating material PS on the surfaces of the insulating layer and the source electrode and the drain electrode by adopting a knife coating process, and then annealing at 100 ℃ for 30 minutes to improve the crystallization of the organic semiconductor layer;
(7) Preparing a silicon dioxide passivation layer on the surface of the semiconductor layer by adopting a plasma enhanced chemical vapor deposition mode;
(8) Preparing a top gate electrode on the surface of the silicon dioxide passivation layer by adopting a vacuum evaporation mode;
(9) Forming a coplanar electrode and a trigger row electrode on the upper surface and the lower surface of a bottom flexible antistatic film of a polyethylene terephthalate (PET) material by adopting a screen printing mode;
(10) Forming PDMS lower isolation columns on the surface of the coplanar electrode by adopting a screen printing mode;
(11) Attaching a bottom flexible antistatic film containing a lower isolation column to the surface of a top gate electrode according to the downward direction of the lower isolation column, and connecting trigger row electrodes with row driving lines in a one-to-one correspondence manner;
(12) Forming a coplanar top electrode on the surface of a top flexible antistatic film of a polyethylene terephthalate (PET) material by adopting a screen printing mode;
(13) Forming PDMS upper isolation columns on the surface of the coplanar top electrode by adopting a screen printing mode;
(14) And attaching the top flexible antistatic film containing the upper isolation column to the surface of the trigger row electrode according to the downward direction of the upper isolation column to form the external trigger touch sensing array.
Example 2
(1) Respectively carrying out ultrasonic cleaning on a polyethylene naphthalate (PEN) substrate by using an ethanol solution, an acetone solution and deionized water, drying after cleaning, and treating the surface of the substrate by adopting oxygen plasma or ultraviolet light/ozone;
(2) Preparing a line driving line and a bottom gate electrode of a double-gate thin film transistor on a polyimide substrate by adopting magnetron sputtering and photoetching processes;
(3) Forming a silicon nitride insulating layer on the surface of the bottom gate electrode by adopting a plasma enhanced chemical vapor deposition process;
(4) Forming an amorphous silicon semiconductor layer on the surface of the insulating layer by adopting a plasma enhanced chemical vapor deposition and photoetching process;
(5) Preparing a column scanning data line, a common electrode line and source and drain electrodes of a double-gate thin film transistor by adopting magnetron sputtering and photoetching processes;
(7) Preparing a silicon dioxide passivation layer on the surface of the semiconductor layer by adopting a plasma enhanced chemical vapor deposition mode;
(8) Preparing a top gate electrode on the surface of the silicon dioxide passivation layer by adopting a magnetron sputtering and photoetching process preparation mode;
(9) Forming a coplanar electrode and a trigger row electrode on the upper and lower surfaces of a bottom flexible antistatic film made of polyethylene naphthalate (PEN) material in a screen printing mode, wherein the trigger row electrode is connected with a row driving line in a one-to-one correspondence manner;
(10) Forming PDMS lower isolation columns on the surface of the coplanar electrode by adopting a screen printing mode;
(11) Attaching a bottom flexible antistatic film containing a lower isolation column to the surface of the top gate electrode according to the downward direction of the lower isolation column;
(12) Forming a coplanar top electrode on the surface of the top flexible antistatic film by adopting a screen printing mode;
(13) Forming PDMS upper isolation columns on the surface of the coplanar top electrode by adopting a screen printing mode;
(14) And attaching the top flexible antistatic film containing the upper isolation column to the surface of the trigger row electrode according to the downward direction of the upper isolation column to form the external trigger touch sensing array.
Example 3
(1) Respectively carrying out ultrasonic cleaning on a Polyimide (PI) substrate by using an ethanol solution, an acetone solution and deionized water, drying after cleaning, and treating the surface of the substrate by adopting oxygen plasma or ultraviolet light/ozone;
(2) Preparing a line driving line and a bottom gate electrode of a double-gate thin film transistor on a polyimide substrate by adopting magnetron sputtering and photoetching processes;
(3) Forming a silicon nitride insulating layer on the surface of the bottom gate electrode by adopting a plasma enhanced chemical vapor deposition process;
(4) Forming an Indium Gallium Zinc Oxide (IGZO) semiconductor layer on the surface of the insulating layer by adopting a plasma enhanced chemical vapor deposition and photoetching process;
(5) Preparing a column scanning data line, a common electrode line and source and drain electrodes of a double-gate thin film transistor by adopting magnetron sputtering and photoetching processes;
(7) Preparing a silicon dioxide passivation layer on the surface of the semiconductor layer by adopting a plasma enhanced chemical vapor deposition mode;
(8) Preparing a top gate electrode on the surface of the silicon dioxide passivation layer by adopting a magnetron sputtering and photoetching process preparation mode;
(9) Forming a coplanar electrode and a trigger row electrode on the upper and lower surfaces of a flexible antistatic film of a bottom layer of Polyimide (PI) material in a screen printing mode, wherein the trigger row electrode is connected with a row driving line in a one-to-one correspondence manner;
(10) Forming PDMS lower isolation columns on the surface of the coplanar electrode by adopting a screen printing mode;
(11) Attaching a bottom flexible antistatic film containing a lower isolation column to the surface of the top gate electrode according to the downward direction of the lower isolation column;
(12) Forming a coplanar top electrode on the surface of a top flexible antistatic film of Polyimide (PI) material by adopting a screen printing mode;
(13) Forming PDMS upper isolation columns on the surface of the coplanar top electrode by adopting a screen printing mode;
(14) And attaching the top flexible antistatic film containing the upper isolation column to the surface of the trigger row electrode according to the downward direction of the upper isolation column to form the external trigger touch sensing array.
Example 4
(1) Respectively carrying out ultrasonic cleaning on a Polyimide (PI) substrate by using an ethanol solution, an acetone solution and deionized water, drying after cleaning, and treating the surface of the substrate by adopting oxygen plasma or ultraviolet light/ozone;
(2) Preparing a line driving line and a bottom gate electrode of a double-gate thin film transistor on a polyimide substrate by adopting magnetron sputtering and photoetching processes;
(3) Forming a silicon nitride insulating layer on the surface of the bottom gate electrode by adopting a plasma enhanced chemical vapor deposition process;
(4) Forming an Indium Gallium Zinc Oxide (IGZO) semiconductor layer on the surface of the insulating layer by adopting a plasma enhanced chemical vapor deposition and photoetching process;
(5) Preparing a column scanning data line, a common electrode line and source and drain electrodes of a double-gate thin film transistor by adopting magnetron sputtering and photoetching processes;
(7) Preparing a silicon dioxide passivation layer on the surface of the semiconductor layer by adopting a plasma enhanced chemical vapor deposition mode;
(8) Preparing a top gate electrode on the surface of the silicon dioxide passivation layer by adopting a magnetron sputtering and photoetching process preparation mode;
(9) Forming a coplanar electrode and a trigger row electrode on the upper and lower surfaces of a flexible antistatic film of a bottom layer of Polyimide (PI) material in a screen printing mode, wherein the trigger row electrode is connected with a row driving line in a one-to-one correspondence manner;
(10) Forming PDMS lower isolation columns on the surface of the coplanar electrode by adopting a screen printing mode;
(11) Forming a capacitive pressure sensitive film at the space between the lower isolation columns;
(12) Attaching a bottom flexible antistatic film containing a lower isolation column to the surface of the top gate electrode according to the downward direction of the lower isolation column;
(13) Forming a coplanar top electrode on the surface of a top flexible antistatic film of Polyimide (PI) material by adopting a screen printing mode;
(14) Forming PDMS upper isolation columns on the surface of the coplanar top electrode by adopting a screen printing mode;
(15) And attaching the top flexible antistatic film containing the upper isolation column to the surface of the trigger row electrode according to the downward direction of the upper isolation column to form the external trigger touch sensing array.
Example 5
(1) Respectively carrying out ultrasonic cleaning on a Polyimide (PI) substrate by using an ethanol solution, an acetone solution and deionized water, drying after cleaning, and treating the surface of the substrate by adopting oxygen plasma or ultraviolet light/ozone;
(2) Preparing a line driving line and a bottom gate electrode of a double-gate thin film transistor on a polyimide substrate by adopting magnetron sputtering and photoetching processes;
(3) Forming a silicon nitride insulating layer on the surface of the bottom gate electrode by adopting a plasma enhanced chemical vapor deposition process;
(4) Forming an Indium Gallium Zinc Oxide (IGZO) semiconductor layer on the surface of the insulating layer by adopting a plasma enhanced chemical vapor deposition and photoetching process;
(5) Preparing a column scanning data line, a common electrode line and source and drain electrodes of a double-gate thin film transistor by adopting magnetron sputtering and photoetching processes;
(7) Preparing a silicon dioxide passivation layer on the surface of the semiconductor layer by adopting a plasma enhanced chemical vapor deposition mode;
(8) Preparing a top gate electrode on the surface of the silicon dioxide passivation layer by adopting a magnetron sputtering and photoetching process preparation mode;
(9) Forming a coplanar electrode and a trigger row electrode on the upper and lower surfaces of a flexible antistatic film of a bottom layer of Polyimide (PI) material in a screen printing mode, wherein the trigger row electrode is connected with a row driving line in a one-to-one correspondence manner;
(10) Forming PDMS lower isolation columns on the surface of the coplanar electrode by adopting a screen printing mode;
(11) Forming a resistive pressure sensitive film at the space between the lower isolation columns;
(12) Attaching a bottom flexible antistatic film containing a lower isolation column to the surface of the top gate electrode according to the downward direction of the lower isolation column;
(13) Forming a coplanar top electrode on the surface of a top flexible antistatic film of Polyimide (PI) material by adopting a screen printing mode;
(14) Forming PDMS upper isolation columns on the surface of the coplanar top electrode by adopting a screen printing mode;
(15) And attaching the top flexible antistatic film containing the upper isolation column to the surface of the trigger row electrode according to the downward direction of the upper isolation column to form the external trigger touch sensing array.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (11)
1. An externally triggered touch sensing array comprising:
a substrate;
the double-gate thin film transistor array is positioned on the surface of the substrate and comprises a plurality of double-gate thin film transistors which are arranged in an array manner;
the lower isolation column is positioned on the surface of the double-gate thin film transistor array, which is away from the substrate;
the bottom flexible antistatic film is positioned above the lower isolation column, the bottom surface of the bottom flexible antistatic film, which faces the lower isolation column, is provided with a coplanar electrode, and the top surface of the bottom flexible antistatic film, which faces away from the lower isolation column, is provided with a triggering row electrode;
the upper isolation column is positioned on the surface of the trigger row electrode, which is away from the substrate;
the top layer flexible antistatic film is positioned above the upper isolation column, and the bottom surface of the top layer flexible antistatic film, which faces the upper isolation column, is provided with a coplanar top electrode;
the double gate thin film transistor includes:
a bottom gate electrode on the surface of the substrate;
an insulating layer covering the bottom gate electrode;
the source electrode and the drain electrode are positioned on the surface of the insulating layer;
a semiconductor layer covering the source electrode and the drain electrode;
a passivation layer covering the semiconductor layer;
and a top gate electrode covering the passivation layer.
2. The externally triggered touch sensor array of claim 1 wherein the bottom gate electrodes of all of the double gate thin film transistors of a same row are connected to a same row drive line in the double gate thin film transistor array;
in the double-gate thin film transistor array, the drain electrodes of all the double-gate thin film transistors in the same column are connected with the same column of scanning data lines;
in the double-gate thin film transistor array, the source electrodes of all the double-gate thin film transistors are connected with the same common electrode line.
3. The externally triggered touch sensor array of claim 2 wherein the number of trigger row electrodes is a plurality and the plurality of trigger row electrodes are connected in one-to-one correspondence with the plurality of row drive lines.
4. The externally triggered touch sensor array of claim 1 further comprising:
and the pressure-sensitive film or the photosensitive film is positioned between the double-gate thin film transistor and the coplanar electrode.
5. The externally triggered touch sensor array of claim 1 wherein the projected area of the top gate electrode in the same dual gate thin film transistor is greater than or equal to the projected area of the bottom gate electrode in a direction perpendicular to the substrate.
6. The externally triggered touch sensor array of claim 1 wherein the materials of the upper and lower isolation posts are polydimethylsiloxane, poly (butylene adipate/terephthalate) blend, polyurethane, or photoresist.
7. The externally triggered touch sensing array of claim 1, wherein the height of the lower isolation posts is 1-50 microns, and the distance between two adjacent lower isolation posts is 1-50 sensing pixels;
the height of the upper isolation columns is 1-50 microns, and the distance between every two adjacent upper isolation columns is 1-50 sensing pixels.
8. The externally triggered touch sensor array of claim 1 wherein the dual gate thin film transistor is an organic thin film transistor, a carbon nanotube thin film transistor, an amorphous oxide thin film transistor, an amorphous silicon thin film transistor, or a polysilicon thin film transistor.
9. The externally triggered touch sensor array of claim 1 wherein the materials of the bottom flexible antistatic film and the top flexible antistatic film are polyurethane, polyimide, polyethylene terephthalate, polyethylene naphthalate, polydimethylsiloxane or platinum catalyzed silica gel.
10. The externally triggered touch sensing array of claim 1, wherein the materials of the bottom gate electrode, the source electrode, the drain electrode, the top gate electrode, the coplanar electrode, the trigger row electrode, and the coplanar top electrode are all conductive polymers, carbon-based conductors, metals, metal oxides, metal nanowires, metal nanoparticles, or metal oxide nanoparticles.
11. A method of manufacturing an externally triggered touch sensing array as claimed in any of claims 1 to 10 comprising the steps of:
providing a substrate;
forming a bottom gate electrode and a row driving line on the surface of the substrate;
forming an insulating layer covering the bottom gate electrode, the row driving line, and the substrate surface;
forming a source electrode, a drain electrode, a column scanning data line and a common electrode line on the surface of the insulating layer;
forming a semiconductor layer covering the source electrode, the drain electrode, and the insulating layer;
forming a passivation layer covering the semiconductor layer;
forming a top gate electrode on the surface of the passivation layer;
forming a coplanar electrode on the bottom surface of the bottom flexible antistatic film, and forming a trigger row electrode on the top surface of the bottom flexible antistatic film, wherein the surface of the coplanar electrode, which is away from the bottom flexible antistatic film, is provided with a lower isolation column;
attaching the bottom flexible antistatic film to the surface of the passivation layer, so that the passivation layer is in contact with the lower isolation column, and a plurality of trigger row electrodes are in one-to-one correspondence connection with a plurality of row driving lines;
forming a coplanar top electrode on the bottom surface of the top flexible antistatic film, wherein the surface of the coplanar top electrode, which is away from the top flexible antistatic film, is provided with an upper isolation column;
and attaching the top-layer flexible antistatic film to the surface of the bottom-layer flexible antistatic film, so that the upper isolation column is contacted with the trigger row electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111230664.3A CN114035710B (en) | 2021-10-22 | 2021-10-22 | External trigger touch sensing array and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111230664.3A CN114035710B (en) | 2021-10-22 | 2021-10-22 | External trigger touch sensing array and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114035710A CN114035710A (en) | 2022-02-11 |
| CN114035710B true CN114035710B (en) | 2024-04-12 |
Family
ID=80135111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111230664.3A Active CN114035710B (en) | 2021-10-22 | 2021-10-22 | External trigger touch sensing array and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114035710B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015277A2 (en) * | 2000-08-14 | 2002-02-21 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
| CN1472994A (en) * | 2003-06-23 | 2004-02-04 | 清华大学 | Organic electrofluorescence device and producing mehtod thereof |
| CN1904702A (en) * | 2005-07-30 | 2007-01-31 | 三星电子株式会社 | Liquid crystal display and method of manufacturing the same |
| CN105242443A (en) * | 2015-10-28 | 2016-01-13 | 深圳市华星光电技术有限公司 | Reflective dual-face LCD |
| CN105552132A (en) * | 2016-02-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Thin film transistor sensor and fabrication method thereof |
| CN105702682A (en) * | 2016-01-25 | 2016-06-22 | 昆山龙腾光电有限公司 | Thin film transistor array substrate, manufacturing method, and liquid crystal display panel |
| CN106406590A (en) * | 2015-07-31 | 2017-02-15 | 昆山国显光电有限公司 | Touch control display apparatus and preparation method thereof |
| CN110137204A (en) * | 2019-05-15 | 2019-08-16 | 上海交通大学 | Organic Thin Film Transistors type sensing pixels circuit and micro-array chip |
| CN111811700A (en) * | 2020-06-11 | 2020-10-23 | 上海交通大学 | Pressure sensor, pressure sensing device and preparation method thereof |
| WO2020244502A1 (en) * | 2019-06-05 | 2020-12-10 | 京东方科技集团股份有限公司 | Touch-control display substrate and manufacturing method therefor, and touch-control display apparatus |
-
2021
- 2021-10-22 CN CN202111230664.3A patent/CN114035710B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002015277A2 (en) * | 2000-08-14 | 2002-02-21 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
| CN101179079A (en) * | 2000-08-14 | 2008-05-14 | 矩阵半导体公司 | Rail stack array of charge storage devices and method of making same |
| JP5792918B2 (en) * | 2000-08-14 | 2015-10-14 | サンディスク・スリー・ディ・リミテッド・ライアビリティ・カンパニーＳａｎｄｉｓｋ ３Ｄ Ｌｌｃ | Highly integrated memory device |
| CN1472994A (en) * | 2003-06-23 | 2004-02-04 | 清华大学 | Organic electrofluorescence device and producing mehtod thereof |
| CN1904702A (en) * | 2005-07-30 | 2007-01-31 | 三星电子株式会社 | Liquid crystal display and method of manufacturing the same |
| CN106406590A (en) * | 2015-07-31 | 2017-02-15 | 昆山国显光电有限公司 | Touch control display apparatus and preparation method thereof |
| CN105242443A (en) * | 2015-10-28 | 2016-01-13 | 深圳市华星光电技术有限公司 | Reflective dual-face LCD |
| CN105702682A (en) * | 2016-01-25 | 2016-06-22 | 昆山龙腾光电有限公司 | Thin film transistor array substrate, manufacturing method, and liquid crystal display panel |
| CN105552132A (en) * | 2016-02-04 | 2016-05-04 | 京东方科技集团股份有限公司 | Thin film transistor sensor and fabrication method thereof |
| CN110137204A (en) * | 2019-05-15 | 2019-08-16 | 上海交通大学 | Organic Thin Film Transistors type sensing pixels circuit and micro-array chip |
| WO2020244502A1 (en) * | 2019-06-05 | 2020-12-10 | 京东方科技集团股份有限公司 | Touch-control display substrate and manufacturing method therefor, and touch-control display apparatus |
| CN111811700A (en) * | 2020-06-11 | 2020-10-23 | 上海交通大学 | Pressure sensor, pressure sensing device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114035710A (en) | 2022-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107843364B (en) | Pressure sensor, pressure sensor array and preparation method thereof | |
| US8502228B2 (en) | Thin film transistor array, method for manufacturing the same, and active matrix type display using the same | |
| KR101432733B1 (en) | Manufacturing method of thin film transistor and thin film transistor, and display | |
| US7825911B2 (en) | Touch sensor, touch pad and input device | |
| JP5376287B2 (en) | Circuit board, electro-optical device, electronic equipment | |
| JP5396698B2 (en) | pressure sensor | |
| US8269219B2 (en) | Printed TFT and TFT array with self-aligned gate | |
| CN111811700B (en) | Pressure sensor, pressure sensing device and preparation method thereof | |
| JP5439723B2 (en) | Thin film transistor, matrix substrate, electrophoretic display device and electronic device | |
| US9153626B2 (en) | Thin film transistor having at least two carbon nanotube patterns formed in a channel and connected by at least one floating electrode and a display device including the same | |
| CN111785745B (en) | Optical sensor, optical sensing device and preparation method thereof | |
| CN113884226B (en) | Pressure sensor, pressure sensing array and preparation method thereof | |
| CN114035710B (en) | External trigger touch sensing array and preparation method thereof | |
| CN109817722B (en) | Driving device based on carbon nano tube thin film transistor and preparation method thereof | |
| CN114035711B (en) | External trigger touch sensing array and preparation method thereof | |
| WO2016067591A1 (en) | Thin-film transistor array and method for manufacturing same | |
| JP4699090B2 (en) | ORGANIC THIN FILM TRANSISTOR, DISPLAY DEVICE EQUIPPED WITH THE SAME, AND METHOD FOR PRODUCING ORGANIC THIN FILM TRANSISTOR | |
| CN110137203B (en) | Pixel sensing structure, sensing device and forming method of pixel sensing structure | |
| US11830904B2 (en) | Light sensing device having offset gate electrode and light sensing panel and light sensing display panel using the same | |
| CN114577376B (en) | Pressure sensing array and preparation method thereof | |
| TWI826003B (en) | Sensing electronic device | |
| KR101267353B1 (en) | transistor-based touch panel | |
| CN114721553A (en) | Touch structure, OLED touch display panel and manufacturing method | |
| KR101287315B1 (en) | Sensing Cell of using Carbon Nanotube and Touch Panel of using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |