CN114025111B - Comparator circuit, readout circuit and image sensor - Google Patents
Comparator circuit, readout circuit and image sensor Download PDFInfo
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- CN114025111B CN114025111B CN202111295614.3A CN202111295614A CN114025111B CN 114025111 B CN114025111 B CN 114025111B CN 202111295614 A CN202111295614 A CN 202111295614A CN 114025111 B CN114025111 B CN 114025111B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a comparison circuit which is applied to a CMOS image sensor and comprises a first comparator, a second comparator, a switch unit and a pre-judging logic unit, wherein the other end of the switch unit is connected with working voltage and is used for controlling the first comparator to enter an on state or an off state, a first input end of the pre-judging logic unit is connected with an output end of the first comparator, a second input end of the pre-judging logic unit is connected with an output end of the second comparator and is used for receiving a first comparison signal and a second comparison signal, and a switch control signal for controlling the switch unit to be turned on or off is output according to the first comparison signal and the second comparison signal, so that the first comparator is switched between the on state and the off state without being in the on state in real time, the power consumption of the first comparator is reduced, and the power consumption of the comparison circuit is reduced. The invention also provides a reading circuit and an image sensor.
Description
Technical Field
The present invention relates to the field of image sensors, and more particularly, to a comparison circuit, a readout circuit, and an image sensor.
Background
In a conventional CMOS image sensor (CMOS image sensor, CIS) structure, the power consumption of a single-integration analog-to-digital conversion circuit (Single Slope Analog-to-Digital Converter, SS-ADC) mainly comes from the quiescent current of a comparator, and the SS-ADC is a readout circuit of the CIS. In order to ensure the speed and accuracy of the analog-to-digital conversion, the quiescent current of the comparator is about 5 μa, and the comparator is always on during CIS operation. If the specification of the CIS processed image is 1000 columns and 1000 rows, i.e., 100 ten thousand pixels, there are 1000 columns of SS-ADCs, and the total quiescent current of the comparator is 5mA. If 800 ten thousand pixels are reached, there are 4000 columns of SS-ADCs and the total quiescent current of the comparator will reach 20mA. For low power consumption applications, a quiescent current of 20mA may cause excessive power consumption, so that the application of CIS is greatly limited.
Therefore, it is necessary to provide a novel comparing circuit, a readout circuit and an image sensor to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a comparison circuit, a reading circuit and an image sensor, which are used for reducing power consumption.
To achieve the above object, the comparison circuit of the present invention is applied to a CMOS image sensor, comprising:
a first comparator for receiving a pixel signal and a first ramp signal to output a first comparison signal as an output signal of the comparison circuit;
the second comparator is a dynamic comparator and is used for receiving the pixel signal and the second ramp signal to output a second comparison signal, wherein the first ramp signal lags behind the second ramp signal by a threshold time, and the signal range, slope and potential of the first ramp signal are identical to those of the second ramp signal;
the switch unit is characterized in that one end of the switch unit is connected with the working voltage end of the first comparator, the other end of the switch unit is connected with the working voltage and is used for controlling the first comparator to enter an on state or an off state, and the grounding end of the first comparator is grounded; and
the first input end of the pre-judging logic unit is connected with the output end of the first comparator, and the second input end of the pre-judging logic unit is connected with the output end of the second comparator and is used for receiving the first comparison signal and the second comparison signal so as to output a switch control signal for controlling the switch unit to be turned on or off according to the first comparison signal and the second comparison signal.
The comparison circuit has the beneficial effects that: the second comparator is a dynamic comparator and is used for receiving the pixel signal and the second ramp signal to output a second comparison signal, one end of the switch unit is connected with the working voltage end of the first comparator, the other end of the switch unit is connected with the working voltage end and is used for controlling the first comparator to enter an on state or an off state, the grounding end of the first comparator is grounded, the first input end of the pre-judging logic unit is connected with the output end of the first comparator, the second input end of the pre-judging logic unit is connected with the output end of the second comparator and is used for receiving the first comparison signal and the second comparison signal to output a switch control signal for controlling the switch unit to be turned on or off according to the first comparison signal and the second comparison signal, so that the first comparator is switched between the on state and the off state without being in the on state in real time, and the power consumption of the first comparator is reduced, and the power consumption of a comparison circuit is further reduced.
Optionally, the pre-judgment logic unit is a combinational logic circuit.
The invention also provides a readout circuit applied to a CMOS image sensor, comprising:
the comparison circuit, and
and the counter is connected with the output end of the first comparator and is used for outputting a digital signal.
The reading circuit has the beneficial effects that: the power consumption of the comparison circuit is reduced, and the power consumption of the reading circuit is further reduced.
The present invention also provides an image sensor including:
the pixel array unit is used for outputting pixel signals after sensitization;
the row selection decoding driving unit is connected with the pixel array unit and used for driving the pixel array unit;
the device comprises a ramp wave generation unit, a first signal generation unit and a second signal generation unit, wherein the ramp wave generation unit is used for generating a first ramp wave signal and a second ramp wave signal, the first ramp wave signal lags behind the second ramp wave signal by a threshold time, and the signal range, slope and potential of the first ramp wave signal are identical to the signal range, slope and potential of the second ramp wave signal;
at least one readout circuit connected to the pixel array unit and the ramp wave generating unit;
an output signal processing unit connected to the readout circuit to convert the digital signal into an image and output the image;
and the time sequence control unit is connected with the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit and is used for sending clock signals to the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit.
The beneficial effects of the image sensor are as follows: the power consumption of the readout circuitry and thus the image sensor is reduced.
Optionally, the pixel array unit includes at least one pixel unit, the pixel unit includes a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a photodiode, the drain electrode of the first NMOS is connected to the operating voltage, the source electrode of the first NMOS is connected to the gate electrode of the second NMOS and the drain electrode of the third NMOS, the gate electrode of the first NMOS is used for receiving a first control signal, the source electrode of the third NMOS is connected to the cathode of the photodiode, the gate electrode of the third NMOS is used for receiving a second control signal, the anode of the photodiode is grounded, the drain electrode of the second NMOS is connected to the operating voltage, the source electrode of the second NMOS is connected to the drain electrode of the fourth NMOS, the gate electrode of the fourth NMOS is used for receiving a first control signal, and the source electrode of the fourth NMOS is used for outputting a pixel signal. The beneficial effects are that: and the light sensing is convenient to output pixel signals.
Optionally, the pixel array unit further includes at least one column output line, where the column output lines are connected to the readout circuits in a one-to-one correspondence, and one column output line is connected to at least one pixel unit to receive the pixel signal from the pixel unit. The beneficial effects are that: the readout circuitry is facilitated to receive the pixel signals from the pixel cells.
Drawings
FIG. 1 is a schematic diagram of an image sensor according to the present invention;
FIG. 2 is a schematic circuit diagram of a pixel unit according to some embodiments of the invention;
FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention;
FIG. 4 is a schematic circuit diagram of a readout circuit according to some embodiments of the present invention;
fig. 5 is a timing diagram of an image sensor according to some embodiments of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
In view of the problems of the prior art, embodiments of the present invention provide an image sensor. Referring to fig. 1, the image sensor 100 includes a pixel array unit 101, a row selection decoding driving unit 103, a ramp wave generating unit 104, at least one readout circuit 102, an output signal processing unit 105, and a timing control unit 106.
Referring to fig. 1, the pixel array unit 101 is configured to output a pixel signal after sensing light; the row selection decoding driving unit 103 is connected with the pixel array unit 101 and is used for driving the pixel array unit 101; the ramp generating unit 104 is configured to generate a first ramp signal and a second ramp signal, where the first ramp signal lags behind the second ramp signal by a threshold time, and a signal range, a slope, and a potential of the first ramp signal are identical to a signal range, a slope, and a potential of the second ramp signal; the readout circuit 102 is connected to the pixel array unit 101 and the ramp wave generation unit 104; the output signal processing unit 105 is connected to the readout circuit 102 to convert the digital signal into an image and output; the timing control unit 106 is connected to the row selection decoding driving unit 103, the ramp wave generating unit 104, the readout circuit 102, and the output signal processing unit 105, and is configured to transmit clock signals to the row selection decoding driving unit 103, the ramp wave generating unit 104, the readout circuit 102, and the output signal processing unit 105. The pixel array unit 101 includes at least one pixel unit 1011, the row selection decoding driving unit 103, the ramp wave generating unit 104, the output signal processing unit 105 and the timing control unit 106 are all known in the art, and will not be described in detail herein.
FIG. 2 is a schematic circuit diagram of a pixel cell according to some embodiments of the invention. Referring to fig. 2, the pixel unit 1011 includes a first NMOS tube 10111, a second NMOS tube 10112, a third NMOS tube 10113, a fourth NMOS tube 10114, and a photodiode 10115, wherein a drain electrode of the first NMOS tube 10114 is connected to an operating voltage, a source electrode of the first NMOS tube 10111 is connected to a gate electrode of the second NMOS tube 10112 and a drain electrode of the third NMOS tube 10113, a gate electrode of the first NMOS tube 10111 is used for receiving a first control signal, a source electrode of the third NMOS tube 10113 is connected to a cathode electrode of the photodiode 10115, a gate electrode of the third NMOS tube 10113 is used for receiving a second control signal, an anode electrode of the photodiode 10115 is grounded, a drain electrode of the second NMOS tube 10114 is connected to an operating voltage, a source electrode of the second NMOS tube 10112 is connected to a drain electrode of the fourth NMOS tube 10114, a gate electrode of the fourth NMOS tube 10114 is used for receiving a third control signal, and a source electrode of the fourth NMOS tube 10114 is used for outputting a pixel signal.
In some embodiments, the pixel array unit further includes at least one column output line, the column output line being connected to the readout circuit in a one-to-one correspondence, one of the column output lines being connected to at least one of the pixel units to receive the pixel signal from the pixel unit. Specifically, the column output line is connected to the source of the fourth NMOS transistor to receive the pixel signal from the pixel unit.
FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention. Referring to fig. 2 and 3, rst denotes a reset stage of the pixel unit 1011, exp denotes an exposure stage of the pixel unit 1011, read denotes a signal Read stage of the pixel unit 1011, SEL denotes a third control signal applied to the gate of the fourth NMOS transistor 10114, RX denotes a first control signal applied to the gate of the first NMOS transistor 10111, and TX denotes a second control signal applied to the gate of the third NMOS transistor 10113.
Referring to fig. 2 and 3, the third control signal SEL maintains a low level, the first control signal RX maintains a high level, and the second control signal TX transitions from a high level to a low level while the pixel unit 1011 is in the reset stage. The first control signal RX and the second control signal TX are both high-point flat, the first NMOS transistor 10111 and the third NMOS transistor 10113 are both turned on, and the potential of the floating node 10115 is pulled up to the working voltage VDD to complete the reset.
Referring to fig. 2 and 3, after both the first control signal RX and the second control signal TX are turned to low level, the pixel unit 1011 enters the exposure stage from the reset stage, the third control signal SEL maintains low level, the first control signal RX maintains low level, and the second control signal TX maintains low level. The first control signal RX and the second control signal TX are both low-point flat, the first NMOS tube 10111 and the third NMOS tube 10113 are both turned off, and the photodiode 10115 senses light and generates photoelectrons in proportion to illumination intensity.
Referring to fig. 2 and 3, after the third control signal SEL is changed from low level to high level, the fourth NMSO tube 10114 is turned on, the pixel unit 1011 enters the signal reading stage from the exposure stage, the first control signal RX is changed from low level to high level to reset the floating node 10118, at this time, the second NMOS tube 10112 is controlled by the potential of the floating node, and the source electrode of the fourth NMOS tube 10114 outputs a first reset potential, and then the first control signal RX is changed from high level to low level; the second control signal TX changes from low level to high level, the photoelectrons in the photodiode 10115 are transferred to the floating node 10118, at this time, the second NMOS transistor 10112 is controlled by the potential of the floating node 10118, and the source of the fourth NMOS transistor 10114 outputs a second reset potential, and then the second control signal TX changes from high level to low level.
Fig. 4 is a circuit schematic of a readout circuit according to some embodiments of the invention. Referring to fig. 4, the readout circuit 102 includes a comparison circuit 1021 and a counter 1022, where the comparison circuit 1021 includes a first comparator 10211, a second comparator 10212, a switch unit 10213, and a pre-determination logic unit 10214, where a positive input terminal of the first comparator 10211 is connected to the same column output line as a positive input terminal of the second comparator 10212 to receive a pixel signal, a negative input terminal of the first comparator 10211 is connected to the ramp generating unit to receive the first ramp signal, a negative input terminal of the second comparator 10212 is connected to the ramp generating unit to receive the second ramp signal, one terminal of the switch unit 10213 is connected to an operating voltage terminal of the first comparator 10211, another terminal of the switch unit 10213 is connected to an operating voltage to control the first comparator 10211 to enter an on state or an off state, a ground terminal of the first comparator 11 is connected to ground, a negative input terminal of the pre-determination unit 10211 is connected to the first comparator 10212 to the first comparator output terminal of the first comparator 10211 to the second comparator output signal, and the switch unit 10213 is connected to the first comparator output terminal of the first comparator 10211 to the first comparator output signal. The second comparator 10212 is a dynamic comparator, the first comparator 10211 is a common comparator in a CMOS image sensor, and the pre-determination logic unit 10214 may be implemented by any circuit, such as a combinational logic circuit, or by computer program control, without any limitation.
Fig. 5 is a timing diagram of an image sensor according to some embodiments of the invention. Referring to fig. 2, 4 and 5, sel represents a third control signal applied to the gate of the fourth NMOS 10114, RX represents a first control signal applied to the gate of the first NMOS 10111, TX represents a second control signal applied to the gate of the third NMOS 10113, rst_cm represents a reset control signal of the first comparator 10211, RAMP represents the first RAMP signal, P-RAMP represents the second RAMP signal, pix_out represents a pixel signal, cm_out represents the first comparison signal, pcm_out represents the second comparison signal, cm_en represents a switch control signal, CNT represents a digital signal, VR represents a second RAMP stage, VS represents a hysteresis threshold time of the first RAMP signal with respect to the second RAMP signal, Δtg1 represents a time interval from a low level to a high level of the switch control signal, tr is the switch-on time interval from the low level to the high level of the switch control signal, cm_out represents a time interval from a high level to a high level of the switch signal, cm_out represents a time interval from a high level to a low level of the switch signal to a high level of the switch signal 102, cm_en represents a continuous time interval from a high level to a high level of the switch signal 102, v is the switch-on time of the switch-off state of the first comparator 11, v represents a time interval is the switch-on time of the switch signal 102, v represents a time interval is a high signal, v represents a time of the switch signal is a high, and the high time phase is a high time of the switch signal is on time, and the high time phase is a high time phase is continuously time, and the high time phase is continuously time, delta t3 represents an interval time from the low level to the high level of the first comparison signal to the low level of the switch control signal in the first ramp stage, delta t4 represents an interval time from the low level to the high level of the first comparison signal in the second ramp stage to the low level of the switch control signal, t1 represents a count time of the counter in the first ramp stage, and t2 represents a count time of the counter in the second ramp stage.
In some embodiments, referring to fig. 4 and 5, the second comparator 10212 compares the P-RAMP with pix_out, when the P-RAMP is lower than pix_out, the pcm_out output by the second comparator 10212 changes from low level to high level, and the pre-determination logic unit 10214 changes the cm_en output by the pre-determination logic unit from low level to high level after a delay Δt1, so as to control the switch unit 10213 to be turned on, so that the first comparator 10211 enters the on state;
the RAMP is delayed from the P-RAMP, after the first comparator 10211 enters an on state in the first RAMP stage, the first comparator 10211 compares the RAMP with the pix_out, when the RAMP is lower than the pix_out, the cm_out output by the first comparator 10211 changes from low level to high level, the pre-judging logic unit 10214 changes from high level to low level after delaying the time of Δt3, so as to control the switch unit 10213 to turn off, so that the first comparator 10211 enters an off state, and the first comparator 10211 maintains the on state for a time tr1 in the first RAMP stage;
in the first RAMP stage, the counter starts counting when RAMP falls, and stops counting when cm_out output from the first comparator 10211 changes from low level to high level, and counts as a first count value.
In some embodiments, referring to fig. 4 and 5, the second comparator 10212 compares the P-RAMP with pix_out, when the P-RAMP is lower than pix_out, the pcm_out output by the second comparator 10212 changes from low level to high level, and the pre-determination logic unit 10214 changes the cm_en output by the pre-determination logic unit from low level to high level after a delay Δt2, so as to control the switch unit 10213 to be turned on, so that the first comparator 10211 enters the on state;
the RAMP is delayed from the P-RAMP, after the first comparator 10211 enters an on state in the second RAMP stage, the first comparator 10211 compares the RAMP with the pix_out, when the RAMP is lower than the pix_out, the cm_out output by the first comparator 10211 changes from low level to high level, the pre-judging logic unit 10214 changes from high level to low level after delaying the time of Δt4, so as to control the switch unit 10213 to turn off, so that the first comparator 10211 enters an off state, and the first comparator 10211 maintains the on state for a time tr2 in the second RAMP stage;
in the second RAMP stage, the counter starts counting when RAMP falls, and stops counting when cm_out output from the first comparator 10211 changes from low level to high level, and counts as a second count value.
In some embodiments, the counter subtracts the first count value from the second count value to obtain a digital signal.
Referring to fig. 4 and 5, the second comparator 10212 is always on, and since the second comparator 10212 is a dynamic comparator, no static current is consumed, and only dynamic current is generated during inversion, the average current is small nA-stage, and therefore, can be ignored.
Referring to fig. 4 and 5, the first comparator 10211 is controlled by the switching unit 10213 to be in an on state or an off state, the switching unit 10213 is controlled by the cm_en, that is, when the cm_en is at a high level, the switching unit 10213 is turned on, the first comparator 10211 is in an on state, the duration of the high level of the cm_en is the sum of tr1 and tr2, the sum of tr1 and tr2 occupies about 1/10 of one period of the readout circuit, and the first comparator in the prior art is always in an on state and occupies the whole period of the readout circuit, so the power consumption of the readout circuit in the present application is 10% of the power consumption of the prior art.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (6)
1. A comparison circuit for use in a CMOS image sensor, comprising:
a first comparator for receiving a pixel signal and a first ramp signal to output a first comparison signal as an output signal of the comparison circuit;
the second comparator is a dynamic comparator and is used for receiving the pixel signal and the second ramp signal to output a second comparison signal, wherein the first ramp signal lags behind the second ramp signal by a threshold time, and the signal range, slope and potential of the first ramp signal are identical to those of the second ramp signal;
the switch unit is characterized in that one end of the switch unit is connected with the working voltage end of the first comparator, the other end of the switch unit is connected with the working voltage and is used for controlling the first comparator to enter an on state or an off state, and the grounding end of the first comparator is grounded; and
the first input end of the pre-judging logic unit is connected with the output end of the first comparator, and the second input end of the pre-judging logic unit is connected with the output end of the second comparator and is used for receiving the first comparison signal and the second comparison signal so as to output a switch control signal for controlling the switch unit to be turned on or off according to the first comparison signal and the second comparison signal.
2. The comparison circuit of claim 1, the pre-determination logic unit being a combinational logic circuit.
3. A readout circuit for use in a CMOS image sensor, comprising:
a comparison circuit as claimed in claim 1 or 2, and
and the counter is connected with the output end of the first comparator and is used for outputting a digital signal.
4. An image sensor, comprising:
the pixel array unit is used for outputting pixel signals after sensitization;
the row selection decoding driving unit is connected with the pixel array unit and used for driving the pixel array unit;
the device comprises a ramp wave generation unit, a first signal generation unit and a second signal generation unit, wherein the ramp wave generation unit is used for generating a first ramp wave signal and a second ramp wave signal, the first ramp wave signal lags behind the second ramp wave signal by a threshold time, and the signal range, slope and potential of the first ramp wave signal are identical to the signal range, slope and potential of the second ramp wave signal;
at least one readout circuit according to claim 3, connected to the pixel array unit and the ramp wave generating unit;
an output signal processing unit connected to the readout circuit to convert the digital signal into an image and output the image;
and the time sequence control unit is connected with the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit and is used for sending clock signals to the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit.
5. The image sensor of claim 4, wherein the pixel array unit comprises at least one pixel unit, the pixel unit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, and a photodiode, a drain electrode of the first NMOS tube is connected to an operating voltage, a source electrode of the first NMOS tube is connected to a gate electrode of the second NMOS tube and a drain electrode of the third NMOS tube, a gate electrode of the first NMOS tube is used for receiving a first control signal, a source electrode of the third NMOS tube is connected to a cathode of the photodiode, a gate electrode of the third NMOS tube is used for receiving a second control signal, an anode of the photodiode is grounded, a drain electrode of the second NMOS tube is connected to an operating voltage, a source electrode of the second NMOS tube is connected to a drain electrode of the fourth NMOS tube, a gate electrode of the fourth NMOS tube is used for receiving the first control signal, and a source electrode of the fourth NMOS tube is used for outputting the pixel signal.
6. The image sensor of claim 5, wherein the pixel array unit further comprises at least one column output line, the column output line being connected in one-to-one correspondence with the readout circuit, one of the column output lines being connected to at least one of the pixel units to receive the pixel signal from the pixel unit.
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