CN115379146B - Reading circuit, reading method and image sensor - Google Patents
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Abstract
The invention provides a reading circuit, a reading method and an image sensor, wherein the reading circuit comprises the following components: the device comprises a sampling module, a signal comparison module and a counting module; the sampling module comprises a first sampling unit and a second sampling unit; one end of the first sampling unit and one end of the second sampling unit are respectively connected with the pixel units; the other end of the first sampling unit and the other end of the second sampling unit are respectively connected with the signal comparison module; the counting module is connected with the signal comparison module, and the counting module obtains a comparison result output by the signal comparison module. The switching period of the readout circuit provided by the invention is started when the ramp signal is smaller than the reset signal and ended when the ramp signal is smaller than the integral signal, compared with the prior art, the time length corresponding to about twice VR stage is saved, namely the switching period of the readout circuit is effectively shortened.
Description
Technical Field
The invention is mainly applied to the field of integrated circuit design, and particularly relates to a reading circuit, a reading method and an image sensor.
Background
CMOS Image Sensors (CIS) have been widely used in imaging fields such as video, monitoring, industrial manufacturing, automobiles, home appliances, and the like. In recent years, the application requirements for CIS have been increasing, so how to achieve high output frame rate with high resolution requirements has become one of the most important research subjects of CIS. The main stream readout circuit structure of the CIS is a readout circuit mainly comprising a column-level monoclinic analog-to-digital converter (SS-ADC) so as to ensure that the CIS has enough conversion precision and speed under reasonable power consumption. The most important disadvantage of this architecture is that the conversion period increases exponentially with increasing ADC resolution, making it difficult to achieve high frame rates at high resolution. For this reason, a method needs to be found to shorten the conversion period of SS-ADC.
The conventional SS-ADC uses a comparator as a basic unit, and performs two comparisons on a reset signal and an integral signal of a pixel respectively to serve as a basis for counting by the counter, so that the whole conversion process needs to include conversion stages of the two signals.
Therefore, the invention provides a reading circuit, a reading method and an image sensor, which are beneficial to improving the frame rate of data output by improving the reading circuit of the traditional SS-ADC so as to effectively shorten the conversion period of the reading circuit.
Disclosure of Invention
The invention provides a reading circuit, a reading method and an image sensor, which are used for solving the problems that the traditional reading circuit has longer conversion period and affects the realization of high frame rate under high resolution.
In a first aspect, the present invention provides a readout circuit comprising: the device comprises a sampling module, a signal comparison module and a counting module; the sampling module comprises a first sampling unit and a second sampling unit; one end of the first sampling unit and one end of the second sampling unit are respectively connected with a pixel unit, and the pixel unit is sampled; the other end of the first sampling unit and the other end of the second sampling unit are respectively connected with the signal comparison module, the signal comparison module obtains the output of the first sampling unit, the output of the second sampling unit and a slope signal, and the signal comparison module is used for comparing the output of the first sampling unit with the slope signal and comparing the output of the second sampling unit with the slope signal; the counting module is connected with the signal comparison module, and the counting module obtains a comparison result output by the signal comparison module; the ramp signal is gradually reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit; the ramp signal continues to decrease, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, wherein the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit.
The beneficial effects are that: compared with the conversion period of the existing readout circuit, the conversion period of the readout circuit provided by the invention has the advantages that the time period corresponding to about twice VR stage is saved, namely the conversion period of the readout circuit is effectively shortened, and the frame rate of data output is improved.
Optionally, the readout circuit further includes: a switching circuit including a first switch, a second switch, a third switch, and a fourth switch; one end of the first switch is respectively connected with one end of the second switch and the slope generator, and the other end of the first switch is respectively connected with one end of the signal comparison module and one end of the third switch; the first switch and the second switch are used for receiving the ramp signal and transmitting the ramp signal to the signal comparison module; the other end of the second switch is respectively connected with one end of the fourth switch and the signal comparison module; the other end of the third switch is respectively connected with the signal comparison module and the other end of the first sampling unit; the other end of the fourth switch is respectively connected with the signal comparison module and the other end of the second sampling unit. The beneficial effects are that: the first sampling unit, the second sampling unit and the signal comparison module are connected through the switch circuit, and signal transmission among the first sampling unit, the second sampling unit and the signal comparison module can be realized by controlling the conduction state of the switch circuit.
Optionally, the signal comparison module includes: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a first P-type transistor, and a second P-type transistor; the grid electrode of the first N-type transistor is respectively connected with the other end of the first switch and one end of the third switch, the source electrode of the first N-type transistor is respectively connected with the source electrode of the second N-type transistor and the drain electrode of the fifth N-type transistor, and the drain electrode of the first N-type transistor is respectively connected with the drain electrode of the third N-type transistor, the grid electrode of the first P-type transistor, the grid electrode of the second P-type transistor and the drain electrode of the first P-type transistor; the drain electrode of the second N-type transistor is respectively connected with the drain electrode of the second P-type transistor and the drain electrode of the fourth N-type transistor, and the drain electrodes of the second N-type transistor, the second P-type transistor and the fourth N-type transistor are connected with the counting module; the source electrode of the third N-type transistor is connected with the drain electrode of the sixth N-type transistor and the source electrode of the fourth N-type transistor; the grid electrode of the fourth N-type transistor is respectively connected with the other end of the fourth switch and the other end of the second sampling unit; the source electrode of the fifth N-type transistor is grounded, the source electrode of the sixth N-type transistor is grounded, the grid electrode of the fifth N-type transistor and the grid electrode of the sixth N-type transistor are used for receiving bias voltages, and the bias voltages are used for providing first bias currents for the fifth N-type transistor and the sixth N-type transistor; and the source electrode of the first P-type transistor is connected with a power supply, and the source electrode of the second P-type transistor is connected with the power supply.
Optionally, the readout circuit further comprises a feedback module, and the signal comparison module is connected with the counting module through the feedback module; one end of the feedback module is respectively connected with the drain electrode of the second N-type transistor, the drain electrode of the second P-type transistor and the drain electrode of the fourth N-type transistor, and the other end of the feedback module is connected with the counting module; the feedback module acquires the output of the signal comparison module, the enabling signal of the slope generator and the enabling signal of the feedback module, and outputs a switch control signal to the switch circuit according to the output of the signal comparison module, the enabling signal of the slope generator and the enabling signal of the feedback module, wherein the switch control signal is used for controlling the working state of the switch circuit; the feedback module is further configured to convert a comparison result between the output of the first sampling unit and the ramp signal into a first digital signal, and convert a comparison result between the output of the second sampling unit and the ramp signal into a second digital signal; the counting module is used for starting counting when one of the first digital signal and the second digital signal changes, and stopping counting when the other of the first digital signal and the second digital signal changes. The beneficial effects are that: the switch control signal output by the feedback module can realize the control of the working state of the switch circuit.
Optionally, the first sampling unit includes a fifth switch and a first capacitor, and the second sampling unit includes a sixth switch and a second capacitor; one end of the fifth switch is connected with the pixel unit, the other end of the fifth switch is connected with the upper-stage plate of the first capacitor, and the lower-stage plate of the first capacitor is grounded; the upper plate of the first capacitor is also respectively connected with the other end of the third switch and the grid electrode of the second N-type transistor; one end of the sixth switching circuit is connected with the pixel unit, the other end of the sixth switching circuit is connected with an upper-stage plate of the second capacitor, and a lower-stage plate of the second capacitor is grounded; the upper plate of the second capacitor is also respectively connected with the other end of the fourth switch and the grid electrode of the fourth N-type transistor. The beneficial effects are that: the design is simple and feasible, and components are saved.
Optionally, the bias module further includes a bias voltage providing unit connected to the gate of the fifth N-type transistor and the gate of the sixth N-type transistor, respectively, to provide the bias voltage to the gate of the fifth N-type transistor and the gate of the sixth N-type transistor.
Optionally, the readout circuit further includes a ramp generator, where the ramp generator is connected to one end of the first switch and one end of the second switch respectively.
Optionally, the first N-type transistor, the second N-type transistor, the third N-type transistor, and the fourth N-type transistor are N-type transistors having a consistent ratio of width to length. The beneficial effects are that: the design is convenient to obtain materials, replace and study the problematic devices.
Optionally, the fifth N-type transistor and the sixth N-type transistor include a current source circuit.
Optionally, the first P-type transistor and the second P-type transistor comprise P-type transistor active loads.
Optionally, the first switch, the second switch, the third switch and the fourth switch each comprise at least one switching transistor.
In a second aspect, the present invention provides an image sensor comprising: a pixel array formed of M columns of pixel cells, N readout circuits as in any one of the first aspects, M and N being positive integers; the output buses of the pixel units of each column in the pixel array are respectively connected with one readout circuit, the readout circuits are used for outputting counting results according to signals output by the pixel units, and the counting results are used for generating image information.
Optionally, the image sensor further includes: a decoding driving module and a time sequence control module; the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array; the time sequence control module is respectively connected with the decoding driving module, the time sequence control module and the readout circuit and is used for controlling the working time sequence of the decoding driving module, the time sequence control module and the readout circuit.
In a third aspect, the present invention provides a reading method of a readout circuit, including: providing a readout circuit according to any one of the first aspects; the first sampling unit and the second sampling unit sample the pixel units respectively to acquire a reset signal and an integral signal; the signal comparison module respectively acquires the reset signal, the integral signal and the slope signal, and compares the reset signal with the slope signal and compares the integral signal with the slope signal; the counting module obtains a comparison result output by the signal comparison module; the ramp signal is gradually reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit; the ramp signal continues to decrease, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, wherein the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit.
Optionally, the first sampling unit and the second sampling unit sample the pixel unit respectively to obtain a reset signal and an integrated signal, including: the pixel unit sequentially outputs a reset signal and an integral signal under the action of the second bias current; the first switch and the second switch are changed from an off state to an on state; the fifth switch circuit is changed from an off state to an on state, and the first sampling capacitor samples the reset signal to an upper plate of the first sampling capacitor; the fifth switching circuit is changed from an on state to an off state, the sixth switching circuit is changed from an off state to an on state, and the second sampling capacitor samples the integrated signal to an upper plate of the second sampling capacitor.
Optionally, the signal comparison module obtains the reset signal, the integrated signal and the ramp signal, and the signal comparison module compares the reset signal with the ramp signal and compares the integrated signal with the ramp signal; the counting module acquires a comparison result output by the signal comparison module, the ramp signal is gradually reduced, and when the comparison result acquired by the counting module is changed from a state that the ramp signal is equal to a reset signal to a state that the ramp signal is smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit; the ramp signal is continuously reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, and the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit and comprises the following components: the second switch is changed from an on state to an off state, the fourth switch is changed from an off state to an on state, the grid electrode of the first N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the second N-type transistor is conducted with the upper plate of the first sampling capacitor to acquire the reset signal; the first N-type transistor and the branch where the second N-type transistor are located compare the ramp signal with the reset signal, when the ramp signal is higher than the reset signal, a first comparison result output by the signal comparison module is low level, the first comparison result is converted into a first digital signal through the synchronous feedback circuit, the first digital signal is 0, the first comparison result is equal to the product of a first coefficient and a first difference value, and the first difference value is the difference value between the ramp signal and the reset signal; as the ramp signal gradually decreases, and when the ramp signal is equal to the reset signal and becomes smaller than the reset signal, the first comparison result output by the signal comparison module is high level, the first comparison result is converted into a second digital signal through the synchronous feedback circuit, the second digital signal is 1, and the counting module receives the second digital signal and starts counting; the synchronous feedback circuit controls the first switch and the fourth switch to be changed from an on state to an off state through the switch control signal, the second switch and the third switch are changed from the off state to the on state, the grid electrode of the third N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the fourth N-type transistor is conducted with the upper plate of the second sampling capacitor to acquire the integral signal; the branch circuit where the third N-type transistor and the fourth N-type transistor are located compares the slope signal with the integral signal, and when the slope signal is higher than the integral signal, a second comparison result output by the signal comparison module is high level and is converted into the second digital signal through the synchronous feedback circuit; as the ramp signal gradually decreases, and when the ramp signal is equal to the integral signal and the ramp signal is smaller than the integral signal, the second comparison result output by the signal comparison module is low level and is converted into the first digital signal through the synchronous feedback circuit, and the counting module receives the first digital signal and stops counting; the second comparison result is equal to the product of the first coefficient and a second difference value, wherein the second difference value is the difference value between the ramp signal and the integral signal; and the counting module outputs a counting result.
Optionally, after the counting module outputs the counting result, the method further includes: the first switch is changed from an off state to an on state, the second switch is kept in the on state, the third switch is changed from the on state to the off state, and the fourth switch is kept in the off state, so that the readout circuit is restored to the state before the pixel unit output is acquired.
The advantageous effects concerning the above second to third aspects can be seen from the description in the above first aspect.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of a CIS standard four-tube pixel unit;
FIG. 2 is a schematic diagram of the operation sequence of a CIS standard four-tube pixel unit circuit;
fig. 3 is a schematic diagram of a CIS readout circuit;
fig. 4 is a schematic diagram showing an operation timing of a CIS readout circuit;
FIG. 5 is a schematic diagram of a readout circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a readout circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of another embodiment of a readout circuit according to the present invention;
FIG. 8 is a schematic diagram of a portion of another embodiment of a readout circuit according to the present invention;
FIG. 9 is a schematic diagram of a readout circuit according to another embodiment of the present invention;
FIG. 10 is a flowchart of a reading method of a readout circuit according to an embodiment of the present application;
fig. 11 is a schematic diagram of an operation timing embodiment of a readout circuit according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application are described below with reference to the accompanying drawings in the embodiments of the present application. In the description of embodiments of the application, the terminology used in the embodiments below is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless stated otherwise. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
Fig. 1 is a circuit structure of a CIS standard four-transistor pixel unit, which is commonly applied to a line exposure CIS, and is composed of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, an amplifying transistor Msf, and a line selection transistor Msel. The photodiode PD will sense light and generate photoelectrons proportional to the intensity of the light. The transfer transistor Mtg functions to transfer photoelectrons within the photodiode PD. When the TX signal is high, the pass transistor Mtg is turned on and transfers the photoelectrons from the photodiode PD to the floating node FD. The reset transistor Mrst functions to reset the potential of the floating node FD when the RX signal is high. The source follower Msf is an amplifying tube, when SEL is at high potential, the row selection transistor Msel is turned on, the source follower Msf, the row selection transistor Msel and a current source to ground form a path, and at this time, the source follower Msf follows the change of the FD potential of the floating node and is finally outputted from the output bus pix_out.
Fig. 2 is a diagram showing operation timings of the four-pipe pixel unit shown in fig. 1, which is divided into reset (Rst), exposure (Exp), and signal Read (Read). In Rst phase, the TX signal, RX signal is at "high" potential, both the pass transistor Mtg and the reset transistor Mrst are on, the floating point FD is reset and its potential is pulled high to the supply voltage VDD. After that, the RX signal and TX signal become low, enter the Exp stage, and floating PD senses and accumulates electrons. Then, in the Read phase, SEL is at "high" level, the RX signal is at "high" level first, after resetting the potential of the floating FD, the RX signal is pulled to "low" level again, and the TX signal is kept at "low" level, at this time, the source follower transistor Msf is controlled by the floating FD potential and outputs the reset potential VRST through the output bus pix_out. Thereafter, the TX signal is pulled to a "high" potential and the electrons on the photodiode PD are transferred to the floating-point FD, at which time the source follower transistor Msf is controlled by the potential of the floating-point FD and outputs the integrated potential VSIG through the output bus pix_out. The difference between VRST-VSIG is the analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted into digital quantities by an analog-to-digital converter (ADC) circuit and subtracted to obtain digital quantities actually corresponding to photoelectrons on the photodiode PD. If the ADC is 12 bits, the ADC reference voltage range is VREF, the final output is DOUT= (VRST-VSIG) ×2 12 /VREF。
Fig. 3 is a schematic diagram of a CIS readout circuit, which includes a pixel array, an ADC (comparator, counter), a ramp generator, a timing control module, a decoding driving module, and an output signal processing module. The pixel array is composed of a plurality of pixel units P as shown in FIG. 1. The pixel array is read out in a ROW-by-ROW manner, and the specific sequence is ROW (0), ROW (1), … … ROW (k-1) and ROW (k). And k is a positive integer. Each column in the pixel array is respectively connected with one output bus, and the output buses are respectively PIX_OUT (0), PIX_OUT (1), … PIX_OUT (n-1) and PIX_OUT (n). The output ends of the output buses are connected with the ADC module. The ADC module consists of a comparator and a counter, wherein the comparator compares an output pixel signal with a RAMP signal RAMP, and the comparison result determines the count value of the counter. The ADC module also judges the VRST and the VSIG potentials respectively and converts the VRST-VSIG difference value into digital quantity to output.
Fig. 4 shows the operation sequence of the CIS Read circuit shown in fig. 3, that is, the Read phase of the sequence shown in fig. 2. In the timing shown in fig. 4, the Read phase is entered, SEL is pulled to "high" potential, RX is at "high" potential, and the pixel unit is reset. Rst_cm is a comparator reset control signal, and rst_cm is also pulled to a "high" potential to put the comparators in all ADC modules into a reset state. Then RX, RST_CM changes from "high" to "low" and the ADC module enters normal operation. The working process of the ADC module consists of a comparison process and a counting process, firstly, when the RAMP potential starts to fall, the counter CNT starts to count, and when the comparator signal turns from low potential to high potential, the counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operation twice, i.e. as a reference of the ADC module, two ramp waves are generated. The first ramp phase (i.e. "VR" phase in fig. 4), the ADC module will determine and store the reset potential VRST, and the counter CNT will count during the time t1 and store the count value CN1 corresponding to the time t 1; in the second ramp phase (i.e. the "VS" phase of fig. 4), the ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 period during the t2 period. The final counter CNT will output a count difference Δcn=cn2-CN 1, corresponding to the difference amount of VSIG-VRST. The above sequence is the conventional SS-ADC conversion process.
In order to reduce the conversion period of the conventional SS-ADC conversion process, the present invention provides a readout circuit, as shown in fig. 5, comprising: a sampling module 501, a signal comparison module 502 and a counting module 503; the sampling module 501 includes a first sampling unit 5011 and a second sampling unit 5012; one end of the first sampling unit 5011 and one end of the second sampling unit 5012 are respectively connected with a pixel unit, and the pixel unit is sampled; the other end of the first sampling unit 5011 and the other end of the second sampling unit 5012 are respectively connected to the signal comparing module 502, the signal comparing module 502 obtains the output of the first sampling unit 5011, the output of the second sampling unit 5012, and a ramp signal, and the signal comparing module 502 is configured to compare the output of the first sampling unit 5011 with the ramp signal and the output of the second sampling unit 5012 with the ramp signal; the counting module 503 is connected with the signal comparing module 502, and the counting module 503 obtains a comparison result output by the signal comparing module 502; the ramp signal is gradually decreasing, and when the comparison result obtained by the counting module 503 is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module 503 starts counting, the reset signal corresponding to a larger one of the output of the first sampling unit 5011 and the output of the second sampling unit 5012; the ramp signal continues to decrease, and when the comparison result acquired by the counting module 503 changes from the ramp signal equal to the integration signal to the ramp signal smaller than the integration signal, the counting module 503 stops counting and outputs a counting result, the integration signal corresponding to the smaller one of the output of the first sampling unit 5011 and the output of the second sampling unit 5012. Optionally, the counting module is a counter.
Compared with the conversion period of the existing readout circuit, the conversion period of the readout circuit provided by the invention has the advantages that the time period corresponding to about twice VR stage is saved, namely the conversion period of the readout circuit is effectively shortened, and the frame rate of data output is improved.
In some embodiments, the readout circuitry further comprises: a switching circuit. The switch circuit 600 has a structure as shown in fig. 6, and includes a first switch K1, a second switch K2, a third switch K3, and a fourth switch K4; one end of the first switch K1 is respectively connected with one end of the second switch K2 and the RAMP generator RAMP, and the other end of the first switch K1 is respectively connected with one end of the signal comparison module and one end of the third switch K3; the first switch K1 and the second switch K2 are used for receiving the ramp signal and transmitting the ramp signal to the signal comparison module; the other end of the second switch K2 is respectively connected with one end of the fourth switch K4 and the signal comparison module; the other end of the third switch K3 is respectively connected with the signal comparison module and the other end RST of the first sampling unit; the other end of the fourth switch K4 is respectively connected with the signal comparison module and the other end SIG of the second sampling unit. The first sampling unit, the second sampling unit and the signal comparison module are connected through the switch circuit, and signal transmission among the first sampling unit, the second sampling unit and the signal comparison module can be realized by controlling the conduction state of the switch circuit.
In some embodiments, as shown in fig. 7, the signal comparison module 700 includes: a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a fourth N-type transistor N4, a fifth N-type transistor N5, a sixth N-type transistor N6, a first P-type transistor P1, and a second P-type transistor P2; the grid electrode of the first N-type transistor N1 is respectively connected with the other end of the first switch K1 and one end of the third switch K3, the source electrode of the first N-type transistor N1 is respectively connected with the source electrode of the second N-type transistor N2 and the drain electrode of the fifth N-type transistor N5, and the drain electrode of the first N-type transistor N1 is respectively connected with the drain electrode of the third N-type transistor N3, the grid electrode of the first P-type transistor P1, the grid electrode of the second P-type transistor P2 and the drain electrode of the first P-type transistor P1; the drain electrode of the second N-type transistor N2 is respectively connected with the drain electrode of the second P-type transistor P2 and the drain electrode of the fourth N-type transistor N4, and the drain electrode of the second N-type transistor N2, the drain electrode of the second P-type transistor P2 and the drain electrode of the fourth N-type transistor N4 are connected with the counting module; the source electrode of the third N-type transistor N3 is connected with the drain electrode of the sixth N-type transistor N6 and the source electrode of the fourth N-type transistor N4; the grid electrode of the fourth N-type transistor N4 is respectively connected with the other end of the fourth switch K4 and the other end SIG of the second sampling unit; the source electrode of the fifth N-type transistor N5 is grounded, the source electrode of the sixth N-type transistor N6 is grounded, the grid electrode of the fifth N-type transistor N5 and the grid electrode of the sixth N-type transistor N6 are used for receiving bias voltages, and the bias voltages are used for providing first bias currents for the fifth N-type transistor N5 and the sixth N-type transistor N6; the source of the first P-type transistor P1 is connected to the power supply VDD, and the source of the second P-type transistor P2 is connected to the power supply VDD.
In some embodiments, as shown in fig. 8, the readout circuit further includes a feedback module 800, and the signal comparison module is connected to the counting module through the feedback module 800; one end of the feedback module 800 is respectively connected with the drain electrode of the second N-type transistor N2, the drain electrode of the second P-type transistor P2 and the drain electrode of the fourth N-type transistor N4, and the other end of the feedback module 800 is connected with the counting module; the feedback module 800 obtains the output of the signal comparison module, the enable signal of the ramp generator, and the enable signal of the feedback module, and outputs a switch control signal to the switch circuit according to the output of the signal comparison module, the enable signal of the ramp generator, and the enable signal of the feedback module, where the switch control signal is used to control the working state of the switch circuit; the feedback module is further configured to convert a comparison result between the output of the first sampling unit and the ramp signal into a first digital signal, and convert a comparison result between the output of the second sampling unit and the ramp signal into a second digital signal; the counting module is used for starting counting when one of the first digital signal and the second digital signal changes, and stopping counting when the other of the first digital signal and the second digital signal changes. The switch control signal output by the feedback module can realize the control of the working state of the switch circuit.
In some embodiments, as shown in fig. 9, the readout circuit includes a bias current providing unit Is, where the bias current providing unit Is connected to the pixel unit and Is configured to provide a second bias current to the pixel unit, so that the pixel unit outputs under the effect of the second bias current. The first sampling unit comprises a fifth switch K5 and a first capacitor C1, and the second sampling unit comprises a sixth switch K6 and a second capacitor C2. One end of the fifth switch K5 is connected to the pixel unit, the other end of the fifth switch K5 is connected to the upper plate RST of the first capacitor C1, and the lower plate of the first capacitor is grounded; the upper plate RST of the first capacitor C1 is also respectively connected with the other end of the third switch K3 and the grid electrode of the second N-type transistor N2; one end of the sixth switching circuit K6 is connected with the pixel unit, the other end of the sixth switching circuit K6 is connected with an upper plate SIG of the second capacitor C2, and a lower plate of the second capacitor C2 is grounded; the upper plate SIG of the second capacitor C2 is further connected to the other end of the fourth switch K4 and the gate of the fourth N-type transistor N4, respectively. The design is simple and feasible, and components are saved.
In some embodiments, the bias module further includes a bias voltage providing unit connected to the gate of the fifth N-type transistor and the gate of the sixth N-type transistor, respectively, to provide the bias voltage to the gate of the fifth N-type transistor and the gate of the sixth N-type transistor.
In some embodiments, the readout circuit further comprises a ramp generator connected to one end of the first switch and one end of the second switch, respectively.
In some embodiments, the first N-type transistor, the second N-type transistor, the third N-type transistor, and the fourth N-type transistor are N-type transistors having a consistent ratio of width to length. The design is convenient to obtain materials, replace and study the problematic devices.
In some embodiments, the fifth N-type transistor and the sixth N-type transistor include current source circuits.
In some embodiments, the first P-type transistor and the second P-type transistor comprise a P-type transistor active load.
In some embodiments, the first switch, the second switch, the third switch, and the fourth switch each comprise at least one switching transistor, the switching transistors being switching MOS transistors.
Based on the readout circuit according to any one of the above embodiments, the present invention provides an image sensor, including: a pixel array formed by M columns of pixel units, N readout circuits according to any one of the embodiments above, where M and N are positive integers; the output buses of the pixel units of each column in the pixel array are respectively connected with one readout circuit, the readout circuits are used for outputting counting results according to signals output by the pixel units, and the counting results are used for generating image information.
In some embodiments, the image sensor further comprises: a decoding driving module and a time sequence control module; the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array; the time sequence control module is respectively connected with the decoding driving module, the time sequence control module and the readout circuit and is used for controlling the working time sequence of the decoding driving module, the time sequence control module and the readout circuit.
Based on the readout circuit according to any one of the foregoing embodiments, the present invention further provides a readout method of the readout circuit, where a flow of the readout method is shown in fig. 10, and the readout method includes:
S101: providing a readout circuit as in any one of the embodiments above;
s102: the first sampling unit and the second sampling unit sample the pixel units respectively to acquire a reset signal and an integral signal;
s103: the signal comparison module respectively acquires the reset signal, the integral signal and the slope signal, and compares the reset signal with the slope signal and compares the integral signal with the slope signal;
s104: the counting module obtains a comparison result output by the signal comparison module;
s105: the ramp signal is gradually reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit;
s106: the ramp signal continues to decrease, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, wherein the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit.
In some embodiments, the first sampling unit and the second sampling unit sample the pixel unit to obtain a reset signal and an integration signal, respectively, including: the pixel unit sequentially outputs a reset signal and an integral signal under the action of the second bias current; the first switch and the second switch are changed from an off state to an on state; the fifth switch circuit is changed from an off state to an on state, and the first sampling capacitor samples the reset signal to an upper plate of the first sampling capacitor; the fifth switching circuit is changed from an on state to an off state, the sixth switching circuit is changed from an off state to an on state, and the second sampling capacitor samples the integrated signal to an upper plate of the second sampling capacitor.
In some embodiments, the signal comparison module obtains the reset signal, the integrated signal, and a ramp signal, respectively, the signal comparison module compares the reset signal to the ramp signal, and compares the integrated signal to the ramp signal; the counting module acquires a comparison result output by the signal comparison module, the ramp signal is gradually reduced, and when the comparison result acquired by the counting module is changed from a state that the ramp signal is equal to a reset signal to a state that the ramp signal is smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit; the ramp signal is continuously reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, and the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit and comprises the following components: the second switch is changed from an on state to an off state, the fourth switch is changed from an off state to an on state, the grid electrode of the first N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the second N-type transistor is conducted with the upper plate of the first sampling capacitor to acquire the reset signal; the first N-type transistor and the branch where the second N-type transistor are located compare the ramp signal with the reset signal, when the ramp signal is higher than the reset signal, a first comparison result output by the signal comparison module is low level, the first comparison result is converted into a first digital signal through the synchronous feedback circuit, the first digital signal is 0, the first comparison result is equal to the product of a first coefficient and a first difference value, and the first difference value is the difference value between the ramp signal and the reset signal; as the ramp signal gradually decreases, and when the ramp signal is equal to the reset signal and becomes smaller than the reset signal, the first comparison result output by the signal comparison module is high level, the first comparison result is converted into a second digital signal through the synchronous feedback circuit, the second digital signal is 1, and the counting module receives the second digital signal and starts counting; the synchronous feedback circuit controls the first switch and the fourth switch to be changed from an on state to an off state through the switch control signal, the second switch and the third switch are changed from the off state to the on state, the grid electrode of the third N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the fourth N-type transistor is conducted with the upper plate of the second sampling capacitor to acquire the integral signal; the branch circuit where the third N-type transistor and the fourth N-type transistor are located compares the slope signal with the integral signal, and when the slope signal is higher than the integral signal, a second comparison result output by the signal comparison module is high level and is converted into the second digital signal through the synchronous feedback circuit; as the ramp signal gradually decreases, and when the ramp signal is equal to the integral signal and the ramp signal is smaller than the integral signal, the second comparison result output by the signal comparison module is low level and is converted into the first digital signal through the synchronous feedback circuit, and the counting module receives the first digital signal and stops counting; the second comparison result is equal to the product of the first coefficient and a second difference value, wherein the second difference value is the difference value between the ramp signal and the integral signal; and the counting module outputs a counting result.
In some embodiments, after the counting module outputs the counting result, further comprising: the first switch is changed from an off state to an on state, the second switch is kept in the on state, the third switch is changed from the on state to the off state, and the fourth switch is kept in the off state, so that the readout circuit is restored to the state before the pixel unit output is acquired.
In order to explain the reading method of the readout circuit provided by the present application in more detail, explanation is made here with reference to fig. 11. The pixel unit outputs a pixel signal pix_out under the bias of the bias current Is. After the pixel signal pix_out enters the reading phase, the SEL signal received by the pixel unit changes from low potential to high potential, and after the RX signal initiates a high pulse, the enable signal en_xo of the signal comparison module changes from low potential to high potential, so that the first switch K1 and the second switch K2 change from off state to on state, and the fifth switch circuit K5 also changes from low potential to high potential. The reset signal VRST of the pixel signal pix_out is sampled onto the upper plate RST of the first capacitor C1. The fifth switch circuit K5 is changed from an on state to an off state, the TX signal is changed from a low potential to a high potential, and the sixth switch circuit K6 is changed from an off state to an on state. The integrated signal VSIG of the pixel signal pix_out is sampled onto the upper plate SIG of the second capacitor C2. Then, the enable signal en_ramp of the RAMP generator is changed from low potential to high potential, the RAMP generator starts to formally output the RAMP signal RAMP, the second switch K2 is changed from on state to off state, the fourth switch K4 is changed from off state to on state, at this time, one input of the signal comparison module DAMP is connected to the upper plate SIG of the second capacitor C2, and the branches where the third N-type transistor N3 and the fourth N-type transistor N4 are located do not have amplification effect. The input of the signal comparison module DAMP is connected with the gates of the first N-type transistor N1 and the second N-type transistor N2 respectively to the slope generator and the upper plate RST of the first capacitor C1, so that the branches where the first N-type transistor N1 and the second N-type transistor N2 are located can compare the slope signal with the reset signal, when the slope signal VRAMP is higher than VRST, a first comparison result VO is output to be low potential, when the slope signal VRAMP is gradually reduced to be just smaller than the reset signal VRST, the first comparison result VO is changed from low potential to high potential, the digital signal DO corresponding to the first comparison result VO is also changed from 0 to 1, the counter starts to count, and the first comparison result VO can be written as follows: vo=gm·rout· (VRAMP-VRST), where gm·rout is a first coefficient, gm is a transconductance of the signal comparison module, rout is an output impedance of the signal comparison module, the first coefficient is a product of the transconductance of the signal comparison module and the output impedance, and VRAMP-VRST is a difference between a ramp signal VRAMP and a reset signal VRST.
At this time, the feedback module is controlled by the switch control signal SFB, so that the first switch K1 and the fourth switch K4 are turned from on to off, the second switch K2 and the third switch K3 are turned from off to on, and the gates of the first N-type transistor N1 and the second N-type transistor N2 are connected to the upper plate RST of the first capacitor C1 by one input of the signal comparison module DAMP, so that the branches where the first N-type transistor N1 and the second N-type transistor N2 are located do not have amplification effects. The input of the signal comparison module DAMP is connected with the gates of the third N-type transistor N3 and the fourth N-type transistor N4 respectively to the slope generator and the upper plate SIG of the second capacitor C2, so that the branches where the third N-type transistor N3 and the fourth N-type transistor N4 are located can compare the slope signal and the integral signal, when the slope signal VRAMP is higher than the integral signal VSIG, the second comparison result VO ' is output and kept at a high potential, when the slope signal VRAMP is gradually reduced to be just smaller than the integral signal VSIG, the second comparison result VO ' is changed from the high potential to the low potential, the digital signal DO corresponding to the second comparison result VO ' is also changed from 1 to 0, the counter stops counting, the first switch K1 is changed from the off state to the on state, the second switch K2 is kept at the on state, the third switch K3 is changed from the on state to the off state, and the fourth switch K4 is kept at the off state to the switch state of the initial reading stage. The second comparison result VO' may be written as: VO' =gm·rout· (VRAMP-VSIG), where gm·rout is a first coefficient, gm is a transconductance of the signal comparison module, rout is an output impedance of the signal comparison module, and the first coefficient is a product of the transconductance of the signal comparison module and the output impedance, VRAMP-VSIG is a difference between a ramp signal VRAMP and an integrated signal VSIG.
Finally, the enable signal en_xo of the feedback module and the enable signal en_ramp of the RAMP generator are both changed from high potential to low potential, the counter outputs a final count result CN3 (a digital quantity corresponding to the count period of t 3), CN3 is output as final DATA to the CIS system for subsequent processing, and the digital quantity corresponding to CN3 is the quantity of VO' -VO, that is, the quantity corresponding to the difference between VRST and VSIG. As can be seen from the working process, the proposed readout circuit can complete conversion of the VRST-VSIG difference value only by one slope counting stage, and compared with the traditional SS-ADC operation, the conversion time of the VRST stage is saved by about 2 times, the time required by the operation of the readout circuit is effectively shortened, and the CIS data output frame rate is improved. Taking 200-ten-thousand-pixel CIS as an example, to realize 30fps data output, one reading period is 30 mu s, the time required for various reset and signal establishment is about 5 mu s, and the time of two stages of VR and VS is 25 mu s. Typically, the VR is 1/4 to 1/3 of the VS, and the VR is 6.25 μs and the VS is 18.75 μs. The VR stage accounts for 20.83% of the entire readout timing period. The readout circuit provided by the invention can omit a VS stage, namely, can save more than 40% of time compared with the time consumed by one period of the traditional SS-ADC readout circuit.
The foregoing is merely a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited to this, and any changes or substitutions within the technical scope disclosed in the embodiment of the present application should be covered in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (17)
1. A readout circuit, comprising: the device comprises a sampling module, a signal comparison module and a counting module; the sampling module comprises a first sampling unit and a second sampling unit;
one end of the first sampling unit and one end of the second sampling unit are respectively connected with a pixel unit, and the pixel unit is sampled to acquire a reset signal and an integral signal;
the other end of the first sampling unit and the other end of the second sampling unit are respectively connected with the signal comparison module, the signal comparison module obtains the output of the first sampling unit, the output of the second sampling unit and a slope signal, and the signal comparison module is used for comparing the output of the first sampling unit with the slope signal and comparing the output of the second sampling unit with the slope signal;
The counting module is connected with the signal comparison module, and the counting module obtains a comparison result output by the signal comparison module;
the ramp signal is gradually reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit;
the ramp signal continues to decrease, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, wherein the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit.
2. The sensing circuit of claim 1, further comprising: a switching circuit including a first switch, a second switch, a third switch, and a fourth switch;
one end of the first switch is respectively connected with one end of the second switch and the slope generator, and the other end of the first switch is respectively connected with one end of the signal comparison module and one end of the third switch; the first switch and the second switch receive the ramp signal and transmit the ramp signal to the signal comparison module;
The other end of the second switch is respectively connected with one end of the fourth switch and the signal comparison module;
the other end of the third switch is respectively connected with the signal comparison module and the other end of the first sampling unit;
the other end of the fourth switch is respectively connected with the signal comparison module and the other end of the second sampling unit.
3. The sensing circuit of claim 2, wherein the signal comparison module comprises: a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a first P-type transistor, and a second P-type transistor;
the grid electrode of the first N-type transistor is respectively connected with the other end of the first switch and one end of the third switch, the source electrode of the first N-type transistor is respectively connected with the source electrode of the second N-type transistor and the drain electrode of the fifth N-type transistor, and the drain electrode of the first N-type transistor is respectively connected with the drain electrode of the third N-type transistor, the grid electrode of the first P-type transistor, the grid electrode of the second P-type transistor and the drain electrode of the first P-type transistor;
the drain electrode of the second N-type transistor is respectively connected with the drain electrode of the second P-type transistor and the drain electrode of the fourth N-type transistor, and the drain electrodes of the second N-type transistor, the second P-type transistor and the fourth N-type transistor are connected with the counting module;
The source electrode of the third N-type transistor is connected with the drain electrode of the sixth N-type transistor and the source electrode of the fourth N-type transistor;
the grid electrode of the fourth N-type transistor is respectively connected with the other end of the fourth switch and the other end of the second sampling unit;
the source electrode of the fifth N-type transistor is grounded, the source electrode of the sixth N-type transistor is grounded, the grid electrode of the fifth N-type transistor and the grid electrode of the sixth N-type transistor are used for receiving bias voltages, and the bias voltages are used for providing first bias currents for the fifth N-type transistor and the sixth N-type transistor;
and the source electrode of the first P-type transistor is connected with a power supply, and the source electrode of the second P-type transistor is connected with the power supply.
4. A readout circuit according to claim 3, further comprising a feedback module, the signal comparison module being connected to the counting module by the feedback module;
one end of the feedback module is respectively connected with the drain electrode of the second N-type transistor, the drain electrode of the second P-type transistor and the drain electrode of the fourth N-type transistor, and the other end of the feedback module is connected with the counting module;
the feedback module acquires the output of the signal comparison module, the enabling signal of the slope generator and the enabling signal of the feedback module, and outputs a switch control signal to the switch circuit according to the output of the signal comparison module, the enabling signal of the slope generator and the enabling signal of the feedback module, wherein the switch control signal is used for controlling the working state of the switch circuit;
The feedback module is further configured to convert a comparison result between the output of the first sampling unit and the ramp signal into a first digital signal, and convert a comparison result between the output of the second sampling unit and the ramp signal into a second digital signal;
the counting module is used for starting counting when one of the first digital signal and the second digital signal changes, and stopping counting when the other of the first digital signal and the second digital signal changes.
5. The sensing circuit of claim 3, wherein the first sampling unit comprises a fifth switch and a first capacitor, and the second sampling unit comprises a sixth switch and a second capacitor;
one end of the fifth switch is connected with the pixel unit, the other end of the fifth switch is connected with the upper-stage plate of the first capacitor, and the lower-stage plate of the first capacitor is grounded; the upper plate of the first capacitor is also respectively connected with the other end of the third switch and the grid electrode of the second N-type transistor;
one end of the sixth switching circuit is connected with the pixel unit, the other end of the sixth switching circuit is connected with an upper-stage plate of the second capacitor, and a lower-stage plate of the second capacitor is grounded; the upper plate of the second capacitor is also respectively connected with the other end of the fourth switch and the grid electrode of the fourth N-type transistor.
6. The readout circuit according to claim 5, further comprising a bias voltage supply unit that connects a gate of the fifth N-type transistor and a gate of the sixth N-type transistor, respectively, to supply the bias voltage to the gate of the fifth N-type transistor and the gate of the sixth N-type transistor.
7. The sensing circuit of claim 2, further comprising a ramp generator connected to one end of the first switch and one end of the second switch, respectively.
8. The sensing circuit of claim 3, wherein the first N-type transistor, the second N-type transistor, the third N-type transistor, and the fourth N-type transistor are N-type transistors having a consistent width to length ratio.
9. The sensing circuit of claim 8, wherein the fifth N-type transistor and the sixth N-type transistor comprise current source circuits.
10. The sensing circuit of claim 9, wherein the first P-type transistor and the second P-type transistor comprise a P-type transistor active load.
11. The sensing circuit of claim 2, wherein the first switch, the second switch, the third switch, and the fourth switch each comprise at least one switching transistor.
12. An image sensor, comprising: a pixel array consisting of M columns of pixel cells, N readout circuits according to any one of claims 1 to 11, said M and said N being both positive integers;
the output buses of the pixel units of each column in the pixel array are respectively connected with one readout circuit, the readout circuits are used for outputting counting results according to signals output by the pixel units, and the counting results are used for generating image information.
13. The image sensor of claim 12, further comprising: a decoding driving module and a time sequence control module;
the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array;
the time sequence control module is respectively connected with the decoding driving module, the time sequence control module and the readout circuit and is used for controlling the working time sequence of the decoding driving module, the time sequence control module and the readout circuit.
14. A method of reading a read circuit, comprising:
providing a sensing circuit according to any of claims 1-11;
the first sampling unit and the second sampling unit sample the pixel units respectively to acquire a reset signal and an integral signal;
The signal comparison module respectively acquires the reset signal, the integral signal and the slope signal, and compares the reset signal with the slope signal and compares the integral signal with the slope signal; the counting module obtains a comparison result output by the signal comparison module;
the ramp signal is gradually reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to a reset signal to the ramp signal smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit;
the ramp signal continues to decrease, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, wherein the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit.
15. The method according to claim 14, wherein the first sampling unit and the second sampling unit sample the pixel units, respectively, to obtain a reset signal and an integration signal, comprising:
The pixel unit sequentially outputs a reset signal and an integral signal under the action of a second bias current; the first switch and the second switch are changed from an off state to an on state;
the fifth switching circuit is changed from an off state to an on state, and the first capacitor samples the reset signal to an upper plate of the first capacitor;
the fifth switching circuit is changed from an on state to an off state, the sixth switching circuit is changed from an off state to an on state, and the second capacitor samples the integrated signal to an upper plate of the second capacitor.
16. The reading method of the readout circuit according to claim 15, wherein the signal comparison module acquires the reset signal, the integrated signal, and the ramp signal, respectively, and the signal comparison module compares the reset signal with the ramp signal, and compares the integrated signal with the ramp signal; the counting module acquires a comparison result output by the signal comparison module, the ramp signal is gradually reduced, and when the comparison result acquired by the counting module is changed from a state that the ramp signal is equal to a reset signal to a state that the ramp signal is smaller than the reset signal, the counting module starts counting, and the reset signal corresponds to the larger one of the output of the first sampling unit and the output of the second sampling unit; the ramp signal is continuously reduced, and when the comparison result obtained by the counting module is changed from the ramp signal equal to the integral signal to the ramp signal smaller than the integral signal, the counting module stops counting and outputs a counting result, and the integral signal corresponds to the smaller one of the output of the first sampling unit and the output of the second sampling unit and comprises the following components:
The second switch is changed from an on state to an off state, the fourth switch is changed from an off state to an on state, the grid electrode of the first N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the second N-type transistor is conducted with the upper plate of the first capacitor to acquire the reset signal;
the first N-type transistor and the branch where the second N-type transistor are located compare the ramp signal with the reset signal, when the ramp signal is higher than the reset signal, a first comparison result output by the signal comparison module is low level and is converted into a first digital signal through the synchronous feedback circuit, the first digital signal is 0, the first comparison result is equal to the product of a first coefficient and a first difference value, the first coefficient is the product of transconductance and output impedance of the signal comparison module, and the first difference value is the difference value between the ramp signal and the reset signal;
as the ramp signal gradually decreases, and when the ramp signal is equal to the reset signal and becomes smaller than the reset signal, the first comparison result output by the signal comparison module is high level, the first comparison result is converted into a second digital signal through the synchronous feedback circuit, the second digital signal is 1, and the counting module receives the second digital signal and starts counting;
The synchronous feedback circuit controls the first switch and the fourth switch to be turned off from the on state through a switch control signal, the second switch and the third switch are turned on from the off state, the grid electrode of the third N-type transistor is conducted with the slope generator to acquire the slope signal, and the grid electrode of the fourth N-type transistor is conducted with the upper plate of the second capacitor to acquire the integral signal;
the branch circuit where the third N-type transistor and the fourth N-type transistor are located compares the slope signal with the integral signal, and when the slope signal is higher than the integral signal, a second comparison result output by the signal comparison module is high level and is converted into the second digital signal through the synchronous feedback circuit;
as the ramp signal gradually decreases, and when the ramp signal is equal to the integral signal and the ramp signal is smaller than the integral signal, the second comparison result output by the signal comparison module is low level and is converted into the first digital signal through the synchronous feedback circuit, and the counting module receives the first digital signal and stops counting; the second comparison result is equal to the product of a first coefficient and a second difference value, wherein the first coefficient is the product of the transconductance and the output impedance of the signal comparison module, and the second difference value is the difference value of the ramp signal and the integral signal;
And the counting module outputs a counting result.
17. The method according to claim 16, further comprising, after the counting module outputs the count result:
the first switch is changed from an off state to an on state, the second switch is kept in an on state, the third switch is changed from an on state to an off state, and the fourth switch is kept in an off state, so that the readout circuit is restored to a state before the pixel unit output is acquired.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2013175936A (en) * | 2012-02-24 | 2013-09-05 | Renesas Electronics Corp | Semiconductor device and imaging device |
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