CN114023817A - GaN HEMT device with piezoelectric layer - Google Patents
GaN HEMT device with piezoelectric layer Download PDFInfo
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- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 9
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- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 229920000620 organic polymer Polymers 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims 3
- 150000002739 metals Chemical class 0.000 claims 1
- 229910052759 nickel Inorganic materials 0.000 claims 1
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- 230000000694 effects Effects 0.000 abstract description 7
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
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- 238000005406 washing Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The invention provides a structure of a GaN HEMT device with a dielectric layer and a preparation method thereof. The conversion of electric energy and mechanical energy is realized by taking the piezoelectric effect of a piezoelectric medium layer as a principle, and the stress of the device is regulated and controlled by applying voltage on a gate electrode to influence the two-dimensional electron gas concentration of an AlGaN/GaN heterojunction channel, so that the conduction current of the device is influenced. On the basis of the structure of the traditional GaN HEMT device, the traditional gate dielectric layer is replaced by the piezoelectric material, so that a brand-new GaN HMET device structure with the dielectric layer is invented.
Description
Technical Field
The invention relates to the technical field of electronic component manufacturing, in particular to a GaN HEMT (gallium nitride high electron mobility transistor) device structure with a piezoelectric medium layer.
Background
Gallium nitride, which is a third-generation wide bandgap semiconductor, has many performance advantages over silicon materials, including wide bandgap, high breakdown voltage, high electron saturation velocity, high critical breakdown field, and the like. At present, gallium nitride is mainly applied to the fields of LEDs (light emitting diodes) and radio frequencies, and starts to develop later but also develops rapidly in the power device aspect.
In the aspect of power devices, most GaN devices are mainly made into a heterojunction transverse structure GaN HEMT (high electron mobility transistor) structure, and meanwhile, a gate dielectric layer is added below a gate, so that the interface quality is improved, the gate leakage current is reduced, and the device performance is improved. At present, the mainstream gate dielectric layer in the market mainly comprises Al2O3、Si3N4、SiO2Or HfO2Any one or a combination of more of them, and the like.
The piezoelectric material comprises piezoelectric single crystal, piezoelectric ceramic, piezoelectric semiconductor or organic polymer piezoelectric material, etc., and the piezoelectric effect realizes the conversion of electric energy and mechanical energy due to the piezoelectric effect, and has the advantages of low price and simple and convenient growth process, and has great potential as a gate dielectric layer.
On the basis of the structure of the traditional GaN HEMT device, the traditional gate dielectric layer is replaced by the piezoelectric material, so that a brand-new GaN HMET device structure with the dielectric layer is invented.
Disclosure of Invention
The invention relates to a GaN HMET device with a piezoelectric medium layer. The stress of the piezoelectric medium is adjusted through the control voltage of the piezoelectric medium to influence the concentration of the two-dimensional electron gas, so that the resistance or the conductance of the device is adjusted.
Principle of piezoelectric medium layer: piezoelectric materials exhibit piezoelectric effects, including positive and negative piezoelectric effects. When a stress is applied to the piezoelectric material, dielectric polarization proportional to the stress occurs, and polarization charges are generated, which is called a positive piezoelectric effect. Conversely, when a large electric field is applied to the piezoelectric material, a stress proportional to the polarization charge is generated, which is called the inverse piezoelectric effect. The voltage is applied to the pressure medium, so that the stress of the medium layer is changed, the concentration of the two-dimensional electron gas is influenced, and the performance of the device is adjusted.
In order to realize the purpose of the GaN HEMT device with the piezoelectric medium layer, the technical scheme adopted by the invention is as follows:
1) GaN/AlGaN materials are epitaxially grown on a substrate, and a desired GaN epitaxial wafer is fabricated by Metal Organic Chemical Vapor Deposition (MOCVD), which is a conventional semiconductor process in the prior art and is not an improvement in the present invention, and will not be described in detail herein. The epitaxial wafer substrate comprises but is not limited to a Si substrate, a GaN self-substrate, a sapphire substrate, a GaAs substrate, a SiC substrate and the like, the thickness of the substrate is 500nm, the thickness of a GaN buffer layer is 1-2 mu m, and the thickness of an AlGaN barrier layer is 20-30nm, as shown in figure 3 (a);
2) and (3) organic and inorganic cleaning, namely performing organic and inorganic cleaning on the GaN epitaxial wafer, and soaking a sample in HCl: h2O is 1: 1 for 1-2 min, washing for 1min by flowing deionized water, and drying by a nitrogen gun to finish the substrate washing;
3) isolating a table top, namely performing alignment mark manufacturing and active area table top isolation on a cleaned sample, throwing photoresist on the sample, then performing prebaking on a hot plate for 3-5 min, performing ultraviolet exposure through a photoetching machine, then selecting a developing solution according to the photoresist for developing to form a corrosion window and an alignment mark, and forming table top isolation in an active area of a device through Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP), wherein the etching depth is 150nm, as shown in figure 3 (b);
4) depositing an ohmic contact source and a drain electrode, performing photoresist uniformizing, photoetching and developing on the device with the isolated table top to form source and drain electrode windows, then completing deposition of a plurality of metal layers of the ohmic contact source and the drain electrode by adopting electron beam evaporation, wherein the plurality of metal layers comprise Ti/Al/Ni/Au, the thicknesses of the metal layers are 20/50/40/50nm respectively, and then performing Rapid Thermal Annealing (RTA) to form source and drain ohmic contacts, wherein the RTA conditions are 850 ℃ and 30s, as shown in figure 3 (c);
5) depositing a piezoelectric medium layer, namely adhering piezoelectric materials between the ohmic contact source and the drain to form the piezoelectric medium layer, wherein the thickness of the piezoelectric medium layer is 20-30nm, different adhering conditions are selected according to different piezoelectric materials, and the piezoelectric medium layer comprises but is not limited to piezoelectric single crystals, piezoelectric ceramics, piezoelectric semiconductors or organic polymer piezoelectric materials and the like, as shown in fig. 3 (d);
6) depositing a gate electrode, coating photoresist on a sample in a spinning mode, forming a gate slot window through a series of exposure and development, and adopting electron beam evaporation or magnetic controlSputtering and depositing a plurality of layers of metal of the grid, wherein the plurality of layers of metal comprise Ni/Au, the thicknesses of the plurality of layers of metal are respectively 20nm and 50nm, stripping the photoresist by using acetone, and then adopting a nitrogen in-situ plasma treatment technology to perform N2And forming a grid electrode for 30s in the atmosphere, and finishing the device manufacturing, as shown in figure 3 (e).
The invention has the beneficial effects that:
1. the piezoelectric medium layer is controlled by adding voltage to the grid, and the stress of the piezoelectric medium is adjusted to influence the concentration of the two-dimensional electron gas, so that the resistance or the conductance of the device is adjusted, and the performance of the device is optimized.
2. The processing technology is simplified, the material cost is reduced by adding the low-cost piezoelectric material to replace the original gate dielectric layer, and meanwhile, the technology is simple to manufacture, easy to realize and beneficial to industrial application.
Drawings
FIG. 1 is a flow chart of a GaN HMET device fabrication with a dielectric layer under pressure;
FIG. 2 is a block diagram of a GaN HMET device with a dielectric layer under pressure;
fig. 3(a-e) is a flow diagram of the fabrication of a GaN HMET device with a dielectric layer under pressure.
Wherein a substrate (1); a GaN buffer layer (2); an AlGaN barrier layer (3); an ohmic contact source electrode (4); an ohmic contact drain electrode (5); a piezoelectric dielectric gate layer (6); a gate electrode (7).
Detailed Description
The technical solution of the present invention is described below with reference to the accompanying drawings and examples.
Example 1, see fig. 3(a) - (e):
the invention provides a GaN HMET device structure with a piezoelectric medium layer, which is prepared by the following steps:
1) GaN/AlGaN materials are epitaxially grown on a substrate, and a desired GaN epitaxial wafer is fabricated by Metal Organic Chemical Vapor Deposition (MOCVD), which is a conventional semiconductor process in the prior art and is not an improvement in the present invention, and will not be described in detail herein. The epitaxial wafer substrate comprises but is not limited to a Si substrate, a GaN self-substrate, a sapphire substrate, a GaAs substrate, a SiC substrate and the like, the thickness of the substrate is 500nm, the thickness of a GaN buffer layer is 1-2 mu m, and the thickness of an AlGaN barrier layer is 20-30nm, as shown in figure 3 (a);
2) and (3) organic and inorganic cleaning, namely performing organic and inorganic cleaning on the GaN epitaxial wafer, and soaking a sample in HCl: h2O is 1: 1 for 1-2 min, washing for 1min by flowing deionized water, and drying by a nitrogen gun to finish the substrate washing;
3) isolating a table top, namely performing alignment mark manufacturing and active area table top isolation on a cleaned sample, throwing photoresist on the sample, then performing prebaking on a hot plate for 3-5 min, performing ultraviolet exposure through a photoetching machine, then selecting a developing solution according to the photoresist for developing to form a corrosion window and an alignment mark, and forming table top isolation in an active area of a device through Reactive Ion Etching (RIE) or inductively coupled plasma etching (ICP), wherein the etching depth is 150nm, as shown in figure 3 (b);
4) depositing an ohmic contact source and a drain electrode, performing photoresist uniformizing, photoetching and developing on the device with the isolated table top to form source and drain electrode windows, then completing deposition of a plurality of metal layers of the ohmic contact source and the drain electrode by adopting electron beam evaporation, wherein the plurality of metal layers comprise Ti/Al/Ni/Au, the thicknesses of the metal layers are 20/50/40/50nm respectively, and then performing Rapid Thermal Annealing (RTA) to form source and drain ohmic contacts, wherein the RTA conditions are 850 ℃ and 30s, as shown in figure 3 (c);
5) depositing a piezoelectric medium layer, namely adhering piezoelectric materials between the ohmic contact source and the drain to form the piezoelectric medium layer, wherein the thickness of the piezoelectric medium layer is 20-30nm, different adhering conditions are selected according to different piezoelectric materials, and the piezoelectric medium layer comprises but is not limited to piezoelectric single crystals, piezoelectric ceramics, piezoelectric semiconductors or organic polymer piezoelectric materials and the like, as shown in fig. 3 (d);
6) depositing a gate electrode, coating photoresist on a sample in a spinning mode, forming a gate slot window through a series of exposure and development, depositing a plurality of layers of metal of the gate electrode by adopting electron beam evaporation or magnetron sputtering, wherein the plurality of layers of metal comprise Ni/Au, the thickness of the metal is 20nm and 50nm respectively, stripping the photoresist by using acetone, and then adopting a nitrogen in-situ plasma processing technology to perform N-phase plasma processing on the metal2And forming a grid electrode for 30s in the atmosphere, and finishing the device manufacturing, as shown in figure 3 (e).
The above embodiments are only used for illustrating but not limiting the technical solutions of the present invention, and although the above embodiments describe the present invention in detail, those skilled in the art should understand that: modifications and equivalents may be made thereto without departing from the spirit and scope of the invention and any modifications and equivalents may fall within the scope of the claims.
Claims (7)
1. A GaN HMET device with a piezoelectric medium layer is characterized in that: a substrate (1); a GaN buffer layer (2); an AlGaN barrier layer (3); an ohmic contact source electrode (4); an ohmic contact drain electrode (5); a piezoelectric dielectric gate layer (6); a gate electrode (7).
2. The GaN HMET structure with piezoelectric medium layer as claimed in claim 1, wherein: the GaN buffer layer (2) is extended on the surface of the substrate (1), and an AlGaN barrier layer (3) is grown on the GaN buffer layer (2).
3. The GaN HMET structure with piezoelectric medium layer as claimed in claim 2, wherein: the thickness of the substrate (1) is about 500 mu m, the thickness of the GaN buffer layer (2) is about 1-3 mu m, and the thickness of the AlGaN barrier layer (3) is about 10-30 nm.
4. The GaN HMET structure with piezoelectric medium layer as claimed in claim 3, wherein: and depositing an ohmic contact source electrode (4) and an ohmic contact drain electrode (5) on the AlGaN barrier layer (3).
5. The GaN HMET structure with piezoelectric medium layer as claimed in claim 4, wherein: the ohmic contact source electrode (4) and the ohmic contact drain electrode (5) are formed by the combined deposition of a plurality of layers of metals, including but not limited to Ti/Al/Ni/Au, Ti/Al/Pt/Au and the like; the deposition mode of the ohmic contact source electrode (4) and the ohmic contact drain electrode (5) comprises but is not limited to magnetron sputtering deposition or electron beam evaporation deposition and the like.
6. The GaN HMET structure with piezoelectric medium layer as claimed in claim 5, wherein: a piezoelectric medium grid layer (6) is formed between the ohmic contact source electrode (4) and the ohmic contact drain electrode (5), the thickness of the piezoelectric medium grid layer (6) is about 20-30nm, and the piezoelectric medium grid layer (6) comprises but is not limited to piezoelectric single crystals, piezoelectric ceramics, piezoelectric semiconductors or organic polymer piezoelectric materials and the like.
7. The GaN HMET structure with piezoelectric medium layer as claimed in claim 5, wherein: depositing a gate electrode (7) on the piezoelectric medium gate layer (6), wherein the gate electrode (7) is formed by depositing a plurality of layers of metal combinations, including but not limited to Ni/Au, Pt/Au, Ni/Au/Ni and the like; the deposition mode of the gate electrode (7) comprises but is not limited to magnetron sputtering deposition or electron beam evaporation deposition and the like.
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| CN202111291026.2A CN114023817A (en) | 2021-11-01 | 2021-11-01 | GaN HEMT device with piezoelectric layer |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752389A (en) * | 2009-10-16 | 2010-06-23 | 中国科学院上海技术物理研究所 | Al2O3/AlN/GaN/AlN MOS-HEMT device and manufacturing method thereof |
| US20120319169A1 (en) * | 2011-06-20 | 2012-12-20 | Imec | Cmos compatible method for manufacturing a hemt device and the hemt device thereof |
| US20140060210A1 (en) * | 2012-09-05 | 2014-03-06 | Sungkyunkwan University Foundation For Corporate Collaboration | Pressure sensor and pressure sensing method |
| CN104655000A (en) * | 2015-02-02 | 2015-05-27 | 上海集成电路研发中心有限公司 | Flexible active strain transducer structure and preparation method |
| CN105514157A (en) * | 2016-01-13 | 2016-04-20 | 中国科学院上海技术物理研究所 | GaN-based double heterojunction HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
-
2021
- 2021-11-01 CN CN202111291026.2A patent/CN114023817A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752389A (en) * | 2009-10-16 | 2010-06-23 | 中国科学院上海技术物理研究所 | Al2O3/AlN/GaN/AlN MOS-HEMT device and manufacturing method thereof |
| US20120319169A1 (en) * | 2011-06-20 | 2012-12-20 | Imec | Cmos compatible method for manufacturing a hemt device and the hemt device thereof |
| US20140060210A1 (en) * | 2012-09-05 | 2014-03-06 | Sungkyunkwan University Foundation For Corporate Collaboration | Pressure sensor and pressure sensing method |
| CN104655000A (en) * | 2015-02-02 | 2015-05-27 | 上海集成电路研发中心有限公司 | Flexible active strain transducer structure and preparation method |
| CN105514157A (en) * | 2016-01-13 | 2016-04-20 | 中国科学院上海技术物理研究所 | GaN-based double heterojunction HEMT (High Electron Mobility Transistor) device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| RAJ K. JANA等: "On the possibility of sub-60 mV/decade subthreshold switching in piezoelectric gate barrier transistors", 《PHYS. STATUS SOLIDI C》, vol. 10, no. 11, pages 1471 * |
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Application publication date: 20220208 |