CN114020668A - Signal processing system, mainboard and server - Google Patents
Signal processing system, mainboard and server Download PDFInfo
- Publication number
- CN114020668A CN114020668A CN202111164877.0A CN202111164877A CN114020668A CN 114020668 A CN114020668 A CN 114020668A CN 202111164877 A CN202111164877 A CN 202111164877A CN 114020668 A CN114020668 A CN 114020668A
- Authority
- CN
- China
- Prior art keywords
- cable
- pcie
- mainboard
- nvme
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012545 processing Methods 0.000 title claims abstract description 39
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- IHIDFKLAWYPTKB-UHFFFAOYSA-N 1,3-dichloro-2-(4-chlorophenyl)benzene Chemical compound C1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl IHIDFKLAWYPTKB-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- JHBVPKZLIBDTJR-UHFFFAOYSA-N 1,2-dichloro-4-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C=C(Cl)C(Cl)=CC=2)=C1 JHBVPKZLIBDTJR-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
The application discloses signal processing system, mainboard and server includes: the PCIe connector is arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard; the OCP equipment is detachably connected with the PCIe connector through the first cable, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment; and the NVME equipment is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module and used for indicating address information of a PCIe signal sent to the NVME equipment. According to the application, the connection of the OCP3.0 network card and the connection of the NVME backboard can be simultaneously compatible under the same PCIe port on the CPU of the mainboard, the mainboard can support more NVME hard disks, and the requirement of higher configuration of a client is met.
Description
Technical Field
The present application relates to the field of servers, and in particular, to a signal processing system, a motherboard, and a server.
Background
With the rapid development of computer technology, informatization gradually covers all areas of society, and the requirements on the performance of servers and the flexibility of applications are increasing. For a server, the rapid development of Network technology makes people put higher demands on the application and the type of a Network Card device of the server, so that an OCP (Open computer Project) NIC (Network Interface Card) appears in the field of view of people, an OCP NIC 3.0 Network Card also becomes a configuration item of a server standard, and for a storage technology, NVME (Non-Volatile Memory host controller Interface specification) is gradually and more widely applied to computer products, because of the appearance of NVME, the performance of a hard Disk is greatly improved, and an SSD (Solid State Disk) of NVME also becomes a mainstream configuration of the server.
Referring to fig. 1, PCIe signals of PCIe Port0 and power, NCSI (Network Controller Sideband Interface) signals and other Sideband signals on the motherboard are connected to a 4C + connector, the OCP Network card is directly inserted into the connector through a gold finger, if NVME needs to be supported at the same time, another PCIe Port, namely PCIe (Peripheral Component Interconnect Express) signals and NVME address signals on PCIe Port1 are connected to a slim connector of X8 and then connected to an NVME backplane through a cable, so as to implement NVME functions.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The utility model aims at providing a signal processing system, mainboard and server can realize the connection of compatible OCP3.0 network card simultaneously and the connection of NVME backplate under the same PCIe port on the CPU of mainboard, and the mainboard can support more NVME hard disks, satisfies the higher requirement of configuration of customer.
In order to solve the above technical problem, the present application provides a signal processing system, including:
the PCIe connector is arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard;
the OCP equipment is detachably connected with the PCIe connector through the first cable, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment;
and the NVME equipment is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module and used for indicating address information of a PCIe signal sent to the NVME equipment.
Optionally, first cable is trinity cable, the first end of first cable is connected the OCP equipment, the second end of first cable is connected power module on the mainboard, the third end of first cable is connected outband management module on the mainboard, the fourth end of first cable with the PCIe connector is connected.
Optionally, the first end of the first cable is connected to the OCP device through a 4C + connector.
Optionally, the second cable further includes a first gold finger, a second gold finger, a first pad, a second pad, a first PCB board and a second PCB board, wherein:
the first golden finger is connected with the NVME equipment, the second golden finger is connected with the PCIe connector, the first pad is connected with the first PCB, the first PCB is connected with the first golden finger, the second pad is connected with the second PCB, the second PCB is connected with the second golden finger, and the address module is arranged on the first PCB.
Optionally, a power supply end of the address module is connected to the P3V3_ STBY end on the motherboard, and a ground end of the address module is connected to a ground end on the motherboard.
Optionally, the address module includes a pull-up resistance unit and a pull-down resistance unit.
To solve the above technical problem, the present application further provides a motherboard including the signal processing system as described in any one of the above.
In order to solve the above technical problem, the present application further provides a server, including the motherboard as described above.
The application provides a signal processing system, comprising: the PCIe connector is arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard; the OCP equipment is detachably connected with the PCIe connector through the first cable, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment; and the NVME equipment is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module and used for indicating address information of a PCIe signal sent to the NVME equipment.
In practical application, adopt the scheme of this application, OCP equipment adopts first cable and mainboard connection, it is more nimble to cut straightly to the mainboard in OCP, this application can no longer be limited by the restriction of mechanism and realize the OCP function, OCP's sideband signal no longer uses an solitary connector simultaneously, but put these signals and realize above the PCIe connector on the mainboard, like this can make full use of the space of connector, reduce the use of the connector on the mainboard, save cost more, set up NVME address signal processing and realize on the second cable, can be more nimble use on the mainboard, can be compatible simultaneously under the same PCIe port on the CPU of mainboard connection of OCP3.0 network card and NVME backplate, the mainboard can support more NVME, satisfy the requirement of the higher configuration of customer.
The application also provides a mainboard and a server, which have the same beneficial effects as the signal processing system.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic diagram illustrating connection between a motherboard and NVME equipment and OCP equipment in the prior art;
FIG. 2 is a schematic diagram of a signal processing system according to the present application
Fig. 3 is a schematic structural diagram of a connection between an OCP device and a motherboard provided in the present application;
fig. 4 is a schematic structural diagram of connection between NVME equipment and a motherboard according to the present application;
fig. 5 is a schematic structural diagram of a second cable provided in the present application.
Detailed Description
The core of the application is to provide a signal processing system, a mainboard and a server, the connection of the OCP3.0 network card and the connection of the NVME backboard can be simultaneously compatible under the same PCIe port on the CPU of the mainboard, the mainboard can support more NVME hard disks, and the requirement of higher configuration of a client is met.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a signal processing system provided in the present application, the signal processing system including:
a PCIe connector 1 arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard;
the OCP device is detachably connected with the PCIe connector 1 through the first cable 2, and the PCIe connector 1 is provided with a processing module 21 for processing sideband signals of the OCP device;
Specifically, the connector arranged on the motherboard is specifically a SLIMLINE connector, one end of the connector is connected with a PCIe port of the CPU on the motherboard and is used for transmitting a PCIe signal, and in this embodiment, the OCP device and the NVME device are connected to the SLIMLINE connector through the first cable 2 and the second cable 3, respectively.
As an alternative embodiment, referring to fig. 3, fig. 3 is a schematic diagram of the OCP device connected to the motherboard through the first cable 2, the first cable 2 is a three-in-one cable, a 4C + connector is disposed at a first end of the first cable 2 for connecting the OCP device, a second end of the first cable 2 is connected to the POWER module POWER on the motherboard, a third end of the first cable 2 is connected to the NCSI module outside the band on the motherboard, and a fourth end of the first cable 2 is connected to the connector. Compared with the OCP device which is directly plugged on a mainboard, the scheme of the embodiment is more flexible, the OCP function can be realized without being limited by the limitation of a mechanism, in addition, regarding the sideband signal of the OCP device, the processing module 21 for processing the sideband signal of the OCP device is arranged on the PCIe connector 1, a separate connector is not used, and the sideband signals are put on the PCIe slim line connector, so that the space of the slim line connector can be fully utilized, the use of the connector on the mainboard is reduced, and the cost is saved more.
It should be noted that the NVME signals are divided into two parts, one part is PCIe signals, the other part is NVME address signals, the NVME address signals include CPU _ ADDR [2:0] and VPP _ ADDR [3:0], wherein CPU _ ADDR indicates which CPU the PCIe signals connected to the NVME come from, and VPP _ ADDR indicates which PCIe port under the CPU the PCIe signals connected to the NVME come from. For example, we define CPU _ ADDR [2:0] as 000 to represent CPU0, VPP _ ADDR [3:0] as 0000 to represent PCIe port0, and the NVME ADDRESS signal is to the CPLD of the backplane, then if CPLD recognizes NVME ADDRESS as 000_0000, then it can locate the NVME hard disk under CPU0_ PE 0.
Normally, if the design is independent, the two parts of signals can be put on the PCIe slim line connector, as shown in the NVME part in fig. 1, but according to the requirements of compatibility between the OCP and the NVME, such a connection cannot be satisfied, because the spare positions on the PCIe slim line connector except for the PCIe signal are occupied by the OCP sideband signal, so that the NVME address signal cannot be connected to the PCIe slim line connector. In order to meet the requirement that the same PCIe port can be compatible with the connection of the OCP3.0 network card and the NVME at the same time, the NVME address signal is designed on the NVME cable, that is, on the second cable 3 in this embodiment.
As an alternative embodiment, referring to fig. 4, the second cable 3 further includes a first gold finger 31, a second gold finger 36, a first pad 33, a second pad 34, a first PCB board 32 and a second PCB board 35, wherein: the first golden finger 31 is connected with NVME equipment, the second golden finger 36 is connected with a connector, the first pad 33 is connected with the first PCB 32, the first PCB 32 is connected with the first golden finger 31, the second pad 34 is connected with the second PCB 35, the second PCB 35 is connected with the second golden finger 36, and the address module is arranged on the first PCB 32. The structure of the first PCB 32 is shown in fig. 5, and the address module is composed of a pull-up resistor and a pull-down resistor.
Specifically, there are P3V3_ STBY and GND in the position of the MISC on the PCIe SLIMLIN connector of the motherboard end, there is a small PCB in the end of the second cable 3 that is butted against the NVME backplane, and the first PCB 32, the left side of the first PCB 32 is the first pad 33, connect to the second PCB 35 in the end of the second cable 3 that is butted against the motherboard, the right side of the first PCB 32 is the first gold finger 31, connect to the slimline connector of the NVME backplane. P3V3_ STBY and GND on the motherboard are introduced to the first PCB 32 at the back board end of the second cable 3 interfacing NVME, and not directly connected to the gold fingers, CPU _ ADDR [2:0], VPP _ ADDR [3:0] address signals are connected to P3V3_ STBY and GND, respectively, on the first PCB 32 of the second cable 3 via pull-up and pull-down resistors, and then CPU _ ADDR [2:0], VPP _ ADDR [3:0] address signals are connected to the gold fingers at the back board end of the second cable 3 interfacing NVME.
In summary, the design of a special cable and a connection mode realizes that the connection of the OCP3.0 network card and the connection of the NVME backplane can be compatible under the same PCIe PORT, and the motherboard can support more NVME hard disks.
The application provides a signal processing system, comprising: the PCIe connector is arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard; the OCP device is detachably connected with the PCIe connector through the first cable, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP device; and the NVME equipment is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module for indicating address information of a PCIe signal sent to the NVME equipment.
In another aspect, the present application further provides a motherboard including the signal processing system as any one of the above.
For the introduction of a motherboard provided in the present application, please refer to the above embodiments, which are not described herein again.
The mainboard has the same beneficial effect as the signal processing system.
On the other hand, the application also provides a server, which comprises the mainboard.
For introducing a server provided in the present application, please refer to the above embodiments, which are not described herein again.
The server provided by the application has the same beneficial effects as the signal processing system.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A signal processing system, comprising:
the PCIe connector is arranged on the mainboard and connected with a PCIe port of the CPU on the mainboard;
the OCP equipment is detachably connected with the PCIe connector through the first cable, and the PCIe connector is provided with a processing module for processing sideband signals of the OCP equipment;
and the NVME equipment is detachably connected with the PCIe connector through the second cable, and the second cable is provided with an address module and used for indicating address information of a PCIe signal sent to the NVME equipment.
2. The signal processing system of claim 1, wherein the first cable is a three-in-one cable, a first end of the first cable is connected to the OCP device, a second end of the first cable is connected to the power module on the motherboard, a third end of the first cable is connected to the out-of-band management module on the motherboard, and a fourth end of the first cable is connected to the PCIe connector.
3. The signal processing system of claim 2, wherein the first end of the first cable is connected to the OCP device through a 4C + connector.
4. The signal processing system of claim 1, wherein the second cable further comprises a first gold finger, a second gold finger, a first pad, a second pad, a first PCB board, and a second PCB board, wherein:
the first golden finger is connected with the NVME equipment, the second golden finger is connected with the PCIe connector, the first pad is connected with the first PCB, the first PCB is connected with the first golden finger, the second pad is connected with the second PCB, the second PCB is connected with the second golden finger, and the address module is arranged on the first PCB.
5. The signal processing system of claim 4, wherein the power supply terminal of the address module is connected to the P3V3_ STBY terminal on the motherboard, and the ground terminal of the address module is connected to the ground terminal on the motherboard.
6. The signal processing system according to any one of claims 1 to 5, wherein the address module includes a pull-up resistance unit and a pull-down resistance unit.
7. A motherboard comprising a signal processing system as claimed in any one of claims 1 to 6.
8. A server, comprising the motherboard of claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111164877.0A CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111164877.0A CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114020668A true CN114020668A (en) | 2022-02-08 |
| CN114020668B CN114020668B (en) | 2024-02-13 |
Family
ID=80055501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111164877.0A Active CN114020668B (en) | 2021-09-30 | 2021-09-30 | Signal processing system, mainboard and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114020668B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209640782U (en) * | 2019-04-12 | 2019-11-15 | 深圳市同泰怡信息技术有限公司 | A kind of PCIE expansion card of NVMe hard-disk interface |
| CN110502462A (en) * | 2019-08-09 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of OCP adapter and server |
| US20200403330A1 (en) * | 2019-06-18 | 2020-12-24 | Bellwether Electronic Corp. | Plug connector having protective member for replacing gold finger on circuit board |
| CN212571566U (en) * | 2020-06-17 | 2021-02-19 | 安费诺电子装配（厦门）有限公司 | Hybrid cable connector and connector assembly |
-
2021
- 2021-09-30 CN CN202111164877.0A patent/CN114020668B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN209640782U (en) * | 2019-04-12 | 2019-11-15 | 深圳市同泰怡信息技术有限公司 | A kind of PCIE expansion card of NVMe hard-disk interface |
| US20200403330A1 (en) * | 2019-06-18 | 2020-12-24 | Bellwether Electronic Corp. | Plug connector having protective member for replacing gold finger on circuit board |
| CN110502462A (en) * | 2019-08-09 | 2019-11-26 | 苏州浪潮智能科技有限公司 | A kind of OCP adapter and server |
| CN212571566U (en) * | 2020-06-17 | 2021-02-19 | 安费诺电子装配（厦门）有限公司 | Hybrid cable connector and connector assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114020668B (en) | 2024-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Anderson | USB system architecture | |
| US5540597A (en) | All flex PCMCIA-format cable | |
| TWI553443B (en) | Riser card | |
| US20040029407A1 (en) | Combined flash memory card driver | |
| CN108170620A (en) | A kind of server hard disk extension system and method, hard disk signal enhancing method | |
| CN209895219U (en) | Board card based on multifunctional Slimline connector | |
| CN114020668B (en) | Signal processing system, mainboard and server | |
| CN111723037A (en) | PCIE interface extension system and server | |
| CN218213983U (en) | Data computing system and server with built-in data computing system | |
| CN211506475U (en) | Connecting device of OCP network card mutil-host | |
| CN215298145U (en) | Modularized computer server system based on FT2500-64 processor | |
| CN115858426A (en) | Hard disk interface, hard disk and electronic equipment | |
| CN210640452U (en) | Adapter card of special-shaped memory card | |
| CN212061064U (en) | CPU board card with quick plug interface | |
| CN204189089U (en) | A kind of server | |
| CN211124265U (en) | Intelligent POS core mainboard capable of being plugged and defined with physical interface | |
| CN200983159Y (en) | USB multi-purpose interface circuit based on PCI bus | |
| CN211149439U (en) | OCP keysets and support NVME's OCP switching system | |
| CN110456889A (en) | Edge calculations array server based on ARM framework | |
| CN109800189B (en) | Data transmission device of NVME hard disk | |
| CN216286533U (en) | High-performance computing mainboard and equipment | |
| CN219576150U (en) | Solid state disk adapter plate | |
| CN219627731U (en) | Gateway motherboard and gateway | |
| CN216412148U (en) | Multi-port HUB with high mobile storage capacity without physical driver | |
| CN213276522U (en) | Server mainboard and one-way server |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |