CN114005851A - Resistive random access memory and manufacturing method thereof - Google Patents

Resistive random access memory and manufacturing method thereof Download PDF

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Publication number
CN114005851A
CN114005851A CN202010733242.7A CN202010733242A CN114005851A CN 114005851 A CN114005851 A CN 114005851A CN 202010733242 A CN202010733242 A CN 202010733242A CN 114005851 A CN114005851 A CN 114005851A
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China
Prior art keywords
layer
oxygen exchange
electrode
variable resistance
random access
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CN202010733242.7A
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Chinese (zh)
Inventor
许博砚
吴伯伦
蔡世宁
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN202010733242.7A priority Critical patent/CN114005851A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices

Abstract

The invention provides a resistive random access memory and a manufacturing method thereof. The resistance random access memory comprises a first electrode layer and a second electrode layer which are arranged oppositely; a variable resistance layer between the first electrode layer and the second electrode layer; an oxygen exchange layer located between the variable resistance layer and the second electrode layer; a conductor layer laterally surrounding the periphery of the sidewall of the oxygen exchange layer; a first barrier layer between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; and a second barrier layer between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.

Description

Resistive random access memory and manufacturing method thereof
Technical Field
The present invention relates to a memory and a method for manufacturing the same, and more particularly, to a Resistive Random Access Memory (RRAM) and a method for manufacturing the same.
Background
RRAM has advantages of high operation speed, low power consumption, and the like, and thus has become a nonvolatile memory which has been widely studied in recent years. However, the etchant used in the manufacturing process of the RRAM, or during the deposition process of the dielectric layer or during the detection process of the RRAM, may easily cause the sidewall of the oxygen exchange layer to be oxidized, thereby causing the effective area of the oxygen exchange layers of the RRAM to be different from each other, causing the oxygen distribution (oxygen distribution) to be uneven, causing the RRAM to form a current distribution (reforming distribution) to be uneven, and affecting the reliability of the RRAM.
Disclosure of Invention
The invention is directed to a resistive random access memory and a method of manufacturing the same, which can prevent the sidewall of an oxygen exchange layer from being oxidized.
According to the embodiments of the present invention, a resistive random access memory and a method for manufacturing the same are provided, which can control an oxygen exchange layer to have substantially the same effective area, so as to have uniform oxygen distribution, and thus the RRAM can have uniform formation current distribution.
According to an embodiment of the present invention, there is also provided a resistive random access memory including a first electrode layer and a second electrode layer disposed opposite to each other; a variable resistance layer between the first electrode layer and the second electrode layer; an oxygen exchange layer located between the variable resistance layer and the second electrode layer; a conductor layer laterally surrounding the periphery of the sidewall of the oxygen exchange layer; a first barrier layer between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; and a second barrier layer between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
According to an embodiment of the present invention, there is also provided a method for manufacturing a resistive random access memory, including: forming a variable resistance layer on the first electrode layer; forming a conductor layer on the variable resistance layer; forming an opening in the conductor layer; forming a first barrier layer and an oxygen exchange layer in the opening; forming a second barrier layer on the conductor layer and the oxygen exchange layer; and forming a second electrode layer on the barrier layer.
In view of the above, the present invention provides a resistive random access memory and a method for manufacturing the same, which can prevent the sidewall of the oxygen exchange layer from being oxidized, and can control the oxygen exchange layer to have substantially the same effective area, so as to achieve uniform oxygen distribution, thereby enabling the RRAM to have uniform formation current distribution. In addition to the forming current generated by the filament during the SET operation, FN tunneling may also be induced between the variable resistance layer and the conductor layer around the oxygen exchange layer, and the resulting leakage current may increase the total current.
Drawings
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a manufacturing process of a resistance random access memory according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Referring to fig. 1F, a Resistive Random Access Memory (RRAM) cell 10 includes a first electrode 102a, a variable resistance layer 104a, a conductive layer 106a, an oxygen exchange layer 112, a first barrier layer 110, a second barrier layer 114a, and a second electrode 116 a.
The first electrode 102a may be connected to the via 100. The via 100 is, for example, any via (via) of a metal interconnect structure formed on a substrate, such as a via having the same height as a first level via in a first level metal layer closest to the substrate. The substrate may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Other components, such as transistors, may be included between the substrate and the first metal layer. The second electrode 116a may be connected to the via 120. The via 120 is, for example, any via of a metal interconnect structure, such as a via having the same height as a second level via in contact with a second level metal layer. The vias 100 and 120 are formed, for example, by physical vapor deposition of tungsten, aluminum, copper, or combinations thereof.
The material of the first electrode layer 102a and the second electrode 116a may include metal, metal nitride, other materials, or a combination thereof. The material of the first electrode layer 102a and the second electrode 116a is, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium Tungsten (TiW) alloy, platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Gd), manganese (Mo), graphite, or a combination thereof, and the formation method may be, for example, a physical vapor deposition method or a chemical vapor deposition method. The first electrode layer 102a and the second electrode layer 116a may be a single layer or a plurality of layers. The thicknesses of the first electrode layer 102a and the second electrode 116a are not particularly limited, but are generally between 5 nanometers (nm) and 500 nm.
The variable resistance layer 104a is located between the first electrode layer 102a and the second electrode 116 a. The variable-resistance layer 104a may have the following characteristics: when a positive bias is applied to the Resistance random access memory, oxygen ions are attracted by the positive bias to leave the variable Resistance layer 104a to generate oxygen vacancies (oxygen vacancies) to form filaments (filaments) and to present an on State, and at this time, the variable Resistance layer 104a is switched from a High Resistance State (HRS) to a Low Resistance State (LRS); when a negative bias is applied to the rram, oxygen ions enter the resistance variable layer 104a to break the filament and assume a non-conductive state, and the resistance variable layer 104a is switched from LRS to HRS. Generally, switching of variable-resistance layer 104a from HRS to LRS is referred to as a SET (hereinafter SET) operation, and switching of variable-resistance layer 104a from LRS to HRS is referred to as a RESET (hereinafter RESET) operation. The material of the variable-resistance layer 104a is not particularly limited, and any material that can change its own resistance by the application of voltage can be used. In the present embodiment, the material of the variable resistance layer 104a includes a metal oxide, such as hafnium oxide (HfO)2) Tantalum oxide (Ta)2O5) Titanium oxide (TiO)2) Magnesium oxide (MgO), nickel oxide (NiO), niobium oxide (Nb)2O5) Alumina (Al)2O3) Vanadium oxide (V)2O5) Tungsten oxide (WO)3) Zinc oxide (ZnO) or cobalt oxide (CoO) by a chemical vapor deposition method or an atomic layer deposition method, for example. In the present embodiment, the oxygen content of the variable resistance layer 104a may be about 75 atomic percent (at%) to about 100 atomic percent. The thickness of the variable-resistance layer 104a is, for exampleIs 2 nm to 10 nm.
The conductor layer 106a, the first barrier layer 110, the oxygen exchange layer 112, and the second barrier layer 114a are located between the variable resistance layer 104a and the second electrode layer 116 a. The first barrier layer 110 and the second barrier layer 114a surround the oxygen exchange layer 112. The first barrier layer 110 is located between the conductor layer 106a and the oxygen exchange layer 112, and between the oxygen exchange layer 112 and the variable resistance layer 104 a. The second barrier layer 114a is located between the second electrode 116a and the conductor layer 106a, and between the second electrode 116a and the oxygen exchange layer 112. The first barrier layer 110 and the second barrier layer 114a may comprise a high-k dielectric material layer, such as aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Or zirconium oxide (ZrO)2). In this embodiment, when the RRAM cell 10 performs the RESET operation, the first barrier layer 110 and the second barrier layer 114a may block oxygen ions in the oxygen exchange layer 112 from diffusing to the second electrode 116.
The oxygen exchange layer 112 is surrounded by the first barrier layer 110 and the second barrier layer 114 a. The sidewalls and bottom surface of the oxygen exchange layer 112 are covered by the first barrier layer 110, while the top surface of the oxygen exchange layer 112 is covered by the second barrier layer 114 a. The oxygen exchange layer 112 may be a material that bonds with oxygen more readily than the conductor layer 106a and the variable resistance layer 104 a. When the RRAM cell 10 performs the SET operation, oxygen ions in the variable resistance layer 104a enter the oxygen exchange layer 112 after being attracted away from the variable resistance layer 104a by the positive bias voltage; when the RRAM cell 10 performs the RESET operation, the oxygen ions in the oxygen exchange layer 112 return to the variable resistance layer 104 a. The material of the oxygen exchange layer 112 may include a metal oxide that is not fully oxidized. In other words, the oxygen exchange layer 112 itself is a metal layer containing oxygen ions. When RRAM cell 10 performs the RESET operation, there are enough oxygen ions in oxygen exchange layer 112 to enter variable resistance layer 104 because oxygen ions from variable resistance layer 104a and oxygen ions contained in oxygen exchange layer 112 are present. Specifically, in the present embodiment, the material of the oxygen exchange layer 112 may include, for example, TiO2-x、HfO2-xOr TaO2-xWherein x is 0.2 to 0.7. In the present embodiment, the top area of the oxygen exchange layer 112 is smaller than the bottom area of the second electrode 116a, and the oxygen exchange layer 112Is smaller than the top area of the variable-resistance layer 104 a.
The conductor layer 106a is located between the second barrier layer 114a and the variable resistance layer 104a and laterally surrounds the oxygen exchange layer 112 and the sidewalls of the first barrier layer 110 to prevent oxygen from diffusing into the oxygen exchange layer 112. In one embodiment, the top surface of the conductive layer 106a is coplanar with the top surface of the first barrier layer 110 and the top surface of the oxygen exchange layer 112. The bottom surface of the conductive layer 106a is coplanar with the top surface of the first barrier layer 110. The conductor layer 106a comprises a material that is less prone to oxygen bonding than the oxygen exchange layer 112. The conductor layer 106a may also be referred to as an inert conductor layer 106 a. The conductive layer 106a may be a single layer or a plurality of layers. The material of the conductive layer 106a may be a metal or a metal nitride, such as platinum, iridium, ruthenium, rhodium, tungsten, titanium, hafnium, tantalum, hafnium nitride, tantalum nitride, titanium nitride, tungsten nitride, or a combination thereof, and the forming method is, for example, a physical vapor deposition method. The thickness of the conductor layer 106a is, for example, 10 nm to 100 nm. From a top view, each conductor layer 106a may be a ring that surrounds the oxygen exchange layer 112. The width W1 of the ring of the conductor layer 106a is less than the width W2 of the oxygen exchange layer 112. The ratio of the width W1 of the ring of the conductor layer 106a to the width W2 of the oxygen exchange layer 112 is, for example, 0.2 to 0.8. The width W1 of the ring of the conductive layer 106a is, for example, 50 nm to 200 nm.
When the resistance random access memory performs the SET operation, oxygen ions in the variable resistance layer 104a are attracted away from the variable resistance layer 104a by the positive bias voltage and enter the oxygen exchange layer 112, and oxygen vacancies are generated in the variable resistance layer 104a, thereby forming a filament current. In addition, during the SET operation, electrons in the variable resistance layer 104a are attracted by the positive bias voltage, and Fowler-nordheim (fn) tunneling is induced between the conductive layer 106a and the variable resistance layer 104a, thereby causing leakage current. The formation of leakage current may cause an increase in the total current for the SET operation. When the RRAM cell 10 performs the RESET operation, the oxygen ions in the oxygen exchange layer 112 return to the variable resistance layer 104a, and FN tunneling is not induced between the variable resistance layer 104a and the conductor layer 106 a.
The sidewalls and top surface of RRAM cell 10 are surrounded by dielectric layer 118. The first electrode 102a, the variable resistance layer 104a, the conductor layer 106a, the sidewall of the first barrier layer 110, and the sidewall and the top surface of the second electrode 116a of the RRAM cell 10 are covered with and in contact with the dielectric layer 118. The oxygen exchange layer 112 is separated from the dielectric layer 118 by the first barrier layer 110 and the conductive layer 106a without contact.
A method of manufacturing the RRAM cell 10 can be described as follows with reference to fig. 1A to 1F. Herein, the same or similar components are denoted by the same or similar reference numerals, and may be formed using the same material or method. For example, the first electrode layers 102 and 102a can be formed by the same material or method.
Referring to fig. 1A, a first electrode layer 102, a variable resistance layer 104, and a conductive layer 106 are sequentially formed on a substrate (not shown) on which a via 100 is formed. The material of the via 100 is, for example, tungsten.
Referring to fig. 1B, a photolithography and etching process (e.g., an anisotropic etching process) is performed to pattern the conductive layer 106 and form an opening 108 in the conductive layer 106. The opening 108 exposes the variable-resistance layer 104.
Referring to fig. 1C, a first barrier layer 110 and an oxygen exchange layer 112 are formed in the opening 108. The method of forming the first barrier layer 110 and the oxygen exchange layer 112 includes the following steps, for example. After forming the first barrier layer 110 and the oxygen exchange layer 112 on the conductive layer 106 and in the opening 108, a chemical mechanical polishing process is performed to remove the first barrier layer 110 and the oxygen exchange layer 112 on the conductive layer 106.
Referring to fig. 1D, a second barrier layer 114 and a second electrode layer 116 are formed on the conductor layer 106, the first barrier layer 110 and the oxygen exchange layer 112.
Referring to fig. 1E, photolithography and etching processes are performed to pattern the second electrode layer 116, the second barrier layer 114, the conductive layer 106, the variable resistance layer 104 and the first electrode layer 102, so as to form a plurality of RRAM cells 10. Each RRAM cell 10 includes a first electrode 102a, a variable resistance layer 104a, a conductor layer 106a, an oxygen exchange layer 112, a first barrier layer 110, a second barrier layer 114a, and a second electrode 116 a.
Referring to fig. 1F, a dielectric layer 118 is formed on the substrate. The dielectric layer 118 is, for example, silicon oxide formed by chemical vapor deposition or a low-k material. Thereafter, photolithography and etching processes are performed to form via openings in the dielectric layer 118. Then, a via 120 is formed in the via opening. The material of the via 120 is, for example, tungsten.
In summary, since the oxygen exchange layer according to the embodiment of the present invention is covered with the variable resistance layer, the conductor layer, the second barrier layer, and the second electrode layer, the etchant used for etching the conductor layer does not contact the oxygen exchange layer, and the dielectric layer does not contact the oxygen exchange layer. Therefore, the sidewalls of the oxygen exchange layer do not oxidize during etching, dielectric layer deposition, thermal process or testing, thereby affecting the effective area and volume.
In the method of embodiments of the present invention, the oxygen exchange layer of each RRAM cell may have substantially the same effective area to provide uniform oxygen distribution through the control of the patterning process. Accordingly, the RRAM may have a uniform formation current distribution.
Furthermore, because the method of the embodiment of the invention can prevent the oxidation of the sidewall of the oxygen exchange layer to form the oxide layer, the reliability problem caused by the extra oxygen atoms or oxygen ions provided by the extra oxide layer can be avoided in the operation process of the RRAM.
On the other hand, when the RRAM cell performs the SET operation, in addition to the forming current generated by the filament, FN tunneling may be induced between the variable resistance layer and the conductor layer around the oxygen exchange layer to generate the leakage current, so that the cycling window may be increased, the bias voltage during the RESET operation may be reduced, and the Complementary Switching (CS) effect may be avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A resistive random access memory, comprising:
a first electrode layer and a second electrode layer disposed opposite to each other;
a variable resistance layer between the first electrode layer and the second electrode layer;
an oxygen exchange layer located between the variable resistance layer and the second electrode layer;
a conductor layer laterally surrounding the periphery of the sidewall of the oxygen exchange layer;
a first barrier layer between the conductor layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer; and
a second barrier layer between the conductor layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
2. The resistive random access memory according to claim 1, wherein the conductor layer comprises a material that is less prone to bonding with oxygen than the oxygen exchange layer.
3. The resistive random access memory according to claim 1, wherein the material of the conductive layer comprises platinum, iridium, ruthenium, rhodium, tungsten, titanium, hafnium, tantalum, hafnium nitride, tantalum nitride, titanium nitride, tungsten nitride, or combinations thereof.
4. The resistive random access memory according to claim 1, further comprising a dielectric layer covering a top surface and sidewalls of the second electrode layer, the second barrier layer, the conductor layer, the variable resistance layer, and a plurality of sidewalls of the first electrode layer, and the dielectric layer and the oxygen exchange layer are separated by the conductor layer.
5. The resistive random access memory according to claim 1, wherein a top surface of the conductor layer is coplanar with a top surface of the second barrier layer and a top surface of the oxygen exchange layer.
6. The resistive random access memory according to claim 1, wherein a top surface of the conductor layer is coplanar with a bottom surface of the first barrier layer.
7. A method for manufacturing a resistive random access memory, comprising:
forming a variable resistance layer on the first electrode layer;
forming a conductor layer on the variable resistance layer;
forming an opening in the conductor layer;
forming a first barrier layer and an oxygen exchange layer in the opening;
forming a second barrier layer on the conductor layer and the oxygen exchange layer; and
and forming a second electrode layer on the second barrier layer.
8. The method of claim 7, further comprising: and patterning the second electrode layer, the second barrier layer, the conductor layer, the variable resistance layer and the first electrode layer to form a plurality of resistance random access memory cells.
9. The method of claim 8, further comprising forming a dielectric layer covering top surfaces and sidewalls of the plurality of RRAM cells.
CN202010733242.7A 2020-07-27 2020-07-27 Resistive random access memory and manufacturing method thereof Pending CN114005851A (en)

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Application Number Priority Date Filing Date Title
CN202010733242.7A CN114005851A (en) 2020-07-27 2020-07-27 Resistive random access memory and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114005851A true CN114005851A (en) 2022-02-01

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