CN114005418B - Common voltage generating circuit, display panel driving circuit and display device - Google Patents
Common voltage generating circuit, display panel driving circuit and display device Download PDFInfo
- Publication number
- CN114005418B CN114005418B CN202111273143.6A CN202111273143A CN114005418B CN 114005418 B CN114005418 B CN 114005418B CN 202111273143 A CN202111273143 A CN 202111273143A CN 114005418 B CN114005418 B CN 114005418B
- Authority
- CN
- China
- Prior art keywords
- circuit
- voltage
- power
- power supply
- trigger
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The utility model provides a public voltage produces circuit, display panel drive circuit and display device, wherein, public voltage produces the circuit and includes tank circuit, voltage-controlled switch circuit and trigger circuit, voltage-controlled switch circuit is direct to be connected with power management integrated circuit's power input end, the trigger circuit controls voltage-controlled switch circuit according to clock pulse signal correspondence and switches on and off, thereby output the electric current of corresponding size to tank circuit, realize the control to tank circuit's charge-discharge, and output the public voltage of corresponding size to display panel, because public voltage is produced by the input power supply that the display device produced the fastest, voltage and chronogenesis are adjusted more in a flexible way, and the input power supply has the working power supply that has more drive current than power management integrated circuit's output, thereby make public voltage generate the speed faster.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a common voltage generation circuit, a display panel driving circuit and a display device.
Background
The display device comprises a corresponding display panel and a display panel driving circuit, wherein the display panel driving circuit provides a source electrode driving signal, a grid electrode driving signal and a common voltage for displaying a corresponding image for the display panel.
Meanwhile, in a common display panel driving circuit, a power management integrated circuit is respectively connected to a timing controller, a source driving circuit, a gate driving circuit, and a common voltage generating circuit to provide respective required working power supplies.
However, the output timing of the common voltage generation circuit needs to follow the power management integrated circuit, the generation speed is slow, and the adjustment of the common voltage timing is not flexible.
Disclosure of Invention
The application aims to provide a public voltage generating circuit and aims to solve the problem that the timing adjustment of a traditional public voltage generating circuit is not flexible.
A first aspect of an embodiment of the present application provides a common voltage generation circuit, including:
the power supply end of the energy storage circuit forms the power supply output end of the public voltage generating circuit and is connected with the public voltage signal end of the display panel;
the power supply input end of the voltage-controlled switch circuit forms the power supply input end of the public voltage generating circuit and is connected with the power supply input end of the power supply management integrated circuit, the power supply output end of the voltage-controlled switch circuit is connected with the power supply end of the energy storage circuit, and the voltage-controlled switch circuit is used for being correspondingly switched on and switched off according to high and low level signals received by the controlled end and outputting current signals with corresponding sizes to the energy storage circuit so as to charge and discharge the energy storage circuit;
the signal input end of the trigger circuit is used for receiving a clock pulse signal, the signal output end of the trigger is connected with the controlled end of the voltage-controlled switch circuit, and the trigger circuit is triggered by the level change of the clock pulse signal to output high and low level signals corresponding to the voltage-controlled switch circuit.
Optionally, the trigger circuit includes a T-trigger, a first resistor, a first electronic switching tube, and a second electronic switching tube;
the clock signal end of the T trigger is used for receiving a clock pulse signal, the input end and the positive power end of a first electronic switching tube are connected in common and used for inputting a positive voltage with a preset voltage, the output end of the T trigger, the controlled end of the first electronic switching tube and the controlled end of a second electronic switching tube are interconnected, the output end of the first electronic switching tube, the input end of the second electronic switching tube and the first end of a first resistor are connected in common to form a signal output end of the trigger circuit, and the output end of the second electronic switching tube and the second end of the first resistor are grounded;
the first electronic switch tube receives high level turn-on and receives low level turn-off, the second electronic switch tube receives high level turn-off and receives low level turn-on, and the input end of the T trigger is connected with the input end of the first electronic switch tube;
or, the first electronic switch tube receives high level turn-off and receives low level turn-on, the second electronic switch tube receives high level turn-on and receives low level turn-off, and the input end of the T trigger is connected with the output end of the first electronic switch tube.
Optionally, the trigger circuit includes a D trigger, a second resistor, a third electronic switching tube, and a fourth electronic switching tube;
a clock signal end of the D flip-flop is configured to receive a clock pulse signal, an input end and a positive power end of a third electronic switching tube are commonly connected and configured to input a positive voltage of a preset voltage, an output end of the D flip-flop, a controlled end of the third electronic switching tube and a controlled end of a fourth electronic switching tube are interconnected, an output end of the third electronic switching tube, an input end of the fourth electronic switching tube, a first end of the second resistor and an input end of the D flip-flop are commonly connected to form a signal output end of the flip-flop circuit, and an output end of the fourth electronic switching tube and a second end of the second resistor are grounded;
the third electronic switch tube receives high-level turn-off and receives low-level turn-on, and the fourth electronic switch tube receives high-level turn-on and receives low-level turn-off.
Optionally, the common voltage generating circuit further comprises:
the power supply output end of the power supply conversion circuit is connected with the positive power supply end, and the power supply conversion circuit is used for converting a direct-current power supply input by the voltage-controlled switch circuit into a positive voltage with a preset voltage to the positive power supply end.
Optionally, the voltage-controlled switching circuit comprises a field effect transistor;
the input end, the output end and the controlled end of the field effect triode respectively form a power input end, a power output end and a controlled end of the voltage-controlled switch circuit.
Optionally, the energy storage circuit includes an energy storage capacitor, a first end of the energy storage capacitor constitutes a power supply end of the energy storage circuit, and a second end of the energy storage capacitor is grounded.
Optionally, the common voltage generating circuit further comprises a voltage stabilizing circuit, the voltage stabilizing circuit comprises a voltage stabilizing tube, a cathode of the voltage stabilizing tube is connected with a power input end of the voltage controlled switch circuit, and an anode of the voltage stabilizing tube is grounded.
Optionally, the common voltage generating circuit further includes a unidirectional turn-on circuit, the unidirectional turn-on circuit includes a diode, an anode of the diode is connected to the power output terminal of the voltage-controlled switching circuit, and a cathode of the diode is connected to the power supply terminal of the energy storage circuit.
A second aspect of the embodiments of the present application provides a display panel driving circuit, including a power management integrated circuit, a timing controller, a source driving circuit, a gate driving circuit, and the common voltage generating circuit as described above;
the power output end of the power management integrated circuit is respectively connected with the power end of the time schedule controller, the power end of the source electrode driving circuit and the power end of the grid electrode driving circuit, the power input end of the public voltage generating circuit is connected with the power input end of the power management integrated circuit, the time schedule controller is also respectively connected with the source electrode driving circuit and the grid electrode driving circuit, and the source electrode driving circuit, the grid electrode driving circuit and the public voltage generating circuit are also respectively connected with the display panel.
A third aspect of the embodiments of the present application provides a display device, which includes a backlight module, a display panel, and the display panel driving circuit as described above, where the display panel is correspondingly connected to the display panel driving circuit.
The embodiment of the application forms a public voltage generating circuit by adopting the energy storage circuit, the voltage-controlled switch circuit and the trigger circuit, the voltage-controlled switch circuit is directly connected with the power input end of the power management integrated circuit, the trigger circuit controls the voltage-controlled switch circuit to be correspondingly switched on and switched off according to the clock pulse signal, thereby outputting the current with the corresponding size to the energy storage circuit, the control of charging and discharging of the energy storage circuit is realized, and outputting the public voltage with the corresponding size to the display panel, because the public voltage is generated by the input power supply generated by the display device at the fastest speed, the voltage and the time sequence adjustment are more flexible, and the input power supply has larger driving current than the working power supply of the output of the power management integrated circuit, thereby the public voltage generation speed is faster.
Drawings
Fig. 1 is a schematic block diagram of a display panel driving circuit according to a first embodiment of the present disclosure;
fig. 2 is a circuit schematic diagram of a common voltage generating circuit according to a second embodiment of the present application;
fig. 3 is a circuit schematic diagram of a common voltage generating circuit according to a third embodiment of the present application;
fig. 4 is a circuit schematic diagram of a common voltage generating circuit according to a fourth embodiment of the present application;
fig. 5 is a schematic block diagram of a power conversion circuit provided in a fifth embodiment of the present application;
fig. 6 is a schematic circuit structure diagram of a first common voltage generation circuit provided in a sixth embodiment and a seventh embodiment of the present application;
fig. 7 is a circuit schematic diagram of a second common voltage generation circuit provided in a sixth embodiment and a seventh embodiment of the present application;
fig. 8 is a schematic circuit diagram of a third common voltage generating circuit provided in a sixth embodiment and a seventh embodiment of the present application;
fig. 9 is a schematic block diagram of a display panel driving circuit according to an eighth embodiment of the present application;
fig. 10 is a schematic block diagram of a display device according to a ninth embodiment of the present application.
Wherein, in the figures, the respective reference numerals:
100-display panel driving circuit, 200-display panel, 300-backlight module, 10-common voltage generating circuit, 20-power management integrated circuit, 30-time schedule controller, 40-source electrode driving circuit, 50-grid electrode driving circuit, 10-trigger circuit, 20-voltage control switching circuit, 13-energy storage circuit, 14-power switching circuit, 15-voltage stabilizing circuit, 16-unidirectional conduction circuit, U1-T trigger, U2-D trigger, Q1-first electronic switching tube, Q2-second electronic switching tube, Q3-field effect transistor, Q4-third electronic switching tube, Q5-fourth electronic switching tube, R1-first resistor, R2-second resistor, C1-energy storage capacitor, D1-voltage stabilizing tube, d2-diode, CP-clock signal, VIN-input voltage, VDD-positive voltage, VCOM-common voltage.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
The first aspect of the embodiments of the present application provides a common voltage generating circuit 10, configured to output a common voltage VCOM to a display panel 200 to provide a reference voltage for ac driving of liquid crystal, where the common voltage VCOM is generally 6V to 8V.
As shown in fig. 1, in the present embodiment, the common voltage generating circuit 10 includes:
a power supply end of the energy storage circuit 13 forms a power supply output end of the common voltage generating circuit 10 and is connected with a common voltage signal end of the display panel 200;
the power input end of the voltage-controlled switch circuit 12 forms the power input end of the common voltage generating circuit 10 and is connected with the power input end of the power management integrated circuit 20, the power output end of the voltage-controlled switch circuit 12 is connected with the power end of the energy storage circuit 13, and the voltage-controlled switch circuit 12 is used for correspondingly switching on and off according to high and low level signals received by the controlled end and outputting current signals with corresponding sizes to the energy storage circuit 13 so as to charge and discharge the energy storage circuit 13;
and a signal input end of the trigger circuit 11 is used for receiving a clock pulse signal CP, a signal output end of the trigger is connected with a controlled end of the voltage-controlled switch circuit 12, and the trigger circuit 11 is triggered by level change of the clock pulse signal CP to output high and low level signals with corresponding voltage magnitude to the voltage-controlled switch circuit 12.
In this embodiment, the flip-flop circuit 11 sequentially outputs different high and low level signals corresponding to the voltage level to the voltage-controlled switch circuit 12 by inverting the output state according to the number of pulses or the rising edge and the falling edge of the received clock pulse signal CP.
The voltage-controlled switch circuit 12 belongs to a voltage-controlled current type circuit, i.e. the voltage of the controlled terminal determines the magnitude of the output current, when receiving the high-low level signal corresponding to the voltage of the trigger circuit 11, the voltage-controlled switch circuit 12 is turned on and off, and outputs a current corresponding to a high level or a low level when turned on, the tank circuit 13 performs tank charging when the voltage-controlled switch circuit 12 is turned on, and discharges the output when the voltage-controlled switch circuit 12 is turned off, by repeating the charge and discharge, the common voltage VCOM is generated and outputted to the display panel 200 to provide the reference voltage for AC driving of the liquid crystal, the pulse parameters of the clock pulse signal CP and the internal circuit structure of the flip-flop circuit 11 are designed correspondingly, so that the flip-flop circuit outputs a level signal corresponding to the required common voltage VCOM, thereby realizing the adjustment of the common voltage VCOM.
The flip-flop circuit 11 may adopt different flip-flop structures such as a T flip-flop U1 and a D flip-flop U2, and may further be matched with a corresponding level conversion device, where the specific structure and the input signal are correspondingly set according to the output current of the voltage-controlled switch circuit 12.
The energy storage circuit 13 may be a battery, a capacitor, or the like.
The voltage-controlled switch circuit 12 is directly connected to a Power input terminal of a Power Management IC (PMIC) 20, and when the display device is turned on, since the common voltage VCOM is generated by an input Power source generated by the display device at the fastest speed, an output of the voltage-controlled switch circuit 12 is synchronized with the Power Management IC 20 instead of following the Power Management IC 20, voltage and timing adjustment is more flexible, and the input Power source has a driving current larger than a working Power source of the output of the Power Management IC 20, so that the common voltage VCOM is generated at a faster speed.
The power output terminal of the power management integrated circuit 20 is further connected to the timing controller 30, the source driving circuit 40, and the gate driving circuit 50 required for driving the display panel 200, respectively, and forms the display panel driving circuit 100 with the common voltage generating circuit 10, and the voltage output by the power management integrated circuit 20 includes a digital operating voltage supplied to each IC, a gate-on voltage supplied to the gate driving circuit 50, and a gate-off voltage.
Example two
The present embodiment is detailed and embodied on the basis of the first embodiment, as shown in fig. 2, optionally, the flip-flop circuit 11 includes a T-flip-flop U1, a first resistor R1, a first electronic switch Q1, and a second electronic switch Q2;
a clock signal end of the T flip-flop U1 is used for receiving a clock pulse signal CP, an input end and a positive power end of the first electronic switch tube Q1 are commonly connected and used for inputting a positive voltage VDD of a preset voltage magnitude, an output end of the T flip-flop U1, a controlled end of the first electronic switch tube Q1 and a controlled end of the second electronic switch tube Q2 are interconnected, an output end of the first electronic switch tube Q1, an input end of the second electronic switch tube Q2 and a first end of the first resistor R1 are commonly connected to form a signal output end of the flip-flop circuit 11, and an output end of the second electronic switch tube Q2 and a second end of the first resistor R1 are grounded;
the first electronic switch tube Q1 receives high level turn-on and receives low level turn-off, the second electronic switch tube Q2 receives high level turn-off and receives low level turn-on, and the input end of the T trigger U1 is connected with the input end of the first electronic switch tube Q1.
The voltage-controlled switching circuit 12 comprises a field effect transistor Q3;
the input end, the output end and the controlled end of the field effect transistor Q3 respectively form a power supply input end, a power supply output end and a controlled end of the voltage-controlled switch circuit 12.
The energy storage circuit 13 comprises an energy storage capacitor C1, a first end of the energy storage capacitor C1 forms a power supply end of the energy storage circuit 13, and a second end of the energy storage capacitor C1 is grounded.
In this embodiment, the positive voltage VDD of the preset voltage is generated synchronously with the input voltage VIN, and may be led out from the output terminal of the corresponding power module in the display device or be a power-on power circuit provided independently, and provides the positive voltage VDD for the trigger circuit 11 when the display device is powered on.
When the display device is started, a positive voltage VDD is output to an input end of a T trigger U1, T is 1, if no pulse signal occurs in a clock pulse signal CP at the moment, the T trigger U1 outputs a low level, a first electronic switching tube Q1 is turned off, a second electronic switching tube Q2 is turned on, and a field effect triode Q3 is grounded and turned off through a second electronic switching tube Q2.
When a first pulse signal of the clock pulse signal CP comes, the output state of the T-flip-flop U1 is inverted, a high level is output, the first electronic switch Q1 and the field effect transistor Q3 are turned on, the second electronic switch Q2 is turned off, the input voltage VIN charges the energy storage capacitor C1 through the field effect transistor Q3, when a second pulse signal comes, the output state of the T-flip-flop U1 is inverted again, the T-flip-flop U1 outputs a low level, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, the field effect transistor Q3 is turned off through the second electronic switch Q2, the energy storage capacitor C1 discharges, when a third pulse signal comes, the energy storage capacitor C1 charges, and the energy storage capacitor C1 switches the charging and discharging state with the continuous output of the pulse signal, thereby generating the common voltage VCOM.
The magnitude of the positive voltage VDD determines the output current of the fet Q3, the interval time of the pulse signal determines the charging time of the energy storage capacitor C1, and the magnitude of the common voltage VCOM is determined by the charging current and the charging/discharging time of the energy storage capacitor C1, so that the common voltage VCOM of a desired magnitude can be obtained by properly selecting the magnitude of the positive voltage VDD and the parameters of the clock signal CP.
To further provide output security and prevent jitter in the output of the common voltage VCOM during shutdown, optionally, the number of pulses is kept even during the time of startup and shutdown, i.e., the fet Q3 is always turned off during shutdown, isolating the input voltage VIN from the common voltage VCOM.
In order to match the conduction requirement and the switching frequency, optionally, the first electronic switching transistor Q1 and the fet Q3 are N-channel fets, and the second electronic switching transistor Q2 is a P-channel fet.
The positive voltage VDD changes according to the input voltage VIN, when the display device is started, the positive voltage VDD is synchronously generated along with the input voltage VIN and can be provided by an independent power circuit, the independent power circuit synchronously acts along with the startup and shutdown of the display device, namely, when the display device is started, the power circuit outputs the positive voltage VDD, and when the display device is shut down, the power circuit is shut down to output, or the positive voltage VDD is converted and output by the input voltage VIN through the power conversion circuit 14, so that the output state following is realized.
Since the common voltage VCOM is generated by the input voltage VIN, and the dc voltage of the logic level is rapidly established under the control of the positive voltage VDD, the timing of the common voltage VCOM can be established according to the clock pulse signal CP of the T flip-flop U1 and the positive voltage VDD, so as to realize the adjustable output timing and magnitude.
EXAMPLE III
The present embodiment is detailed and embodied on the basis of the first embodiment, as shown in fig. 3, optionally, the flip-flop circuit 11 includes a T-flip-flop U1, a first resistor R1, a first electronic switch Q1, and a second electronic switch Q2;
a clock signal end of the T flip-flop U1 is used for receiving a clock pulse signal CP, an input end and a positive power end of the first electronic switch tube Q1 are commonly connected and used for inputting a positive voltage VDD of a preset voltage magnitude, an output end of the T flip-flop U1, a controlled end of the first electronic switch tube Q1 and a controlled end of the second electronic switch tube Q2 are interconnected, an output end of the first electronic switch tube Q1, an input end of the second electronic switch tube Q2 and a first end of the first resistor R1 are commonly connected to form a signal output end of the flip-flop circuit 11, and an output end of the second electronic switch tube Q2 and a second end of the first resistor R1 are grounded;
the first electronic switching tube Q1 receives high level turn-on and receives low level turn-off, the second electronic switching tube Q2 receives high level turn-off and receives low level turn-on, and the input end of the T trigger U1 is connected with the input end of the first electronic switching tube Q1;
the first electronic switch tube Q1 receives high level turn-off and receives low level turn-on, the second electronic switch tube Q2 receives high level turn-on and receives low level turn-off, and the input end of the T trigger U1 is connected with the output end of the first electronic switch tube Q1.
The voltage-controlled switching circuit 12 comprises a field effect transistor Q3;
the input end, the output end and the controlled end of the field effect transistor Q3 respectively form a power supply input end, a power supply output end and a controlled end of the voltage-controlled switch circuit 12.
The energy storage circuit 13 comprises an energy storage capacitor C1, a first terminal of the energy storage capacitor C1 forms a power supply terminal of the energy storage circuit 13, and a second terminal of the energy storage circuit 13 is grounded.
In this embodiment, the positive voltage VDD of the preset voltage is generated synchronously with the input voltage VIN, and may be led out from the output terminal of the corresponding power module in the display device or be an independently arranged power circuit, and provides the positive voltage VDD for the trigger circuit 11 when the display device is turned on.
When the display device is started, a positive voltage VDD is output to an input end of a first electronic switching tube Q1, T is 0, if no pulse signal occurs in a clock pulse signal CP at the moment, a T trigger U1 outputs a low level, the first electronic switching tube Q1 is conducted, a second electronic switching tube Q2 is turned off, a field effect transistor Q3 is conducted, an input voltage VIN charges an energy storage capacitor C1 through a field effect transistor Q3, and T is 1 at the moment.
When the first pulse signal of the clock pulse signal CP arrives, the output state of the T-flip-flop U1 is inverted, a high level is output, the first electronic switching tube Q1 is turned off, the second electronic switching tube Q2 is turned on, the field-effect transistor Q3 is grounded and turned off through the second electronic switching tube Q2, and the energy storage capacitor C1 discharges.
When the second pulse signal arrives, the energy storage capacitor C1 charges, and the energy storage capacitor C1 switches the charge and discharge state with the continuous output of the pulse signal, thereby generating the common voltage VCOM.
The magnitude of the positive voltage VDD determines the output current of the fet Q3, the interval time of the pulse signal determines the charging time of the energy storage capacitor C1, and the magnitude of the common voltage VCOM is determined by the charging current and the charging/discharging time of the energy storage capacitor C1, so that the common voltage VCOM of a desired magnitude can be obtained by properly selecting the magnitude of the positive voltage VDD and the parameters of the clock signal CP.
To further provide output security and prevent jitter in the output of the common voltage VCOM during shutdown, optionally, the number of pulses is kept odd during the time of startup and shutdown, i.e., the fet Q3 is always turned off during shutdown, isolating the input voltage VIN from the common voltage VCOM.
In order to match the conduction requirement and the switching frequency, optionally, the second electronic switching transistor Q2 and the fet Q3 are N-channel fets, and the first electronic switching transistor Q1 is a P-channel fet.
The positive voltage VDD changes according to the input voltage VIN, when the display device is started, the positive voltage VDD is synchronously generated along with the input voltage VIN and can be provided by an independent power circuit, the independent power circuit synchronously acts along with the startup and shutdown of the display device, namely, when the display device is started, the power circuit outputs the positive voltage VDD, when the display device is shut down, the power circuit is shut down to output, or the positive voltage VDD is converted and output by the input voltage VIN through the power conversion circuit 14, so that the output state following is realized.
Since the common voltage VCOM is generated by the input voltage VIN, and the dc voltage of the logic level is rapidly established under the control of the positive voltage VDD, the timing of the common voltage VCOM can be established according to the clock pulse signal CP of the T flip-flop U1 and the positive voltage VDD, so as to realize the adjustable output timing and magnitude.
Example four
The present embodiment is detailed and embodied on the basis of the first embodiment, as shown in fig. 4, optionally, the flip-flop circuit 11 includes a D flip-flop U2, a second resistor R2, a third electronic switch Q4, and a fourth electronic switch Q5;
a clock signal end of the D flip-flop U2 is configured to receive a clock pulse signal CP, an input end and a positive power end of the third electronic switch Q4 are commonly connected and configured to input a positive voltage VDD of a preset voltage magnitude, an output end of the D flip-flop U2, a controlled end of the third electronic switch Q4, and a controlled end of the fourth electronic switch Q5 are interconnected, an output end of the third electronic switch Q4, an input end of the fourth electronic switch Q5, a first end of the second resistor R2, and an input end of the D flip-flop U2 are commonly connected to form a signal output end of the flip-flop circuit 11, and an output end of the fourth electronic switch Q5 and a second end of the second resistor R2 are grounded;
the third electronic switch Q4 receives a high-level turn-off and receives a low-level turn-on, and the fourth electronic switch Q5 receives a high-level turn-on and receives a low-level turn-off.
The voltage-controlled switching circuit 12 comprises a field effect transistor Q3;
the input end, the output end and the controlled end of the field effect transistor Q3 respectively form a power supply input end, a power supply output end and a controlled end of the voltage-controlled switch circuit 12.
The energy storage circuit 13 comprises an energy storage capacitor C1, a first terminal of the energy storage capacitor C1 forms a power supply terminal of the energy storage circuit 13, and a second terminal of the energy storage circuit 13 is grounded.
In this embodiment, the output state of the D flip-flop U2 depends on the state at the end of the time point D when the rising edge of the pulse signal reaches, that is, when D is 1, the rising edge of the pulse signal arrives, the D flip-flop U2 outputs a high level, and when D is 0, if the last state Q is 0, whenever CLK arrives, the next state Q is 0, and if Q is 1, the next state Q is 1.
In operation, in an initial state, the D flip-flop U2 outputs a low level, the third electronic switching transistor Q4 and the field effect transistor Q3 are turned on, the input voltage VIN charges the energy storage capacitor C1 through the field effect transistor Q3, and meanwhile, the input end D of the D flip-flop U2 changes to 1.
When the rising edge comes, at this time, the output of the D flip-flop U2 is 1, the third electronic switching tube Q4 is turned off, the fourth electronic switching tube Q5 is turned on, the field-effect transistor Q3 is turned off, at this time, the energy storage capacitor C1 discharges, and at this time, the input end of the D flip-flop U2 is 0.
When the rising edge of the next pulse signal arrives, at this time, the output of the D flip-flop U2 is 0, the third electronic switch Q4 and the field effect transistor Q3 are turned on, the input voltage VIN charges the energy storage capacitor C1 through the field effect transistor Q3, and meanwhile, the input end D of the D flip-flop U2 changes to 1, and the charging and discharging control of the energy storage capacitor C1 is realized by repeatedly switching, so that the common voltage VCOM is generated.
In order to match the conduction requirement and the switching frequency, optionally, the fourth electronic switching transistor Q5 and the fet Q3 are N-channel fets, and the third electronic switching transistor Q4 is a P-channel fet.
EXAMPLE five
In this embodiment, optimization is performed on the basis of the second to fourth embodiments, as shown in fig. 5, in order to ensure that the positive voltage VDD is reliably established and the line structure is reduced, optionally, the common voltage generating circuit 10 further includes:
the power supply input end of the power supply conversion circuit 14 is connected with the power supply input end of the voltage-controlled switch circuit 12, the power supply output end of the power supply conversion circuit 14 is connected with the positive power supply end, and the power supply conversion circuit 14 is used for converting a direct-current power supply input by the voltage-controlled switch circuit 12 into a positive voltage VDD with a preset voltage magnitude to the positive power supply end.
In this embodiment, the positive voltage VDD is converted and output from the input voltage VIN through the power conversion circuit 14, the state of the positive voltage VDD changes along with the state of the input voltage VIN, that is, the input voltage VIN and the positive voltage VDD are synchronously established when the power is turned on, the input voltage VIN and the positive voltage VDD disappear when the power is turned off, the common voltage VCOM is generated from the input voltage VIN, and the dc voltage with the logic level is quickly established under the control of the positive voltage VDD, so that the timing sequence of the common voltage VCOM can be established according to the clock pulse signal CP of the T flip-flop U1 and the positive voltage VDD, and the output timing sequence and the size can be adjusted.
The power conversion circuit 14 may be a voltage regulator circuit, a BUCK circuit, or the like, and the specific structure is not limited.
EXAMPLE six
In order to improve the input safety and avoid the fluctuation of the input voltage VIN, as shown in fig. 6 to 8, the common voltage generating circuit 10 further includes a voltage stabilizing circuit 15, optionally, the voltage stabilizing circuit 15 includes a voltage regulator tube D1, a cathode of the voltage regulator tube D1 is connected to the power input terminal of the voltage controlled switch circuit 12, and an anode of the voltage regulator tube D1 is grounded.
It can be understood that, when the display device is turned on, the input voltage VIN may have unstable voltage due to unstable current during the turning on, and because the voltage regulator D1 is provided to stabilize the input voltage VIN, the problem that the electronic switch tube is damaged due to the input voltage VIN changing along with the input current is prevented, and the safety and reliability are improved.
EXAMPLE seven
The present embodiment is optimized based on the second to the fourth embodiments, as shown in fig. 6 to 8, optionally, the common voltage generating circuit 10 further includes a unidirectional conducting circuit 16, the unidirectional conducting circuit 16 includes a diode D2, an anode of the diode D2 is connected to the power supply output terminal of the voltage controlled switching circuit 12, and a cathode of the diode D2 is connected to the power supply terminal of the energy storage circuit 13.
In this embodiment, the diode D2 realizes unidirectional output of the output current of the electronic switch tube, thereby preventing the current of the energy storage capacitor C1 from flowing back to the electronic switch tube to cause damage to the electronic switch tube, improving the output stability of the common voltage VCOM, and avoiding the problem of flickering shutdown pictures.
Example eight
As shown in fig. 9, the display panel driving circuit 100 includes a power management integrated circuit 20, a timing controller 30, a source driving circuit 40, a gate driving circuit 50, and a common voltage generating circuit 10, and the specific structure of the common voltage generating circuit 10 refers to the above embodiments, and since the display panel driving circuit 100 adopts all the technical solutions of all the above embodiments, the display panel driving circuit at least has all the beneficial effects brought by the technical solutions of the above embodiments, and no further description is given here.
The power output terminal of the power management integrated circuit 20 is connected to the power source terminal of the timing controller 30, the power source terminal of the source driver circuit 40, and the power source terminal of the gate driver circuit 50, the power input terminal of the common voltage generator circuit 10 is connected to the power input terminal of the power management integrated circuit 20, the timing controller 30 is further connected to the source driver circuit 40 and the gate driver circuit 50, and the source driver circuit 40, the gate driver circuit 50, and the common voltage generator circuit 10 are further connected to the display panel 200.
In this embodiment, the power management integrated circuit 20, the timing controller 30, the source driving circuit 40, the gate driving circuit 50 and the common voltage generating circuit 10 form the display panel driving circuit 100 to provide the source driving signal, the gate driving signal and the common voltage VCOM required for driving the display panel 200.
The common voltage generating circuit 10 is directly connected to the power input terminal of the power management integrated circuit 20, when the display device is turned on, since the common voltage VCOM is generated by the input power generated by the display device fastest, the output of the common voltage generating circuit 10 is synchronized with the power management integrated circuit 20 instead of following the power management integrated circuit 20, the voltage and timing adjustment is more flexible, and the input power has a larger driving current than the operating power of the output of the power management integrated circuit 20, thereby making the generation speed of the common voltage VCOM faster.
The power output terminal of the power management integrated circuit 20 is further connected to the timing controller 30, the source driver circuit 40, and the gate driver circuit 50 required for driving the display panel 200, respectively, and forms the display panel driver circuit 100 with the common voltage VCOM circuit 10, and the voltage output by the power management integrated circuit 20 includes a digital operating voltage supplied to each IC, a gate-on voltage supplied to the gate driver circuit 50, and a gate-off voltage.
Example nine
The present application further provides a display device, which includes a backlight module 300, a display panel 200 and a display panel driving circuit 100, wherein the specific structure of the display panel driving circuit 100 refers to the above embodiments, and since the display device adopts all technical solutions of all the above embodiments, the display device at least has all the beneficial effects brought by the technical solutions of the above embodiments, and is not repeated herein, wherein the display panel 200 is correspondingly connected to the display panel driving circuit 100.
In this embodiment, the display panel driving circuit 100 performs line-by-line scanning lighting on the display panel 200 to realize normal driving, and cooperates with the backlight module 300 to display corresponding image information.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A common voltage generation circuit, comprising:
the power supply end of the energy storage circuit forms the power supply output end of the public voltage generating circuit and is connected with the public voltage signal end of the display panel;
the power supply input end of the voltage-controlled switch circuit forms the power supply input end of the public voltage generating circuit and is connected with the power supply input end of the power supply management integrated circuit, the power supply output end of the voltage-controlled switch circuit is connected with the power supply end of the energy storage circuit, and the voltage-controlled switch circuit is used for being correspondingly switched on and switched off according to high and low level signals received by the controlled end and outputting current signals with corresponding sizes to the energy storage circuit so as to charge and discharge the energy storage circuit;
the signal input end of the trigger circuit is used for receiving a clock pulse signal, the signal output end of the trigger is connected with the controlled end of the voltage-controlled switch circuit, and the trigger circuit is triggered by the level change of the clock pulse signal to output high and low level signals corresponding to the voltage-controlled switch circuit.
2. The common voltage generating circuit of claim 1, wherein said trigger circuit comprises a T-trigger, a first resistor, a first electronic switching tube and a second electronic switching tube;
the clock signal end of the T trigger is used for receiving a clock pulse signal, the input end and the positive power end of a first electronic switching tube are connected in common and used for inputting a positive voltage with a preset voltage, the output end of the T trigger, the controlled end of the first electronic switching tube and the controlled end of a second electronic switching tube are interconnected, the output end of the first electronic switching tube, the input end of the second electronic switching tube and the first end of a first resistor are connected in common to form a signal output end of the trigger circuit, and the output end of the second electronic switching tube and the second end of the first resistor are grounded;
the first electronic switch tube receives high level turn-on and receives low level turn-off, the second electronic switch tube receives high level turn-off and receives low level turn-on, and the input end of the T trigger is connected with the input end of the first electronic switch tube;
or, the first electronic switch tube receives high level turn-off and receives low level turn-on, the second electronic switch tube receives high level turn-on and receives low level turn-off, and the input end of the T trigger is connected with the output end of the first electronic switch tube.
3. The common voltage generating circuit as claimed in claim 1, wherein said trigger circuit comprises a D-flip-flop, a second resistor, a third electronic switching tube and a fourth electronic switching tube;
the clock signal end of the D trigger is used for receiving a clock pulse signal, the input end and the positive power end of a third electronic switching tube are connected in common and used for inputting a positive voltage with a preset voltage, the output end of the D trigger, the controlled end of the third electronic switching tube and the controlled end of a fourth electronic switching tube are interconnected, the output end of the third electronic switching tube, the input end of the fourth electronic switching tube, the first end of the second resistor and the input end of the D trigger are connected in common to form a signal output end of the trigger circuit, and the output end of the fourth electronic switching tube and the second end of the second resistor are grounded;
the third electronic switch tube receives high level turn-off and receives low level turn-on, and the fourth electronic switch tube receives high level turn-on and receives low level turn-off.
4. The common voltage generating circuit according to claim 2 or 3, wherein the common voltage generating circuit further comprises:
the power supply conversion circuit is used for converting a direct-current power supply input by the voltage-controlled switch circuit into a positive voltage with a preset voltage to the positive power supply end.
5. The common voltage generating circuit according to claim 2 or 3, wherein the voltage controlled switching circuit comprises a field effect transistor;
the input end, the output end and the controlled end of the field effect triode respectively form a power input end, a power output end and a controlled end of the voltage-controlled switch circuit.
6. A common voltage generating circuit according to claim 2 or 3, wherein said energy storage circuit comprises an energy storage capacitor, a first terminal of said energy storage capacitor constituting a power supply terminal of said energy storage circuit, a second terminal of said energy storage capacitor being connected to ground.
7. The common voltage generating circuit according to claim 2 or 3, wherein the common voltage generating circuit further comprises a voltage stabilizing circuit, the voltage stabilizing circuit comprises a voltage regulator tube, a cathode of the voltage regulator tube is connected with a power input end of the voltage controlled switch circuit, and an anode of the voltage regulator tube is grounded.
8. A common voltage generating circuit as claimed in claim 2 or 3, further comprising a unidirectional conducting circuit comprising a diode, the anode of the diode being connected to the power supply output terminal of the voltage controlled switching circuit, the cathode of the diode being connected to the power supply terminal of the tank circuit.
9. A display panel driving circuit comprising a power management integrated circuit, a timing controller, a source driving circuit, a gate driving circuit, and the common voltage generating circuit according to any one of claims 1 to 8;
the power output end of the power management integrated circuit is respectively connected with the power end of the time schedule controller, the power end of the source electrode driving circuit and the power end of the grid electrode driving circuit, the power input end of the public voltage generating circuit is connected with the power input end of the power management integrated circuit, the time schedule controller is also respectively connected with the source electrode driving circuit and the grid electrode driving circuit, and the source electrode driving circuit, the grid electrode driving circuit and the public voltage generating circuit are also respectively connected with the display panel.
10. A display device comprising a backlight module, a display panel and the display panel driving circuit as claimed in claim 9, wherein the display panel is connected with the display panel driving circuit correspondingly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111273143.6A CN114005418B (en) | 2021-10-29 | 2021-10-29 | Common voltage generating circuit, display panel driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111273143.6A CN114005418B (en) | 2021-10-29 | 2021-10-29 | Common voltage generating circuit, display panel driving circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114005418A CN114005418A (en) | 2022-02-01 |
| CN114005418B true CN114005418B (en) | 2022-09-20 |
Family
ID=79925242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111273143.6A Active CN114005418B (en) | 2021-10-29 | 2021-10-29 | Common voltage generating circuit, display panel driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114005418B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928005A (en) * | 2014-01-27 | 2014-07-16 | 深圳市华星光电技术有限公司 | GOA unit, drive circuit and array for jointly driving grid electrode and common electrode |
| CN109243393A (en) * | 2018-10-29 | 2019-01-18 | 惠科股份有限公司 | Driving circuit and display drive apparatus |
| CN109285526A (en) * | 2018-12-14 | 2019-01-29 | 惠科股份有限公司 | Charging circuit, display panel, drive circuit and display device |
| CN109559702A (en) * | 2019-01-15 | 2019-04-02 | 合肥鑫晟光电科技有限公司 | Public electrode voltages control circuit and driving method, display panel |
| CN209070958U (en) * | 2018-12-12 | 2019-07-05 | 惠科股份有限公司 | Public electrode voltages generation circuit and display device |
| CN213904905U (en) * | 2020-12-30 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Common electrode discharge unit of display array and liquid crystal display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI413080B (en) * | 2009-06-22 | 2013-10-21 | Chunghwa Picture Tubes Ltd | Common voltage generating circuit of an lcd |
-
2021
- 2021-10-29 CN CN202111273143.6A patent/CN114005418B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928005A (en) * | 2014-01-27 | 2014-07-16 | 深圳市华星光电技术有限公司 | GOA unit, drive circuit and array for jointly driving grid electrode and common electrode |
| CN109243393A (en) * | 2018-10-29 | 2019-01-18 | 惠科股份有限公司 | Driving circuit and display drive apparatus |
| CN209070958U (en) * | 2018-12-12 | 2019-07-05 | 惠科股份有限公司 | Public electrode voltages generation circuit and display device |
| CN109285526A (en) * | 2018-12-14 | 2019-01-29 | 惠科股份有限公司 | Charging circuit, display panel, drive circuit and display device |
| CN109559702A (en) * | 2019-01-15 | 2019-04-02 | 合肥鑫晟光电科技有限公司 | Public electrode voltages control circuit and driving method, display panel |
| CN213904905U (en) * | 2020-12-30 | 2021-08-06 | 昆山龙腾光电股份有限公司 | Common electrode discharge unit of display array and liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114005418A (en) | 2022-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6278318B1 (en) | Booster circuit associated with low-voltage power source | |
| US7375722B2 (en) | Driving circuit and display device | |
| TW529003B (en) | Power voltage conversion circuit and its control method, display device and portable terminal apparatus | |
| TWI431603B (en) | Boost converter for liquid crystal display | |
| US7561154B2 (en) | Power supply circuit and display system | |
| JPH0997925A (en) | Light-emitting element driver circuit | |
| TWI351809B (en) | Apparatus for driving a display and method of usin | |
| CN215770465U (en) | Display driving circuit and display device | |
| KR101464076B1 (en) | Driving circuit for display panel | |
| KR102661084B1 (en) | Electronic Device Capable of Reducing Color Shift | |
| CN114005418B (en) | Common voltage generating circuit, display panel driving circuit and display device | |
| TWI299148B (en) | Liquid crystal display and integrated driver circuit thereof | |
| CN217238692U (en) | LCD driving circuit | |
| US20130106822A1 (en) | Display device and method for controlling display device | |
| KR101685908B1 (en) | Apparatus for supplying power, back light unit and display apparatus using the same | |
| CN110311556B (en) | Power module, power control circuit and method for improving insufficient discharge of display panel | |
| EP4390903A1 (en) | Driving circuit of display panel and driving device | |
| CN106655727B (en) | Device and method for reducing power consumption of solar bypass switch circuit | |
| JP2004229434A (en) | Dc-dc converter, integrated circuit and flat display device | |
| US6376934B1 (en) | Voltage waveform generator | |
| KR20080046934A (en) | Liquid crystal display and method of driving the same | |
| KR101143608B1 (en) | Power module for energy recovery and sustain of plasma display panel | |
| WO2024098979A1 (en) | Driving circuit, active stylus and touch chip | |
| CN114822443B (en) | Driving method of LCD driving circuit | |
| CN214959288U (en) | Circuit for converting positive voltage into negative voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |