CN113990238A - Shift register - Google Patents
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- CN113990238A CN113990238A CN202111452144.7A CN202111452144A CN113990238A CN 113990238 A CN113990238 A CN 113990238A CN 202111452144 A CN202111452144 A CN 202111452144A CN 113990238 A CN113990238 A CN 113990238A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a shift register. The shift register comprises an output adjusting module, a first node and a second node, wherein the output adjusting module is used for outputting a first power supply signal from an output end of the shift register according to the potential of the first node and outputting a second power supply signal according to the potential of the second node; the first coupling module is used for coupling the signal of the output end of the shift register to a second node; the node adjusting module is used for adjusting the potential of the first node, and comprises a power supply introducing submodule, an adjusting submodule and a second coupling module, wherein the power supply introducing submodule is used for writing a first power supply signal into a control end of the adjusting submodule according to a trigger signal, the adjusting submodule is used for writing a clock signal into the first node according to the potential of the control end of the adjusting submodule, and the second coupling module is used for coupling the clock signal to the control end of the adjusting submodule; and the trigger writing module is used for writing the trigger signal into the second node according to the clock signal. The invention can output an output signal with longer duration.
Description
Technical Field
The embodiment of the invention relates to a shift register technology, in particular to a shift register.
Background
The shift register can output the trigger signal after shifting to a certain extent, has an important role in the field of display panels, and can provide a required scanning signal for a pixel circuit in the display panel.
However, the conventional pixel circuit suitable for low refresh frequency and weak image sticking problem usually needs one scan signal with long pulse duration, and the conventional shift register cannot output the scan signal with long duration.
Disclosure of Invention
The invention provides a shift register, which can output an output signal with longer duration.
An embodiment of the present invention provides a shift register, including:
the output adjusting module is used for outputting a first power supply signal from the output end of the shift register according to the potential of a first node and outputting a second power supply signal from the output end of the shift register according to the potential of a second node;
the first coupling module is used for coupling the signal of the output end of the shift register to the second node;
the node adjusting module is used for adjusting the potential of the first node, and comprises a power supply lead-in submodule, an adjusting submodule and a second coupling module, wherein the power supply lead-in submodule is used for writing the first power supply signal into a control end of the adjusting submodule according to a trigger signal, the adjusting submodule is used for writing a clock signal into the first node according to the potential of the control end of the adjusting submodule, and the second coupling module is used for coupling the clock signal to the control end of the adjusting submodule;
and the trigger writing module is used for writing the trigger signal into the second node according to the clock signal.
Optionally, the trigger signal is configured to: the pulse duration of the trigger signal is greater than or equal to twice the period of the clock signal.
Optionally, a first end of the power supply lead-in sub-module is connected to the first power supply signal, a second end of the power supply lead-in sub-module is electrically connected to a control end of the adjusting sub-module, and the control end of the power supply lead-in sub-module is connected to the trigger signal;
the first end of the second coupling module is connected to the clock signal, and the second end of the second coupling module is electrically connected with the control end of the adjusting sub-module;
a first end of the trigger writing module is connected to the trigger signal, a second end of the trigger writing module is electrically connected to the second node, and a control end of the trigger writing module is connected to the clock signal;
the first end of the first coupling module is electrically connected with the output end of the shift register, and the second end of the first coupling module is electrically connected with the second node.
Optionally, the trigger writing module includes a first transistor, a first end of the first transistor is used as a first end of the trigger writing module, a second end of the first transistor is used as a second end of the trigger writing module, and a control end of the first transistor is used as a control end of the trigger writing module;
the power supply lead-in sub-module comprises a second transistor, wherein a first end of the second transistor is used as a first end of the power supply lead-in sub-module, a second end of the second transistor is used as a second end of the power supply lead-in sub-module, and a control end of the second transistor is used as a control end of the power supply lead-in sub-module;
the adjusting submodule comprises a third transistor, wherein a first end of the third transistor is used as a first end of the adjusting submodule, a second end of the third transistor is used as a second end of the adjusting submodule, and a control end of the third transistor is used as a control end of the adjusting submodule;
the first coupling module comprises a first capacitor, a first end of the first capacitor is used as a first end of the first coupling module, and a second end of the first capacitor is used as a second end of the first coupling module;
the second coupling module comprises a second capacitor, a first end of the second capacitor is used as a first end of the second coupling module, and a second end of the second capacitor is used as a second end of the second coupling module.
Optionally, the shift register further includes a feedback module, a first end of the feedback module is connected to the first power signal, a second end of the feedback module is electrically connected to the first node, a control end of the feedback module is electrically connected to the second node, and the feedback module is configured to write the first power signal into the first node according to a potential of the second node.
Optionally, the feedback module includes a fourth transistor, a first terminal of the fourth transistor is used as the first terminal of the feedback module, a second terminal of the fourth transistor is used as the second terminal of the feedback module, and a control terminal of the fourth transistor is used as the control terminal of the feedback module.
Optionally, the shift register further includes a normally open module, a second end of the trigger write-in module is electrically connected to the second node through the normally open module, wherein the second end of the trigger write-in module is electrically connected to a first end of the normally open module, a second end of the normally open module is electrically connected to the second node, and a control end of the normally open module is connected to the second power signal.
Optionally, the normally-on module includes a fifth transistor, a first end of the fifth transistor is used as the first end of the normally-on module, a second end of the fifth transistor is used as the second end of the normally-on module, and a control end of the fifth transistor is used as the control end of the normally-on module.
Optionally, the output adjusting module comprises: the system comprises a pull-up submodule, a pull-down submodule and a maintenance submodule;
a first end of the pull-up sub-module is connected to the first power supply signal, a second end of the pull-up sub-module is electrically connected with an output end of the shift register, and a control end of the pull-up sub-module is electrically connected with the first node;
the first end of the pull-down submodule is connected with the second power supply signal, the second end of the pull-down submodule is electrically connected with the output end of the shift register, and the control end of the pull-down submodule is electrically connected with the second node;
and the first end of the maintaining submodule is connected with the first power supply signal, and the second end of the maintaining submodule is electrically connected with the control end of the pull-up submodule.
Optionally, the pull-up sub-module includes a sixth transistor, a first terminal of the sixth transistor is used as the first terminal of the pull-up sub-module, a second terminal of the sixth transistor is used as the second terminal of the pull-up sub-module, and a control terminal of the sixth transistor is used as the control terminal of the pull-up sub-module;
the pull-down sub-module comprises a seventh transistor, wherein a first end of the seventh transistor is used as a first end of the pull-down sub-module, a second end of the seventh transistor is used as a second end of the pull-down sub-module, and a control end of the seventh transistor is used as a control end of the pull-down sub-module;
the first end of the third capacitor is used as the first end of the maintenance submodule, and the second end of the third capacitor is used as the second end of the maintenance submodule.
According to the technical scheme of the embodiment of the invention, the adopted shift register comprises an output adjusting module, a first power supply signal is output from the output end of the shift register according to the electric potential of a first node, and a second power supply signal is output from the output end of the shift register according to the electric potential of a second node; the first coupling module is used for coupling the signal of the output end of the shift register to a second node; the node adjusting module is used for adjusting the potential of the first node, and comprises a power supply introducing submodule, an adjusting submodule and a second coupling module, wherein the power supply introducing submodule is used for writing a first power supply signal into a control end of the adjusting submodule according to a trigger signal, the adjusting submodule is used for writing a clock signal into the first node according to the potential of the control end of the adjusting submodule, and the second coupling module is used for coupling the clock signal to the control end of the adjusting submodule; and the trigger writing module is used for writing the trigger signal into the second node according to the clock signal. The shift register can shift and output the trigger signal with longer pulse duration, so that the output signal with longer pulse duration is generated, and the tailing phenomenon of the output signal is weaker under the coupling action of the first coupling module.
Drawings
Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
fig. 8 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;
FIG. 9 is a timing diagram of a shift register according to an embodiment of the present invention;
fig. 10 is a schematic circuit diagram of a display driver according to an embodiment of the present invention;
fig. 11 is a timing diagram of a display driver according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic circuit structure diagram of a shift register according to an embodiment of the present invention, and referring to fig. 1, the shift register includes: an output adjusting module 101, wherein the output adjusting module 101 is configured to output the first power signal VGH from the output terminal EMB of the shift register according to the potential of the first node N1, and output the second power signal VGL from the output terminal EMB of the shift register according to the potential of the second node N2; a first coupling module 102, wherein the first coupling module 102 is configured to couple a signal at the output end EMB of the shift register to a second node N2; the node adjusting module is used for adjusting the potential of the first node N1, and includes a power supply lead-in submodule 103, an adjusting submodule 104 and a second coupling module 105, the power supply lead-in submodule 103 is used for writing a first power supply signal VGH into a control end of the adjusting submodule 104 according to a trigger signal EINB, and the adjusting submodule 104 is used for writing a clock signal ECK into the first node N1 according to the potential of the control end; the second coupling module 105 is configured to couple the clock signal ECK to the control terminal of the adjustment submodule 104; the trigger writing module 106 is configured to write the trigger signal EINB into the second node N2 according to the clock signal ECK.
Specifically, the shift register can shift the trigger signal EINB for a certain time and then output the trigger signal EINB through the output end EMB of the shift register, so that a scanning signal is provided for one row of pixels of the display panel. The output adjusting module 101 can adjust the output of the shift register, for example, can output a first power signal VGH or a second power signal VGL, where the first power signal VGH and the second power signal VGL have different high and low levels, and typically, the first power signal VGH can be set to be a high level, and the second power signal VGL can be set to be a low level, at this time, the output adjusting module is turned on when the corresponding modules are at the low level, and the pulse of the trigger signal EINB is at the low level; when the signal at the first node N1 is an active signal, the output adjustment module 101 can control the output end EMB of the shift register to output the first power signal VGH, and when the signal at the second node N2 is an active signal, the output adjustment module 101 can control the output end EMB of the shift register to output the second power signal VGL, so that the trigger signal EINB is output after shifting through controlling the first node N1 and the second node N2. The clock signal ECK may be generated by a driving chip in the display panel, for example, and the duty ratio of the low level in the clock signal ECK may be 50% or less than 50%. When the pulse (low level) of the trigger signal EINB does not arrive, the power supply introducing submodule 103 is turned off, the potential of the first node N1 is not rewritten, and similarly, although the trigger writing module 106 is periodically turned on, since the trigger signal EINB is high level, the potential of the second node N2 is continuously low level, and the output end EMB of the shift register at this time keeps the potential (high level) at the previous time; then the trigger signal EINB comes at a low level, the power supply introducing sub-module 103 is turned on, the first power supply signal VGH controls the adjusting sub-module 104 to be turned off, the potential of the first node N1 still does not change, when the clock signal ECK is at a high level, the potential of the second node N2 is still at a high level, the output end of the shift register continuously outputs a high level, when the low level of the clock signal ECK comes, the potential of the second node N2 is pulled down, so that the output adjusting module 101 outputs the second power supply signal VGL, that is, the falling edge of the output signal of the shift register output end EMB comes at this time, and due to the coupling effect of the first coupling module 102, the output signal at the low level is coupled to the second node N2, so that the potential of the second node N2 is further pulled down, and the output adjusting module 101 pulls down the signal of the shift register output end EMB to a lower level more quickly, namely, the trailing phenomenon of the falling edge can be greatly improved; then, in the process that the trigger signal EINB is continuously at the low level, no matter the clock signal ECK is at the high level or at the low level, the adjustment sub-module 104 is always in the off state, and the trigger write-in module 106 is periodically turned on, so that the second node N2 can maintain the low level, and further the output end EMB of the shift register always outputs the low level, that is, the pulse duration of the trigger signal EINB is set to be longer in this embodiment, and the pulse duration of the output signal of the shift register can also be longer; when the trigger signal EINB changes to the high level, the clock signal ECK does not change to the low level at this time, the power supply introduction submodule 103 is turned off, the control end of the adjustment submodule 104 is still at the high level, the adjustment submodule 104 is still turned off, the trigger write module 106 is also turned off at this time, the potentials of the first node N1 and the second node N2 are not changed, and the output end of the shift register still outputs the low level at this time; when the low level of the clock signal ECK arrives, the control end of the adjusting submodule 104 is coupled to the low level through the coupling effect of the second coupling module 105, the adjusting submodule 104 is turned on, so that the first node N1 is at the low level, the output adjusting module 101 controls the shift register to output the high level, and at this time, because the clock signal ECK is at the low level, the trigger writing module 106 is turned on, the trigger signal EINB at the high level is written into the second node N2, and the output adjusting module cannot control the output end of the shift register to output the low level. In summary, the shift register can shift and output the trigger signal with longer pulse duration, so as to generate an output signal with longer pulse duration, and the tailing phenomenon of the output signal is weaker.
In the technical scheme of this embodiment, the shift register includes an output adjustment module, configured to output a first power signal from an output terminal of the shift register according to a potential of a first node, and output a second power signal from the output terminal of the shift register according to a potential of a second node; the first coupling module is used for coupling the signal of the output end of the shift register to a second node; the node adjusting module is used for adjusting the potential of the first node, and comprises a power supply introducing submodule, an adjusting submodule and a second coupling module, wherein the power supply introducing submodule is used for writing a first power supply signal into a control end of the adjusting submodule according to a trigger signal, the adjusting submodule is used for writing a clock signal into the first node according to the potential of the control end of the adjusting submodule, and the second coupling module is used for coupling the clock signal to the control end of the adjusting submodule; and the trigger writing module is used for writing the trigger signal into the second node according to the clock signal. The shift register can shift and output the trigger signal with longer pulse duration, so that the output signal with longer pulse duration is generated, and the tailing phenomenon of the output signal is weaker under the coupling action of the first coupling module.
For example, the present embodiment may set the pulse duration of the trigger signal EINB to be greater than or equal to twice the period of the clock signal ECK. With this arrangement, the output terminal of the shift register can also output a signal having a pulse time greater than or equal to twice the period of the clock signal ECK, and thus can be applied to a pixel circuit requiring a scanning signal having a long duration. Of course, the pulse duration of the output signal of the shift register can be controlled by adjusting the pulse duration of the trigger signal EINB.
Optionally, with reference to fig. 1, a first end of the power supply lead-in sub-module 103 is connected to the first power supply signal VGH, a second end of the power supply lead-in sub-module 103 is electrically connected to a control end of the regulator sub-module 104, and a control end of the power supply lead-in sub-module 103 is connected to the trigger signal EINB; a first end of the second coupling module 105 is connected to the clock signal ECK, and a second end of the second coupling module 105 is electrically connected to a control end of the regulator sub-module 104; a first end of the trigger writing module 106 is connected to a trigger signal EINB, a second end of the trigger writing module 106 is electrically connected to the second node N2, and a control end of the trigger writing module 106 is connected to a clock signal ECK; a first terminal of the first coupling module 102 is electrically connected to the output terminal EMB of the shift register, and a second terminal of the first coupling module 102 is electrically connected to the second node N2.
In this embodiment, all functions of the shift register can be realized by the power supply lead-in sub-module 103, the trigger write-in module 106, the second coupling module 105, the adjustment sub-module 104, the output adjustment module 101, and the first coupling module 102, and the circuit structure is simple, which is beneficial to reducing the cost of the circuit.
For example, fig. 2 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, and referring to fig. 2, the toggle writing module 106 includes a first transistor T1, a first terminal of the first transistor T1 is used as a first terminal of the toggle writing module 106, a second terminal of the first transistor T1 is used as a second terminal of the toggle writing module 106, and a control terminal of the first transistor T1 is used as a control terminal of the toggle writing module 106; the power supply introduction sub-module 103 comprises a second transistor T2, a first terminal of the second transistor T2 is used as a first terminal of the power supply introduction sub-module 103, a second terminal of the second transistor T2 is used as a second terminal of the power supply introduction sub-module 103, and a control terminal of the second transistor T2 is used as a control terminal of the power supply introduction sub-module 103; the adjusting sub-module 104 includes a third transistor T3, a first terminal of the third transistor T3 is a first terminal of the adjusting sub-module 104, a second terminal of the third transistor T3 is a second terminal of the adjusting sub-module 104, and a control terminal of the third transistor T3 is a control terminal of the adjusting sub-module 104; the first coupling module 102 includes a first capacitor C1, a first terminal of the first capacitor C1 is used as a first terminal of the first coupling module 102, and a second terminal of the first capacitor C1 is used as a second terminal of the first coupling module 102; the second coupling module 105 includes a second capacitor C2, a first terminal of the second capacitor C2 is used as a first terminal of the second coupling module 105, and a second terminal of the second capacitor C2 is used as a second terminal of the second coupling module 105.
Specifically, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors or N-type transistors, and because the P-type transistors in the display panel are mature in manufacturing process, low in manufacturing cost, and good in stability, the P-type transistors may be preferred; in this embodiment, the functions of the modules can be realized through the transistors and the capacitors, the number of components is small, the circuit structure is simple, and the narrow frame of the display panel can be realized more favorably.
Optionally, fig. 3 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 3, the shift register further includes a feedback module 107, a first end of the feedback module 107 is connected to the first power signal VGH, a second end of the feedback module 107 is electrically connected to the first node N1, a control end of the feedback module 107 is electrically connected to the second node N2, and the feedback module 107 is configured to write the first power signal VGH into the first node N1 according to a potential of the second node N2.
Specifically, when the second node N2 is an active signal (low level), the feedback module 107 is turned on, so that the first power signal VGH is written into the first node N1, and the output adjustment module 101 can only control the output terminal of the shift register to output the second power signal VGL, thereby preventing an output error phenomenon caused by the output terminal of the shift register outputting the first power signal VGH and the second power signal VGL at the same time.
For example, referring to fig. 4, the feedback module 107 includes a fourth transistor T4, a first terminal of the fourth transistor T4 is used as a first terminal of the feedback module 107, a second terminal of the fourth transistor T4 is used as a second terminal of the feedback module 107, and a control terminal of the fourth transistor T4 is used as a control terminal of the feedback module 107 according to a circuit configuration diagram of another shift register provided by an embodiment of the invention.
Specifically, the fourth transistor T4 may be, for example, a P-type transistor, and the feedback function of the feedback module 107 can be realized by using one fourth transistor T4, so that the circuit structure is simple, and the cost of the shift register is further reduced while the working stability of the shift register is ensured.
Optionally, fig. 5 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, and referring to fig. 5, the shift register further includes a normally-on module 108, a second end of the trigger write module 106 is electrically connected to a second node N2 through the normally-on module 108, wherein the second end of the trigger write module 106 is electrically connected to the first end of the normally-on module 108, the second end of the normally-on module 108 is electrically connected to a second node N2, and a control end of the normally-on module 108 is connected to the second power signal VGL.
Specifically, by setting the normally-on module 108, the leakage current of the second node N2 can be reduced, and an output error of the shift register caused by an excessive potential loss of the second node N2 can be avoided, that is, the stability of the output of the shift register can be further improved by setting the normally-on module 108.
For example, referring to fig. 6, the normally-on module 108 includes a fifth transistor T5, a first terminal of the fifth transistor T5 is used as a first terminal of the normally-on module 108, a second terminal of the fifth transistor T5 is used as a second terminal of the normally-on module 108, and a control terminal of the fifth transistor T5 is used as a control terminal of the normally-on module 108 according to a circuit configuration diagram of another shift register provided by an embodiment of the invention.
Specifically, the fifth transistor T5 may be, for example, a P-type transistor, and the control terminal of the fifth transistor T5 is connected to the second power signal VGL, that is, is always connected to a low level, so that the fifth transistor T5 is always in a conducting state, which does not affect the writing of the potential of the first node N1, and can reduce the leakage current, and meanwhile, the function of the normally-open module 108 can be realized by using one fifth transistor T5, and the circuit structure is simple, which is beneficial to further reducing the cost of the shift register.
Optionally, fig. 7 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, and referring to fig. 7, the output adjusting module 101 includes: a pull-up sub-module 1011, a pull-down sub-module 1012, and a sustain sub-module 1013; a first end of the pull-up sub-module 1011 is connected to a first power signal VGH, a second end of the pull-up sub-module 1011 is electrically connected to an output end EMB of the shift register, and a control end of the pull-up sub-module 1011 is electrically connected to a first node N1; a first end of the pull-down submodule 1012 is connected to a second power supply signal VGL, a second end of the pull-down submodule 1012 is electrically connected to an output end EMB of the shift register, and a control end of the pull-down submodule 1012 is electrically connected to a second node N2; a first end of the sustain submodule 1013 is connected to the first power signal VGH, and a second end of the sustain submodule 1012 is electrically connected to a control end of the pull-up submodule 1011.
Specifically, the pull-up sub-module 1011 can turn on its first terminal and second terminal when its control terminal is at a low level, so that the output terminal EMB of the shift register outputs a high level, and the sustain sub-module 1013 can sustain the potential of the control terminal of the pull-up sub-module 1011; the pull-down sub-module 1012 can conduct the first terminal and the second terminal when the control terminal is at a low level, so that the output terminal EMB of the shift register outputs a low level; in this embodiment, the pull-up sub-module 1011, the pull-down sub-module 1012 and the sustain sub-module 1013 are used to implement the related functions of the output adjustment module 101, and the circuit structure is simple, which is beneficial to further reducing the cost of the shift register.
Exemplarily, fig. 8 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and referring to fig. 8, the pull-up sub-module 1011 includes a sixth transistor T6, a first terminal of the sixth transistor T6 is used as a first terminal of the pull-up sub-module 1011, a second terminal of the sixth transistor T6 is used as a second terminal of the pull-up sub-module 1011, and a control terminal of the sixth transistor T6 is used as a control terminal of the pull-up sub-module 1011; the pull-down sub-module 1012 includes a seventh transistor T7, a first terminal of the seventh transistor T7 is a first terminal of the pull-down sub-module 1012, a second terminal of the seventh transistor T7 is a second terminal of the pull-down sub-module 1012, and a control terminal of the seventh transistor T7 is a control terminal of the pull-down sub-module 1012; the sustain sub-module 1013 comprises a third capacitor C3, a first terminal of the third capacitor C3 being a first terminal of the sustain sub-module 1013, and a second terminal of the third capacitor C3 being a second terminal of the sustain sub-module 1013.
Specifically, the sixth transistor T6 and the seventh transistor T7 may be P-type transistors, and in this embodiment, the transistors and the capacitors are used to realize the related functions of each sub-module in the output adjustment module 101, and the shift register has fewer components, a simple circuit structure, and a lower cost.
For example, fig. 9 is a timing diagram of a shift register according to an embodiment of the present invention, and fig. 9 may correspond to fig. 8, and the present invention is described in detail with reference to fig. 9 and fig. 8 (for convenience of description, the second terminal of the first transistor T2 is the third node N3, and the second terminal of the second transistor T2 is the fourth node N4):
at the stage T0, the trigger signal EINB is at a high level first, at this time, the second transistor T2 is turned off, the fourth node N4 is coupled by the second capacitor C2 and changes with the clock signal ECK, so that the first node N1 is kept at a low level, and since the trigger signal EINB is at a high level, the third node N3 and the second node N2 are always at a high level, the output end EMB of the shift register outputs a high level, and when the low level of the trigger signal EINB arrives, since the clock signal ECK is not yet set low at this time, the potentials of the first node N1 and the second node N2 are not changed, and the output is still at a high level;
at stage T1, the clock signal ECK jumps down, but since the fourth node N4 is still high, the third transistor T3 is turned off, the first transistor T1 is turned on, the third node N3 is pulled low, the fourth transistor T4 is turned on, the first node N1 is pulled high and held by the third capacitor C3, and the sixth transistor T6 is turned off; because the second node N2 is pulled low by times, the fifth transistor T5 is in a critical off state, the seventh transistor T7 is turned on, the output signal jumps down, and meanwhile, due to the coupling effect of the first capacitor C1, the second node N2 is coupled to an extremely low level, and the output signal jumps down to the level of the second power supply signal VGL quickly and stops;
at stage t2, although the clock signal ECK makes a transition, the output signal remains low because the trigger signal EINB has not changed;
at stage T3, the trigger signal EINB jumps high, so that the second transistor T2 is turned off and the fourth node N4 goes high; however, at this time, the clock signal ECK is at a high level, and the potentials of the second node N2 and the third node N3 are not changed, so that the output signal is still at a low level;
at stage T4, the clock signal ECK jumps down, a high level is written into the second node N2 and the third node N3, the fourth transistor T4 and the seventh transistor T7 are turned off, the fourth node N4 is coupled to a low level, the third transistor T3 is turned on, the low level is transmitted to the first node N1, so that the sixth transistor T6 is turned on, and the output signal jumps up to the high level;
in the period T5, the second node N2 remains unchanged, the fourth node N4 is turned on along with the down-jump of the clock signal ECK, and a low level is periodically transmitted to the first node N1, so that the sixth transistor T6 remains turned on, and the output signal EMB remains high for output.
Therefore, the shift of the trigger signal with longer pulse duration can be realized by seven transistors and three capacitors in the embodiment, and the trailing edge of the output signal has no trailing phenomenon.
Fig. 10 shows a schematic circuit structure of a display driver according to an embodiment of the present invention, where the display driver includes a plurality of cascaded shift registers 10 according to any embodiment of the present invention, where an output EMB of an m-th shift register provides a trigger signal EINB of an m + 1-th shift register, the display driver further includes a first clock line CK1, a second clock line CK2 and a trigger signal line EIN, fig. 11 is a timing diagram of the display driver according to the embodiment of the present invention, and with reference to fig. 10 and 11, the first clock line CK1 provides a clock signal of an odd-numbered shift register, the second clock line CK2 provides a clock signal of an even-numbered shift register, the trigger signal line cn provides a trigger signal EINB of the first shift register, and as can be seen from fig. 11, the display driver according to this embodiment can output a plurality of scan signals (EINB1, EINB, EIN) in a shifting relationship with each other EINB2 … …)
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A shift register, comprising:
the output adjusting module is used for outputting a first power supply signal from the output end of the shift register according to the potential of a first node and outputting a second power supply signal from the output end of the shift register according to the potential of a second node;
the first coupling module is used for coupling the signal of the output end of the shift register to the second node;
the node adjusting module is used for adjusting the potential of the first node, and comprises a power supply lead-in submodule, an adjusting submodule and a second coupling module, wherein the power supply lead-in submodule is used for writing the first power supply signal into a control end of the adjusting submodule according to a trigger signal, the adjusting submodule is used for writing a clock signal into the first node according to the potential of the control end of the adjusting submodule, and the second coupling module is used for coupling the clock signal to the control end of the adjusting submodule;
and the trigger writing module is used for writing the trigger signal into the second node according to the clock signal.
2. The shift register of claim 1, wherein the trigger signal is configured to: the pulse duration of the trigger signal is greater than or equal to twice the period of the clock signal.
3. The shift register according to claim 1, wherein a first terminal of the power supply import submodule is connected to the first power supply signal, a second terminal of the power supply import submodule is electrically connected to a control terminal of the regulation submodule, and the control terminal of the power supply import submodule is connected to the trigger signal;
the first end of the second coupling module is connected to the clock signal, and the second end of the second coupling module is electrically connected with the control end of the adjusting sub-module;
a first end of the trigger writing module is connected to the trigger signal, a second end of the trigger writing module is electrically connected to the second node, and a control end of the trigger writing module is connected to the clock signal;
the first end of the first coupling module is electrically connected with the output end of the shift register, and the second end of the first coupling module is electrically connected with the second node.
4. The shift register according to claim 3, wherein the toggle writing module comprises a first transistor, a first terminal of the first transistor is used as the first terminal of the toggle writing module, a second terminal of the first transistor is used as the second terminal of the toggle writing module, and a control terminal of the first transistor is used as the control terminal of the toggle writing module;
the power supply lead-in sub-module comprises a second transistor, wherein a first end of the second transistor is used as a first end of the power supply lead-in sub-module, a second end of the second transistor is used as a second end of the power supply lead-in sub-module, and a control end of the second transistor is used as a control end of the power supply lead-in sub-module;
the adjusting submodule comprises a third transistor, wherein a first end of the third transistor is used as a first end of the adjusting submodule, a second end of the third transistor is used as a second end of the adjusting submodule, and a control end of the third transistor is used as a control end of the adjusting submodule;
the first coupling module comprises a first capacitor, a first end of the first capacitor is used as a first end of the first coupling module, and a second end of the first capacitor is used as a second end of the first coupling module;
the second coupling module comprises a second capacitor, a first end of the second capacitor is used as a first end of the second coupling module, and a second end of the second capacitor is used as a second end of the second coupling module.
5. The shift register according to claim 3, further comprising a feedback module, wherein a first terminal of the feedback module is connected to the first power signal, a second terminal of the feedback module is electrically connected to the first node, a control terminal of the feedback module is electrically connected to the second node, and the feedback module is configured to write the first power signal into the first node according to a potential of the second node.
6. The shift register of claim 5, wherein the feedback module comprises a fourth transistor, a first terminal of the fourth transistor is used as the first terminal of the feedback module, a second terminal of the fourth transistor is used as the second terminal of the feedback module, and a control terminal of the fourth transistor is used as the control terminal of the feedback module.
7. The shift register according to claim 3, further comprising a normally-on module, wherein a second end of the trigger write module is electrically connected to the second node through the normally-on module, a second end of the trigger write module is electrically connected to a first end of the normally-on module, a second end of the normally-on module is electrically connected to the second node, and a control end of the normally-on module is connected to the second power signal.
8. The shift register of claim 7, wherein the normally-on module comprises a fifth transistor, a first terminal of the fifth transistor is used as the first terminal of the normally-on module, a second terminal of the fifth transistor is used as the second terminal of the normally-on module, and a control terminal of the fifth transistor is used as the control terminal of the normally-on module.
9. The shift register of claim 1, wherein the output adjustment module comprises: the system comprises a pull-up submodule, a pull-down submodule and a maintenance submodule;
a first end of the pull-up sub-module is connected to the first power supply signal, a second end of the pull-up sub-module is electrically connected with an output end of the shift register, and a control end of the pull-up sub-module is electrically connected with the first node;
the first end of the pull-down submodule is connected with the second power supply signal, the second end of the pull-down submodule is electrically connected with the output end of the shift register, and the control end of the pull-down submodule is electrically connected with the second node;
and the first end of the maintaining submodule is connected with the first power supply signal, and the second end of the maintaining submodule is electrically connected with the control end of the pull-up submodule.
10. The shift register of claim 9, wherein the pull-up sub-block comprises a sixth transistor, a first terminal of the sixth transistor is used as the first terminal of the pull-up sub-block, a second terminal of the sixth transistor is used as the second terminal of the pull-up sub-block, and a control terminal of the sixth transistor is used as the control terminal of the pull-up sub-block;
the pull-down sub-module comprises a seventh transistor, wherein a first end of the seventh transistor is used as a first end of the pull-down sub-module, a second end of the seventh transistor is used as a second end of the pull-down sub-module, and a control end of the seventh transistor is used as a control end of the pull-down sub-module;
the first end of the third capacitor is used as the first end of the maintenance submodule, and the second end of the third capacitor is used as the second end of the maintenance submodule.
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