CN114333673A

CN114333673A - Gate drive unit, gate drive circuit and display device

Info

Publication number: CN114333673A
Application number: CN202111640618.0A
Authority: CN
Inventors: 黄丽玉; 张军; 祝伟鹏
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-04-12
Anticipated expiration: 2041-12-29
Also published as: CN114333673B

Abstract

The embodiment of the invention discloses a gate drive unit, which comprises: the input module is coupled between the first high level and the first node and charges the first node according to a pre-charge signal; the output module is coupled with the first node and provides a current-stage grid driving signal according to the first node voltage and the first clock signal; and a pull-down maintenance module coupled to the first node and the output module, for pulling down the first node to a first low level according to the pull-down signal and maintaining the first node and the gate driving signal of the present stage at a second low level according to a second high level and the gate driving signal of the present stage, wherein the pull-down maintenance module includes: the voltage of the second node is controlled by the stability maintaining control unit according to a second high level and a stability maintaining signal, and the current-level grid driving signal and the first node are maintained at the second low level by the stability maintaining unit according to the voltage of the second node.

Description

Gate drive unit, gate drive circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a gate driving unit, a gate driving circuit and a display device.

Background

The Display device displays Display data on the Display Panel through the transmission apparatus, and examples of the Display device include a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), an Organic Light-Emitting Diode (OLED) Display, and an electrophoretic Display (EPD).

With the development of display technologies, display panels tend to have high integration and low cost. In the related art, a Gate-driver in Array (GIA) circuit is directly integrated on an Array substrate of a display panel, and the GIA circuit generally includes a plurality of cascaded Gate driving units, each corresponding to one or more rows of pixels corresponding to a scan line, so as to implement a scan driver for the display panel. However, the GIA circuit has a problem of high-temperature failure in practical application, and when the temperature is high, the driving signal output by the GIA circuit has a phenomenon of large noise or false operation, and further causes a problem of screen flicker due to in-plane leakage.

Therefore, an improved gate driving unit, gate driving circuit and display device are desired to solve the above problems.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a gate driving unit, a gate driving circuit and a display device having good output capability and stability, thereby improving high temperature performance of products.

According to an aspect of the present invention, there is provided a gate driving unit for driving corresponding scan lines on a display panel, the gate driving unit including: an input module, coupled between a first high level and a first node, for charging the first node according to a precharge signal; the output module is coupled with the first node and used for providing a grid driving signal of the current stage according to the voltage of the first node and a first clock signal; and a pull-down maintenance module, coupled to the first node and the output module, for pulling down the first node to a first low level according to a pull-down signal and maintaining the first node and the gate driving signal of the current stage at a second low level according to a second high level and a maintenance signal, wherein the pull-down maintenance module includes: the gate driving circuit comprises a gate driving signal of the current stage and a gate driving signal of the first node, and the gate driving signal of the current stage and the first node are maintained at a first low level according to the voltage of the first node.

Optionally, the stability-maintaining control unit includes: and the first end and the control end of the first transistor are coupled with the second high level, the second end of the first transistor is coupled with the second node, the first end of the second transistor is coupled with the second node, the second end of the second transistor is coupled with the second low level, and the control end of the first transistor is coupled with the first stable signal.

Optionally, the stability maintaining control unit further includes: a third transistor, a first terminal of which is coupled to the second node, a second terminal of which is coupled to the second low level, and a control terminal of which is coupled to a second maintenance signal.

Optionally, the stability maintaining control unit further includes: a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the second low level, and a control terminal of the fourth transistor is coupled to the gate driving signal of the current stage.

Optionally, the pull-down stability maintaining module further includes: the pull-down transistor is coupled between a first low level and the first node, and the control end receives a pull-down signal and pulls down the voltage of the first node to a first low level according to the pull-down signal.

Optionally, the stability maintaining module comprises: a fifth transistor coupled between the first node and the second low level; and a sixth transistor coupled between the gate driving signal and the second low level; the fifth transistor turns on or off a current path between the first node and the second low level according to an active state of the second node, and the sixth transistor turns on or off the current path between the gate driving signal and the second low level according to an active state of the second node.

Optionally, the stability maintaining module further comprises: and a seventh transistor, coupled between the gate driving signal and a second low level, wherein the control terminal receives a second clock signal and periodically turns on a current path between the gate driving signal and the second low level according to the second clock signal.

Optionally, the output module includes: an output transistor coupled between the first clock signal and the gate driving signal, and having a control terminal coupled to the first node; and the capacitor is coupled between the control end and the second end of the output transistor.

According to another aspect of the present invention, there is provided a gate driving circuit, wherein the gate driving circuit comprises a plurality of stages of gate driving units as described above.

According to still another aspect of the present invention, there is provided a display device including: the gate driving circuit as described above, for providing a plurality of gate driving signals; a data driving circuit for providing a plurality of gray scale data; and a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines, wherein the display panel receives the plurality of gate driving signals via the plurality of scan lines to select the plurality of pixel units by rows, and receives the plurality of gray scale data via the plurality of data lines by columns to provide the plurality of gray scale data to the selected pixel units to realize image display.

In the grid driving unit and the grid driving circuit provided by the invention, the stability maintaining control unit controls the stability maintaining unit to pull down and maintain the stability of the grid driving signal of the grid driving unit according to the stability maintaining signal.

Optionally, in the gate driving unit and the gate driving circuit provided by the present invention, the gate driving signals output by the previous stage, the present stage and the next stage gate driving units are used as the stability maintaining signal, and the voltage of the second node is not greatly fluctuated due to the coupling of the first node by the clock signal, and the loss of the charge of the second node can be reduced, so that the second node in the stability maintaining stage can be maintained at a higher and more stable voltage, and the stability of the gate driving unit and the gate driving circuit is further improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a circuit configuration diagram of a gate driving unit of the related art;

FIG. 2 shows a timing diagram of some of the signals in FIG. 1;

fig. 3 shows a circuit configuration diagram of a gate driving unit of an embodiment of the present invention;

FIG. 4 shows a signal timing diagram of the gate driving unit of FIG. 3;

FIG. 5 illustrates a second node waveform comparison graph of a gate driving unit of the prior art and the present invention;

FIG. 6 illustrates a gate drive circuit of an embodiment of the present invention;

fig. 7 shows a packaging schematic of the gate driving unit of fig. 3;

fig. 8 shows a signal timing diagram of the gate driving circuit of fig. 6;

FIG. 9 shows a timing diagram of a portion of the gate drive signals of the gate drive circuit of FIG. 6;

fig. 10 is a schematic structural view showing a display device according to an embodiment of the present invention;

fig. 11 is a circuit configuration diagram showing a gate driving unit according to still another embodiment of the present invention;

fig. 12 is a circuit configuration diagram illustrating a gate driving unit according to still another embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "coupled" to another element or circuit is "coupled" between two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.

In this application, the transistor may include one selected from a bipolar transistor or a field effect transistor, the first terminal and the second terminal of the transistor are a high potential terminal and a low potential terminal, respectively, on the current path, and the control terminal is configured to receive a control signal to control the transistor to be turned on and off. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal, and a current flows from the first terminal to the second terminal in an on state of the MOSFET. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.

Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 shows a circuit configuration diagram of a gate driving unit 310 of the related art. The gate driving unit of the related art includes an input transistor T8, an output module 311, and a pull-down maintenance module 312.

The input transistor T8 has a first terminal coupled to the DC high level signal DC _ H, a second terminal coupled to the first node Q, and a control terminal receiving the pre-charge signal Gn-4 for charging the first node Q according to the pre-charge signal Gn-4.

The output module 311 is coupled to the first node Q and provides the gate driving signal Gn according to a voltage of the first node Q and a clock signal CLK 2.

The pull-down maintenance module 312 is coupled to the output module 311 and the first node Q, and maintains the gate driving signal Gn at a low level signal VGL under the control of the voltage of the first node Q.

Further, the pull-down stability maintaining module 312 includes a pull-down transistor T10, a stability maintaining control unit 3121, and a stability maintaining unit 3122.

The pull-down transistor T10 has a first terminal coupled to the first node Q, a second terminal coupled to the DC low level signal DC _ L, a control terminal receiving the pull-down signal Gn +4, and the pull-down transistor T10 pulls down the voltage of the first node Q to the low level DC _ L according to the active state of the pull-down signal Gn + 4.

The stability maintenance control unit 3121 is coupled to the first node Q and the second node QB, and pulls down the voltage of the second node QB to the low level signal VGL according to the active state of the first node Q.

The stability maintaining unit 3122 is coupled to the first node Q, the second node QB, and the gate driving signal Gn, and pulls down the voltage of the first node Q and the gate driving signal Gn to the low level signal VGL according to the active state of the second node QB, so as to ensure that the gate driving signal of the gate driving unit of the present stage is maintained at the low level signal VGL when the gate driving units of other stages are outputting, thereby enabling the gate driving circuit 200 to have good stability.

Specifically, the output module 311 includes: an output transistor T9 and a capacitor C1. The output transistor T9 has a first terminal receiving the clock signal CLK2, a second terminal coupled to the gate driving signal Gn, and a control terminal coupled to the first node Q. The capacitor C1 has a first terminal coupled to the control terminal of the output transistor T9 and a second terminal coupled to the second terminal of the output transistor T9.

The stability maintenance control unit 3121 includes a first transistor T1 and a second transistor T2, wherein a first terminal of the first transistor T1 receives the second high level DC, a second terminal is coupled to the second node QB, and a control terminal is coupled to the first terminal. The second transistor T2 has a first terminal coupled to the second node QB, a control terminal coupled to the first node Q, and a second terminal coupled to the low-level signal VGL.

The maintenance unit 3122 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The control terminals of the fifth transistor T5 and the sixth transistor T6 are respectively coupled to the second node QB, the second terminal is respectively coupled to the low level VGL, the first terminal of the fifth transistor T5 is coupled to the first node Q, and the first terminal of the sixth transistor T6 is coupled to the gate driving signal Gn. The seventh transistor T7 has a first terminal coupled to the gate driving signal Gn, a second terminal coupled to the low level signal VGL, and a control terminal receiving the clock signal CLK 4.

In the vitalizing period, the first node Q has been pulled down to the low level signal VGL in the previous period, and the input transistor T8, the output transistor T9, and the pull-down transistor T10 are all in the off state. The second high level DC charges the second node QB through the first transistor T1, turns on the fifth transistor T5 to pull down the voltage of the first node Q to the low level signal VGL, and turns on the sixth transistor T6 to pull down the gate driving signal Gn to the low level signal, thereby pulling down and stabilizing the first node Q and the gate driving signal Gn.

However, the gate driving unit 310 in the prior art has a problem of high temperature failure, the change of the node voltage caused by the phenomena of leakage, coupling and the like of the gate driving unit 310 at normal temperature does not affect the conduction state of the internal transistor, and after the temperature rises, the threshold voltage of the transistor decreases along with the temperature rise, so that part of the transistors which should be in the off state is partially conducted. Referring to fig. 2, fig. 2 shows a timing diagram of part of the signals in fig. 1. In the transient state, the voltage of the first node Q is coupled and increased by the clock signal CLK2, the voltage of the control terminal of the second transistor T2 increases, the threshold voltage of the second transistor T2 decreases due to the temperature increase, the second transistor T2 is turned on, the charge of the second node QB is discharged through the second transistor T2, the voltage of the first terminal of the second transistor T2 decreases, the fifth transistor T5 is turned on insufficiently, and the charge of the first node Q cannot be discharged effectively. As the charges of the first node Q are accumulated, the voltage thereof also gradually increases, so that the output transistor T9 cannot be completely turned off, and when the clock signal CLK2 received by the first terminal of the output transistor T9 is at a high level, the level of the gate driving signal Gn increases, the gate driving signal Gn generates noise or malfunction, and further, the electric leakage causes the problems of screen flicker and the like.

To solve the above problem, the present invention provides an improved gate driving unit, as shown in fig. 3. Fig. 3 shows a circuit structure diagram of a gate driving unit according to an embodiment of the present invention, and the gate driving unit 320 includes an input transistor T8, an output module 321, and a pull-down maintenance module 322.

The input transistor T8 is coupled between the first high level VGH and the first node Q, and the control terminal receives the pre-charge signal Gn-4 and charges the first node Q according to an active state of the pre-charge signal Gn-4. The output module 321 is connected to the first node Q and provides the gate driving signal Gn according to a voltage of the first node Q and a clock signal CLK 2. The pull-down maintenance module 322 is coupled to the output module 321 and the first node Q, and maintains the gate driving signal Gn at the second low level VSQ under the control of the first maintenance signal Gn-2 and the second maintenance signal Gn + 2. The pull-down maintenance module 322 also pulls down the voltage of the first node Q to the first low level VGL according to the active state of the pull-down signal Gn + 4.

Further, the pull-down stabilivolt module 322 includes a pull-down transistor T10, a stabilivolt control unit 3221, and a stabilivolt unit 3222. The pull-down transistor T10 has a first terminal coupled to the first low level VGL, a second terminal coupled to the first node Q, a control terminal receiving the pull-down signal Gn +4, and the pull-down transistor T10 pulls down the voltage of the first node Q to the first low level VGL according to the active state of the pull-down signal Gn + 4. The maintenance controlling unit 3221 is coupled to the second node QB, and pulls down the voltage of the second node QB to the second low level VSQ under the control of the first maintenance signal Gn-2, the second maintenance signal Gn +2 and the gate driving signal Gn, and the maintenance controlling unit 3222 maintains the voltage of the first node Q and the gate driving signal Gn at the second low level VSQ according to the active state of the second node QB, so as to ensure the stability of the output of the gate driving unit 3222. In one possible embodiment, the maintenance unit 3222 also periodically discharges the charge of the output terminal of the gate driving signal Gn according to the clock signal CLK 4.

Specifically, the output module 321 includes an output transistor T9 and a capacitor C1. The output transistor T9 has a first terminal receiving the clock signal CLK2, a second terminal coupled to the gate driving signal Gn, and a control terminal coupled to the first node Q. The capacitor C1 has a first terminal coupled to the control terminal of the output transistor T9 and a second terminal coupled to the gate driving signal Gn.

The capacitor C1 is a parasitic capacitor between the control terminal and the second terminal of the output transistor T9. It should be understood that, in order to improve the coupling effect of the capacitor, and thus the effect of pulling up the Q voltage at the first node, a separate storage capacitor may be disposed between the control terminal and the second terminal of the output transistor T9, and the capacitor C1 is the sum of the parasitic capacitor between the control terminal and the second terminal of the output transistor T9 and the storage capacitor.

The stability maintenance control unit 3221 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The second transistor T2, the third transistor T3, and the fourth transistor T4 have first terminals respectively coupled to the second node QB and second terminals coupled to the second low level VSQ. The control terminal of the second transistor T2 receives the first steady signal Gn-2 and pulls down the second node QB to the second low level VSQ according to the active state of the first steady signal Gn-2, the control terminal of the third transistor T3 receives the second steady signal Gn +2 and pulls down the second node QB to the second low level VSQ according to the active state of the second steady signal Gn +2, and the control terminal of the fourth transistor T4 receives the gate driving signal Gn of the present stage and pulls down the second node QB to the second low level VSQ according to the active state of the gate driving signal Gn of the present stage. The first and control terminals of the first transistor T1 are coupled to the second high level DC, and the second terminal is coupled to the second node QB, and when the second, third and fourth transistors T2, T3 and T4 are all in an off state, the second high level DC charges the second node QB through the first transistor T1 to raise its voltage.

The vitamin cell includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The fifth transistor T5 has a first terminal coupled to the first node Q, a second terminal coupled to the second low level VSQ, and a control terminal coupled to the second node QB. The sixth transistor T6 has a first terminal coupled to the gate driving signal Gn, a second terminal coupled to the second low level VSQ, and a control terminal coupled to the second node QB. The seventh transistor T7 has a first terminal coupled to the gate driving signal Gn of the present stage, a second terminal coupled to the second low level VSQ, and a control terminal receiving the clock signal CLK 4.

The gate driving unit 320 provided by the present invention is further described with reference to fig. 4. Fig. 4 shows a signal timing diagram of the gate driving unit of fig. 3, which includes a precharge signal Gn-4, a first glitch signal Gn-2, a clock signal CLK2, a clock signal CLK4, a second glitch signal Gn +2, a pull-down signal Gn +4, a first node Q, a second node QB, and a gate driving signal Gn from top to bottom, respectively. The period of the clock signal CLK2 is 8T, the period at the high level is 3T, the period at the low level is 5T, and the period and the duty ratio of the clock signal CLK4 are the same as those of the clock signal CLK2 and lag behind the clock signal CLK2 by 4T (i.e., one-half period of the clock signal CLK 2).

During the precharge period, i.e., the periods T0-T1, the precharge signal Gn-4 transits from low level to high level, the input transistor T8 is turned on, and the first high level VGH precharges the first node Q through the input transistor T8, thereby turning on the output transistor T9. After 2T (i.e., a quarter cycle of the clock signal CLK 2), the first stabilizing signal Gn-2 transits from low level to high level, turning on the second transistor T2, pulling down the second node QB to the second low level VSQ, turning off the fifth transistors T5 and T7, thereby stopping the pulling down of the gate driving signal Gn and the first node Q.

In the bootstrap phase, i.e., the phases T1-T2, the output transistor T9 is already turned on through the precharge phase, the clock signal CLK2 transitions from low level to high level, the gate driving signal Gn is output through the output transistor T9, and the voltage of the first node Q is increased by the bootstrap action of the capacitor C1, so that the output transistor T9 is ensured to be fully turned on in the bootstrap phase. When the gate driving signal Gn transitions to a high level, the fourth transistor T4 is turned on, the second node QB is continuously pulled down to the second low level VSQ, after 1T (i.e., one eighth of a period of the clock signal CLK 2), the first steady-state signal Gn-2 transitions to a low level, the second transistor T2 is turned off, at this time, the fourth transistor T4 is in a turned-on state, it is ensured that the potential of the second node QB is maintained at the second low level VSQ, after 1T, the second steady-state signal Gn +2 transitions from the low level to the high level, the third transistor T3 is turned on, and the second node QB is continuously pulled down to the second low level VSQ.

In the pull-down phase, i.e., the phases T2-T3, during the 1 st T of T2-T3, the pull-down signal Gn +4 is at a low level, the voltage of the first node Q is kept at a high level, the output transistor T9 is kept in a conducting state, when the clock signal CLK2 transits from a high level to a low level, the gate driving signal Gn is quickly pulled down to a low level through the output transistor T9, and the fourth transistor T4 is turned off. After 1T, the pull-down signal Gn +4 goes high, the pull-down first transistor T10 is turned on, the first node Q is pulled down to the first low level VGL, and after 1T, Gn +2 goes low, and T3 is turned off.

After the transient maintaining period, i.e. time T3, the first node Q has been pulled down to the first low level VGL, the input transistor T8, the output transistor T9 and the pull-down transistor T10 are all in the off state, the first transient maintaining signals Gn-2 and Gn +2 and the gate driving signal Gn of the current stage are also in the low level, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned off, the second high level DC charges the second node QB through the first transistor T1, the second node QB rises in potential, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first node Q and the gate driving signal Gn are pulled down to the second low level VSQ to maintain the stability. Meanwhile, the clock signal CLK4 also periodically turns on the seventh transistor T7, further stabilizing the gate driving signal Gn.

In the gate driving unit 320 according to the embodiment of the invention, the stability control unit 3221 is not coupled to the first node Q, and the voltage of the second node QB is not decreased due to the first node Q being coupled and raised by the clock signal CLK2, so that the second node QB can maintain a higher and more stable potential in the stability maintaining stage, which is beneficial for the fifth transistor T5 and the sixth transistor T6 to keep pulling down the first node Q and the gate driving signal Gn, so that the gate driving unit 320 according to the embodiment of the invention outputs the stable gate driving signal Gn.

Referring to fig. 5, fig. 5 illustrates a second node waveform comparison diagram of a gate driving unit of the related art and the present invention. The clock signal CLK2 and the second node QB are respectively from top to bottom, where a solid line represents the voltage of the second node QB of the gate driving unit according to the embodiment of the present invention, and a dotted line represents the voltage of the second node QB of the gate driving unit in the prior art. As can be seen from the figure, the voltage of the second node QB in the prior art not only fluctuates greatly due to the coupling of the first node Q, but also decreases due to charge loss. The second node QB of the present application can maintain a higher and more stable voltage during the maintenance phase.

Fig. 6 shows a gate driving circuit of an embodiment of the present invention. For example, two sides of the gate driving unit include 1612 stages of gate driving units. The package structure of each gate driving unit is shown in fig. 7, and the pin positions of each gate driving unit in fig. 6 are the same as those in the package diagram of the gate driving unit in fig. 7, so the pin names are omitted in fig. 6. Fig. 7 shows a packaging schematic of the gate driving unit of fig. 3. The gate driving unit 320 is packaged to form a stage block, and the stage block includes at least a clock terminal clock1 and a clock terminal clock2 for receiving different clock signals, respectively, an input terminal for receiving a second high level DC, a first low level VGL, a first high level VGH, a second low level VSQ, a pre-charge signal Gn-4, a pull-down signal Gn +4, a first stabilizing signal Gn-2, a second stabilizing signal Gn +2, and an output terminal for outputting the gate driving signal Gn.

With continued reference to fig. 6, the principle of the gate driving unit stage1 to gate driving unit stage1611 on the left side will be described. Each stage of the gate driving unit receives the second high level DC, the first low level VGL, the first high level VGH, and the second low level VSQ.

The pre-charge signal Gn-4 and the first steady signal Gn-2 of the gate driving unit stage1 are both the first pulse signal STV1L, the pre-charge signal Gn-4 of the gate driving unit stage3 is also the first pulse signal STV1L, and in addition, the pre-charge signal Gn-4 of each stage of gate driving unit stage (n) is the gate driving signal Gn-4 of the gate driving unit stage (n-4), and the first steady signal Gn-2 is the gate driving signal Gn-2 of the gate driving unit stage (n-2).

The pull-down signal Gn +4 and the second maintenance signal Gn +2 of the gate driving unit stage1611 are both the second pulse signal STV2L, the pull-down signal Gn +4 of the gate driving unit stage1609 is also the second pulse signal STV2L, and in addition, the pull-down signal Gn +4 of each stage of gate driving unit stage (n) is the gate driving signal Gn +4 of the gate driving unit stage (n +4), and the second maintenance signal Gn +2 is the gate driving signal Gn +2 of the gate driving unit stage (n + 2).

A clock terminal clock1 of the gate driving unit stage1 receives the clock signal CLK1L, and a clock terminal clock2 receives the clock signal CLK 3L; a clock terminal clock1 of the gate driving unit stage3 receives the clock signal CLK2L, and a clock terminal clock2 receives the clock signal CLK 4L; a clock terminal clock1 of the gate driving unit stage5 receives the clock signal CLK3L, and a clock terminal clock2 receives the clock signal CLK 1L; a clock terminal clock1 of the gate driving unit stage7 receives the clock signal CLK4L, and a clock terminal clock2 receives the clock signal CLK 2L; … … the gate driving unit stage1605 has a clock terminal clock1 receiving the clock signal CLK3L and a clock terminal clock2 receiving the clock signal CLK 1L; a clock terminal clock1 of the gate driving unit stage1607 receives the clock signal CLK4L, and a clock terminal clock2 receives the clock signal CLK 2L; a clock terminal clock1 of the gate driving unit stage1609 receives the clock signal CLK1L, and a clock terminal clock2 receives the clock signal CLK 3L; the clock terminal clock1 of the gate driving unit stage1611 receives the clock signal CLK2L, and the clock terminal clock2 receives the clock signal CLK 4L.

The connection relationship of the gate driving unit on the right side of the gate driving circuit shown in fig. 6 is similar to that on the left side, and is not described herein again. In one possible embodiment, the first pulse signal STV1L, the second pulse signal STV2L, the clock signal CKL1L, and the clock signal CLK4L are generated by a timing controller.

Fig. 8 shows a signal timing diagram of the gate driving circuit of fig. 6. From top to bottom, there are the left first pulse signal STV1L, the right first pulse signal STV1R, the left second pulse signal STV2L, the right second pulse signal STV2R, the clock signal CLK1L, the clock signal CLK1R, the clock signal CLK2L, the clock signal CLK2R, the clock signal CLK3L, the clock signal CLK3R, the clock signal CLK4L, and the clock signal CLK4R, respectively. The first high level VGH and the second high level DC are always high level, and the first low level VGL and the second low level VSQ are always low level (not shown). The last bit of the clock signal is 'L' and represents the clock signal coupled with the left gate driving unit, and the last bit is 'R' and represents the clock signal coupled with the right gate driving unit.

It can be seen that the period of each clock signal is 8T, the duration of the high state is 3T, the first rising edge of the clock signal CLK1L lags time T4 by 12T, the clock signal CLK1R lags time T relative to the clock signal CLK1L by 1T, the clock signal CLK2L lags time T relative to the clock signal CLK1R, and so on. The high level of the left first pulse signal STV1L, the right first pulse signal STV1R, the left second pulse signal STV2L, and the right second pulse signal STV2R has a duration of 4T, the rising edge of the left first pulse signal STV1L lags behind time T4 by 9T, the falling edge of the right first pulse signal STV1R lags behind time T of 1T with respect to the left first pulse signal STV1L, the falling edge of the right second pulse signal STV2R leads time T by 13T with respect to time T5, and the left second pulse signal STV2L leads ahead of time T of the right second pulse signal STV2R by 1T.

As shown in fig. 8, the gate driving circuit shown in fig. 6 is supplied with timing signals, thereby causing the gate driving circuit 120 to output a desired waveform as shown in fig. 9. Fig. 9 is a timing diagram of a part of gate driving signals of the gate driving circuit of fig. 6. Referring to the gate driving signals output by the adjacent 7-stage gate driving units shown in fig. 9, it can be seen that, with the gate driving circuit composed of the gate driving units according to the embodiment of the present invention, each stage of gate driving unit can output good noise-free gate driving signals, and can be kept at a lower and more stable level at the stage of output stopping, and there is no problem of noise or malfunction caused by high temperature failure.

Fig. 10 is a schematic structural diagram showing a display device according to an embodiment of the present invention. As shown in fig. 10, in this embodiment, the display device 10 includes a display panel 100, a gate driving circuit 200, and a data driving circuit (not shown) for providing a plurality of gray-scale data, wherein the gate driving circuit 200 may be integrated on the same substrate as the display panel 100 to form an integrated gate driving circuit structure.

The display panel 100 includes pixel units (not shown) arranged in a row array, m scan lines for transmitting gate driving signals, and n data lines for transmitting gray scale data, where m and n are non-zero integers.

The gate driving circuit 200 includes a plurality of stages of gate driving units 300, wherein at least one stage of the gate driving units 300 employs the gate driving unit 320 provided by the present invention, and exemplarily, the gate driving units 300 in this embodiment each employ the gate driving unit 320 provided by the present invention. Each stage of the gate driving unit 300 outputs a corresponding gate driving signal through a corresponding scan line. In this embodiment, each stage of the gate driving unit 300 in the gate driving circuit 200 is connected to a corresponding one of the scan lines, and provides the gate driving signals G1 to Gm in response to the left-side first pulse signal and the right-side first pulse signal, so as to turn on the thin film transistors (not shown) in the pixel cells of each row by row. In the present embodiment, the gate driving units 300 corresponding to the left and right sides are respectively coupled to the scan lines in different rows, for example, the left gate driving unit 300 is respectively coupled to the scan lines in the odd-numbered rows, and the right gate driving unit 300 is respectively coupled to the scan lines in the even-numbered rows.

In one possible embodiment, the gate driving units 300 corresponding to the left and right sides of the gate driving circuit 200 are coupled to the scan lines in the same row.

Further, the gate driving unit 320, the gate driving circuit and the display device 10 provided in the foregoing embodiments of the invention can be used for both forward scanning and reverse scanning, and for application scenarios requiring only forward scanning and only reverse scanning, the invention provides the gate driving unit 320 shown in fig. 11 and 12, respectively.

In the gate driving unit 330 shown in fig. 11 according to another embodiment of the present invention, only the first dimensionally stable signal received by the second transistor T2 needs to be changed from Gn-2 to Gn-4, so that the application scenario that only needs to be scanned is satisfied, and in the gate driving circuit composed of the gate driving units 330, one input pin of Gn-2 is reduced for each stage of gate driving unit, and wiring of Gn-2 can be omitted, which is beneficial to saving layout area and further reducing frame width. The maintenance signal Gn-4 turns on the second transistor T2 to pull down the second node QB to the second low level VSQ while the precharge signal Gn-4 turns on the transistor T8 to precharge the first node Q.

In the gate driving unit 340 shown in fig. 12 according to another embodiment of the present invention, as compared to the gate driving unit 320, only the second stable signal received by the third transistor T3 needs to be changed from Gn +2 to Gn +4, so that the application scenario that only reverse scanning is required can be satisfied, in the gate driving circuit composed of the gate driving units 340, one input pin of Gn +2 is reduced for each stage of gate driving unit, and wiring of Gn +2 can also be omitted, which is beneficial to saving the layout area and further reducing the frame width.

In summary, in the gate driving unit and the gate driving circuit provided by the invention, the stability maintaining control unit controls the stability maintaining unit to pull down and maintain the stability of the gate driving signal of the gate driving unit of the current stage according to the first stability maintaining signal and the second stability maintaining signal.

It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A gate driving unit for driving corresponding scan lines on a display panel, the gate driving unit comprising:

an input module, coupled between a first high level and a first node, for charging the first node according to a precharge signal;

the output module is coupled with the first node and used for providing a grid driving signal of the current stage according to the voltage of the first node and a first clock signal; and

a pull-down maintenance module, coupled to the first node and the output module, for pulling down the first node to a first low level according to a pull-down signal and maintaining the first node and the gate driving signal of the present stage at a second low level according to a second high level and a maintenance signal,

wherein, the pull-down stability maintaining module comprises: the gate driving circuit comprises a gate driving signal of the current stage and a gate driving signal of the first node, and the gate driving signal of the current stage and the first node are maintained at a first low level according to the voltage of the first node.

2. The gate driving unit of claim 1, the stability-maintaining control unit comprising: and the first end and the control end of the first transistor are coupled with the second high level, the second end of the first transistor is coupled with the second node, the first end of the second transistor is coupled with the second node, the second end of the second transistor is coupled with the second low level, and the control end of the first transistor is coupled with the first stable signal.

3. The gate driving unit of claim 2, the stability-maintaining control unit further comprising: a third transistor, a first terminal of which is coupled to the second node, a second terminal of which is coupled to the second low level, and a control terminal of which is coupled to a second maintenance signal.

4. The gate driving unit of claim 3, the stability-maintaining control unit further comprising: a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second node, a second terminal of the fourth transistor is coupled to the second low level, and a control terminal of the fourth transistor is coupled to the gate driving signal of the current stage.

5. The gate driving unit of claim 1, wherein the pull-down maintenance module further comprises:

the pull-down transistor is coupled between a first low level and the first node, and the control end receives a pull-down signal and pulls down the voltage of the first node to a first low level according to the pull-down signal.

6. The gate driving unit of claim 1, wherein the dimensionally stable module comprises:

a fifth transistor coupled between the first node and the second low level; and a sixth transistor coupled between the gate driving signal and the second low level; wherein the content of the first and second substances,

the fifth transistor turns on or off a current path between the first node and the second low level according to an active state of the second node,

the sixth transistor turns on or off a current path between the gate driving signal and the second low level according to an active state of the second node.

7. The gate driving unit of claim 6, wherein the dimensionally stable module further comprises:

and a seventh transistor, coupled between the gate driving signal and a second low level, wherein the control terminal receives a second clock signal and periodically turns on a current path between the gate driving signal and the second low level according to the second clock signal.

8. The gate driving unit of claim 1, wherein the output module comprises:

an output transistor coupled between the first clock signal and the gate driving signal, and having a control terminal coupled to the first node;

and the capacitor is coupled between the control end and the second end of the output transistor.

9. A gate driving circuit comprising at least one stage of the gate driving unit according to any one of claims 1 to 8.

10. A display device, comprising:

a gate drive circuit as claimed in claim 9, for providing a plurality of gate drive signals;

a data driving circuit for providing a plurality of gray scale data; and

a display panel including a plurality of pixel units arranged in an array, and a plurality of scan lines and a plurality of data lines,

the display panel receives the gate driving signals through the scanning lines to select the pixel units according to rows, and receives the gray scale data through the data lines to provide the gray scale data for the selected pixel units to realize image display.