CN113990233A - Drive circuit, drive module and display device - Google Patents
Drive circuit, drive module and display device Download PDFInfo
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- CN113990233A CN113990233A CN202111226633.0A CN202111226633A CN113990233A CN 113990233 A CN113990233 A CN 113990233A CN 202111226633 A CN202111226633 A CN 202111226633A CN 113990233 A CN113990233 A CN 113990233A
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention provides a driving circuit, a driving module and a display device. The driving circuit comprises a driving signal output end, a first node control circuit, a first control circuit, a second node control circuit and a driving output circuit; the first node control circuit controls an input clock signal end to provide an input clock signal to a first node under the control of an input signal; the driving output circuit is respectively electrically connected with the first node, the second node and the driving signal output end and is used for controlling the driving signal output end to output driving signals under the control of the potential of the first node and the potential of the second node. The invention can prolong the service life of the driving module.
Description
Technical Field
The invention relates to the technical field of display, in particular to a driving circuit, a driving module and a display device.
Background
The related display device adopts an oxide material as an active layer material of the transistor, and the oxide material is easily influenced to drift the characteristics of the transistor, so that the threshold voltage of the transistor is easily increased, the conduction current of the transistor is reduced, and the driving capability is reduced. At the end of the service life of a driving module in the display device, a driving circuit in the driving module is subjected to long-term bias voltage or the influence of severe use environment, the threshold voltage is deviated, the cascaded attenuation inside the driving module is not serious, and a first node cannot be effectively charged, so that the driving circuit cannot be started, and the service life of the driving module is short.
Disclosure of Invention
The present invention provides a driving circuit, a driving module and a display device, which can solve the problem of short service life of the driving module.
In order to achieve the above object, an embodiment of the present invention provides a driving circuit, including a driving signal output terminal, a first node control circuit, a first control circuit, a second node control circuit, and a driving output circuit;
the first node control circuit is respectively electrically connected with an input end, an input clock signal end and a first node, and is used for controlling the input clock signal end to provide an input clock signal to the first node under the control of an input signal provided by the input end;
the first control circuit is electrically connected with the first node and used for controlling the potential of the first node;
the second node control circuit is electrically connected with a second node and used for controlling the potential of the second node;
the driving output circuit is electrically connected with the first node, the second node and the driving signal output end respectively, and is used for controlling the driving signal output end to output a driving signal under the control of the potential of the first node and the potential of the second node.
Optionally, the first node control circuit includes a first transistor;
the control electrode of the first transistor is electrically connected with the input end, the first electrode of the first transistor is electrically connected with the input clock signal end, and the second electrode of the first transistor is electrically connected with the first node.
Optionally, the driving circuit according to at least one embodiment of the present invention further includes a carry signal output terminal and a carry output circuit;
the carry output circuit is respectively electrically connected with the first node, the second node, the output clock signal end, the first voltage end and the carry signal output end, and is used for controlling the carry signal output end to be electrically connected with the output clock signal end under the control of the potential of the first node and controlling the carry signal output end to be communicated with the first voltage end under the control of the potential of the second node.
Optionally, the driving output circuit is further electrically connected to an output clock signal terminal and a second voltage terminal, and is configured to control the driving signal output terminal to be electrically connected to the output clock signal terminal under the control of the potential of the first node, and control the driving signal output terminal to be communicated with the second voltage terminal under the control of the potential of the second node;
the first control circuit is further respectively electrically connected with a reset end, an initial voltage end, the second node, the driving signal output end and the first voltage end, and is used for controlling the first node to be communicated with the first voltage end under the control of a reset signal provided by the reset end, controlling the first node to be communicated with the first voltage end under the control of a second initial voltage signal provided by the initial voltage end, controlling the second node to be communicated with the first voltage end under the control of the potential of the second node, and controlling the potential of the first node according to the driving signal.
Optionally, the second nodes include a first second node and a second node;
the second node control circuit is further electrically connected with the first control voltage end, the second control voltage end, the first node and the first voltage end respectively, and is used for controlling the potential of the first second node under the control of the first control voltage provided by the first control voltage end and the potential of the first node, and controlling the potential of the second node under the control of the second control voltage provided by the second control voltage end and the potential of the first node.
The embodiment of the invention also provides a driving module which comprises the multi-stage driving circuit.
Optionally, the driving circuit includes a carry signal output terminal; the first node circuit is electrically connected with a reset terminal; the driving module is electrically connected with 2A clock signal lines, wherein A is a positive integer;
the carry signal output end of the nth-stage driving circuit included by the driving module is electrically connected with the input end of the (N + A) th-stage driving circuit included by the driving module and is used for providing an input signal for the input end of the (N + A) th-stage driving circuit;
the carry signal output end of the Mth-level driving circuit included in the driving module is electrically connected with the reset end of the Mth-A-1-level driving circuit included in the driving module and used for providing a reset signal for the reset end of the Mth-A-1-level driving circuit;
the input end of the nth-stage driving circuit included in the driving module is electrically connected with a first starting voltage line;
n is a positive integer, M is an integer greater than A +1, and N is a positive integer less than or equal to N.
Optionally, an input clock signal end of the nth stage driving circuit is electrically connected to the first start voltage line.
Optionally, an input clock signal end of the a + B stage driving circuit included in the driving module may be electrically connected to a B-th clock signal line, where the B-th clock signal line is configured to provide an input clock signal for the input clock signal end of the a + B stage driving circuit included in the driving module;
b is a positive integer; when B cannot be divided by 2A, B is the remainder of B divided by 2A; when B is divisible by 2A, B equals 2A.
Optionally, an output clock signal end of a C-th stage driving circuit included in the driving module is electrically connected to a C-th clock signal line, and the C-th clock signal line provides an output clock signal for the output clock signal end of the C-th stage driving circuit included in the driving module;
c is a positive integer; when C cannot be divided by 2A, C is the remainder obtained by dividing C by 2A; when C is divisible by 2A, C equals 2A.
The embodiment of the invention also provides a display device which comprises the driving module.
Optionally, the display device includes two driving modules; the display device further comprises a display panel; the display panel includes a plurality of rows of pixel circuits;
the first driving module is arranged on a first side edge of the display panel, and the second driving module is arranged on a second side edge of the display panel;
the first driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits;
and the second driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits.
The driving circuit, the driving module and the display device control the input clock signal to be written into the first node through the first node control circuit under the control of the input signal; when the characteristics of each transistor in the driving circuit have certain drift, the internal cascade signal in the driving module is attenuated, and the attenuation only affects the grid potential of the transistor in the first node control circuit and does not affect the drain signal of the transistor, so that the influence of the cascade attenuation on the charging of the first node can be reduced to the maximum extent, the difference between the potential of the first node in the first-stage driving circuit in the driving module and the potential of the first node in the last-stage driving circuit in the driving module is greatly shortened, and the service life of the driving module is prolonged.
Drawings
Fig. 1 is a structural diagram of a driving circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a driving circuit according to at least one embodiment of the invention;
FIG. 3 is a block diagram of a driving circuit according to at least one embodiment of the invention;
FIG. 4 is a block diagram of a driving circuit according to at least one embodiment of the invention;
FIG. 5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;
FIG. 6 is a timing diagram illustrating the operation of the driving circuit shown in FIG. 5 according to the present invention;
fig. 7 is a schematic connection diagram of a multi-stage driving circuit included in the driving module according to at least one embodiment of the invention;
FIG. 8 is a timing diagram illustrating operation of the driving module shown in FIG. 7 according to at least one embodiment of the present invention;
fig. 9 is a simulation timing diagram of the driving module according to the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.
As shown in fig. 1, the driving circuit according to the embodiment of the present invention includes a driving signal output terminal OUT, a first node control circuit 11, a first control circuit 12, a second node control circuit 13, and a driving output circuit 14;
the first node control circuit 11 is electrically connected to an input terminal IN, an input clock signal terminal IN _ CLK, and a first node P1, respectively, and is configured to control the input clock signal terminal IN _ CLK to provide an input clock signal to the first node P1 under the control of an input signal provided by the input terminal IN;
the first control circuit 12 is electrically connected to the first node P1 for controlling the potential of the first node P1;
the second node control circuit 13 is electrically connected to a second node P2 for controlling the potential of the second node P2;
the driving output circuit 14 is electrically connected to the first node P1, the second node P2 and the driving signal output terminal OUT, respectively, and is configured to control the driving signal output terminal OUT to output a driving signal under the control of the potential of the first node P1 and the potential of the second node P2.
In the driving circuit according to the embodiment of the present invention, the first node control circuit 11 controls writing of the input clock signal to the first node P1 under the control of the input signal. When the characteristics of each transistor in the driving circuit have a certain degree of drift, the internal cascade signal in the driving module attenuates, and the attenuation only affects the gate potential of the transistor in the first node control circuit 11, but does not affect the drain signal of the transistor, so that the influence of the cascade attenuation on the charging of the first node P1 can be reduced to the maximum extent, the difference between the potential of the first node in the first-stage driving circuit in the driving module and the potential of the first node in the last-stage driving circuit in the driving module is greatly shortened, and the service life of the driving module is prolonged.
In at least one embodiment of the present invention, the first node may be a pull-up node, and the second node may be a pull-down node, but not limited thereto.
Optionally, the first node control circuit includes a first transistor;
the control electrode of the first transistor is electrically connected with the input end, the first electrode of the first transistor is electrically connected with the input clock signal end, and the second electrode of the first transistor is electrically connected with the first node.
As shown in fig. 2, on the basis of the embodiment of the pixel circuit shown in fig. 1, the driving circuit according to at least one embodiment of the present invention may further include a carry signal output terminal OUT _ C and a carry output circuit 20;
the carry output circuit 20 is electrically connected to the first node P1, the second node P2, the output clock signal terminal CLK, the first voltage terminal V1 and the carry signal output terminal OUT _ C, respectively, and is configured to control the carry signal output terminal OUT _ C to be electrically connected to the output clock signal terminal CLK under the control of the potential of the first node P1, and to control the carry signal output terminal OUT _ C to be electrically connected to the first voltage terminal V1 under the control of the potential of the second node P2.
In at least one embodiment of the present invention, the first voltage terminal V1 can be a first low voltage terminal, but is not limited thereto.
In at least one embodiment of the present invention, the carry signal provided by the carry signal output terminal OUT _ C is used for cascade connection.
As shown in fig. 3, in addition to at least one embodiment of the pixel circuit shown in fig. 2, the driving output circuit 14 is further electrically connected to an output clock signal terminal CLK and a second voltage terminal V2 respectively, for controlling the driving signal output terminal OUT to be electrically connected to the output clock signal terminal CLK under the control of the potential of the first node P1, controlling the communication between the driving signal output terminal OUT and the second voltage terminal V2 under the control of the potential of the second node P2, and controlling the potential of the first node P1 according to the driving signal;
the first control circuit 12 is further electrically connected to a reset terminal Rpu, a start voltage terminal STV, the second node P2, the driving signal output terminal OUT and the first voltage terminal V1, respectively, and is configured to control communication between the first node P1 and the first voltage terminal V1 under control of a reset signal provided by the reset terminal Rpu, control communication between the first node P1 and the first voltage terminal V1 under control of a second start voltage signal provided by the start voltage terminal STV, control communication between the first node P1 and the first voltage terminal V1 under control of a potential of the second node P2, and control a potential of the first node P1 according to the driving signal.
In at least one embodiment shown in fig. 3, the second voltage terminal may be a second low voltage terminal, but is not limited thereto.
In particular implementation, the second node may include a first second node and a second node;
the second node control circuit is further electrically connected with the first control voltage end, the second control voltage end, the first node and the first voltage end respectively, and is used for controlling the potential of the first second node under the control of the first control voltage provided by the first control voltage end and the potential of the first node, and controlling the potential of the second node under the control of the second control voltage provided by the second control voltage end and the potential of the first node.
As shown in fig. 4, based on at least one embodiment of the pixel circuit shown in fig. 3, the second nodes include a first second node P21 and a second node P22;
the second node control circuit 13 is further electrically connected to a first control voltage terminal VDD1, a second control voltage terminal VDD2, the first node P1 and a first voltage terminal V1, respectively, for controlling the potential of the first second node P21 under the control of the first control voltage provided by the first control voltage terminal VDD1 and the potential of the first node P1, and controlling the potential of the second node P22 under the control of the second control voltage provided by the second control voltage terminal VDD2 and the potential of the first node P1;
the first control circuit 12 is electrically connected to a first second node P21 and a second node P22, respectively, and is configured to control communication between the first node P1 and the first voltage terminal V1 under the control of the potential of the first second node P21, and control communication between the first node P1 and the first voltage terminal V1 under the control of the potential of the second node P22;
the driving output circuit 14 is electrically connected to a first second node P21 and a second node P22, respectively, and is configured to control communication between the driving signal output terminal OUT and the second voltage terminal V2 under the control of the potential of the first second node P21, and control communication between the driving signal output terminal OUT and the second voltage terminal V2 under the control of the potential of the second node P22;
the carry output circuit 20 is electrically connected to the first second node P21 and the second node P22, respectively, and is configured to control communication between the carry signal output terminal OUT _ C and the first voltage terminal V1 under the control of the potential of the first second node P21, and control communication between the carry signal output terminal OUT _ C and the first voltage terminal V1 under the control of the potential of the second node P22.
In at least one embodiment of the driving circuit shown in fig. 4, the second nodes include a first second node P21 and a second node P22, the first control voltage provided by VDD1 and the second control voltage provided by VDD2 are opposite in phase, the first control voltage and the second control voltage are switched between high and low voltages every 2s-3s, and the potential of P21 and the potential of P22 are alternately changed to high voltages.
As shown in fig. 5, on the basis of at least one embodiment of the driving circuit shown in fig. 4, the first node control circuit 11 includes a first transistor M1;
the gate of the first transistor M1 is electrically connected to the input terminal IN, the drain of the first transistor M1 is electrically connected to the input clock signal terminal IN _ CLK, and the source of the first transistor M1 is electrically connected to the first node P1;
the first control circuit 12 includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a storage capacitor C;
a gate of the second transistor M2 is electrically connected to the reset terminal Rpu, a drain of the second transistor M2 is electrically connected to the first node P1, a source of the second transistor M2 is electrically connected to a first low voltage terminal LVGL, and the first low voltage terminal LVGL is configured to provide a first low voltage signal;
a gate of the third transistor M3 is electrically connected to the first second node P21, a drain of the third transistor M3 is electrically connected to the first node P1, and a source of the third transistor M3 is electrically connected to the first low voltage terminal LVGL;
a gate of the fourth transistor M4 is electrically connected to the second node P21, a drain of the fourth transistor M4 is electrically connected to the first node P1, and a source of the fourth transistor M4 is electrically connected to the first low voltage terminal LVGL;
a gate of the fifth transistor M5 is electrically connected to the start voltage terminal STV, a drain of the fifth transistor M5 is electrically connected to the first node P1, and a source of the fifth transistor M5 is electrically connected to the first low voltage terminal LVGL;
a first end of the storage capacitor C is electrically connected to a first node P1, and a second end of the storage capacitor C is electrically connected to the driving signal output end OUT;
the second node control circuit 13 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11;
a gate of the sixth transistor M6 and a drain of the sixth transistor M6 are electrically connected to the first control voltage terminal VDD1, and a source of the sixth transistor M6 is electrically connected to the first second node P21;
a gate of the seventh transistor M7 is electrically connected to the first node P1, a drain of the seventh transistor M7 is electrically connected to the first second node P21, and a source of the seventh transistor M7 is electrically connected to the first low voltage terminal LVGL;
a gate of the eighth transistor M8 is electrically connected to the input terminal IN, a drain of the eighth transistor M8 is electrically connected to the first second node P21, and a source of the seventh transistor M7 is electrically connected to the first low voltage terminal LVGL;
a gate of the ninth transistor M9 and a drain of the ninth transistor M9 are electrically connected to the second control voltage terminal VDD2, and a source of the ninth transistor M9 is electrically connected to the second node P22;
a gate of the tenth transistor M10 is electrically connected to the first node P1, a drain of the tenth transistor M10 is electrically connected to the second node P22, and a source of the tenth transistor M10 is electrically connected to the first low voltage terminal LVGL;
a gate of the eleventh transistor M11 is electrically connected to the input terminal IN, a drain of the eleventh transistor M11 is electrically connected to the second node P22, and a source of the eleventh transistor M11 is electrically connected to the first low voltage terminal LVGL;
the driving output circuit 14 includes a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14;
a gate of the twelfth transistor M12 is electrically connected to the first node P1, a drain of the twelfth transistor M12 is electrically connected to the output clock signal terminal CLK, and a source of the twelfth transistor M12 is electrically connected to the driving signal output terminal OUT;
a gate of the thirteenth transistor M13 is electrically connected to the first second node P21, a drain of the thirteenth transistor M13 is electrically connected to the driving signal output terminal OUT, and a source of the thirteenth transistor M13 is electrically connected to the second low voltage terminal VGL; the second low voltage terminal VGL is used for providing a second low voltage signal;
a gate of the fourteenth transistor M14 is electrically connected to the second node P22, a drain of the fourteenth transistor M14 is electrically connected to the driving signal output terminal OUT, and a source of the fourteenth transistor M14 is electrically connected to the second low voltage terminal VGL;
the carry output circuit 20 includes a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17;
a gate of the fifteenth transistor M15 is electrically connected to the first node P1, a drain of the fifteenth transistor M15 is electrically connected to the output clock signal terminal CLK, and a source of the fifteenth transistor M15 is electrically connected to the carry signal output terminal OUT _ C;
a gate of the sixteenth transistor M16 is electrically connected to the first second node P21, a drain of the sixteenth transistor M16 is electrically connected to the carry signal output terminal OUT _ C, and a source of the thirteenth transistor M16 is electrically connected to the second low voltage terminal VGL;
the gate of the seventeenth transistor M17 is electrically connected to the second node P22, the drain of the seventeenth transistor M17 is electrically connected to the carry signal output terminal OUT _ C, and the source of the seventeenth transistor M17 is electrically connected to the second low voltage terminal VGL.
In at least one embodiment of the driving circuit shown in fig. 5, all the transistors are n-type transistors, the first voltage terminal may be the first low voltage terminal LVGL, and the second voltage terminal may be the second low voltage terminal VGL, but not limited thereto.
As shown in fig. 6, when the driving circuit shown in fig. 5 of the present invention is in operation, taking VDD1 providing a high voltage signal and VDD2 providing a low voltage signal as an example, the driving cycle includes an input phase t1, an output phase t2, and a reset phase t 3;
IN an input phase t1, IN provides a high voltage signal, IN _ CLK provides a high voltage signal, STV provides a low voltage signal, Rpu provides a low voltage signal, CLK provides a low voltage signal, M1 is turned on to raise the potential of P1, M6 is turned on, M7 and M8 are turned on, the potential of P21 is low, M9 is turned off, M10 and M11 are turned on, the potential of P22 is low, M12 is turned on, M13 and M14 are turned off, OUT outputs a low voltage signal, M15 is turned on, M16 and M17 are turned off, and OUT _ C provides a low voltage signal;
IN the output phase t2, IN provides a low voltage signal, STV provides a low voltage signal, Rpu provides a low voltage signal, CLK provides a high voltage signal, M1 is turned off, the potential of P1 is maintained at a high voltage, M6 is turned on, M7 is turned on, M8 is turned off, the potential of P21 is at a low voltage, M9 is turned off, M10 is turned on, M11 is turned off, the potential of P22 is at a low voltage, M12 is turned on, M13 and M14 are turned off, OUT outputs a high voltage signal, the potential of P1 is bootstrapped by the coupling effect of the storage capacitor C, M15 is turned on, M16 and M17 are turned off, and OUT _ C provides a high voltage signal;
IN the reset phase t3, IN provides a low voltage signal, STV provides a low voltage signal, Rpu provides a high voltage signal, M1 turns off, M2 turns on to pull the potential of P1 low to a low voltage, M6 turns on, M7 and M8 turn off, the potential of P21 is a high voltage, M9 turns off, M10 and M11 turn off, the potential of P22 remains low, M12 turns off, M13 turns on, M14 turns off, OUT outputs a low voltage signal, M15 turns off, M16 turns on, M17 turns off, and OUT _ C provides a low voltage signal.
In operation of at least one embodiment of the driving circuit of the present invention as shown in fig. 5, at a predetermined time period in two adjacent frame times, STV provides a high voltage signal, M5 is turned on to communicate between P1 and LVGL to reset the potential of P1.
In the related art, the active layer of the transistor in the driving circuit may be made of an oxide material, such as IGZO (indium gallium zinc oxide). The oxide material is the most active layer material, has the advantage of high mobility, can be suitable for high-frequency and high-resolution products, and can reduce the size of a transistor, save the frame of a display panel, improve the aperture opening ratio of pixels and reduce power consumption. However, the oxide material is easily affected by O2, H2O, H-Ion (negative hydrogen Ion) and temperature, and changes channel characteristics or degrades stability of the transistor, which causes a forward shift in characteristics of the transistor, and increases a threshold voltage of the transistor, reduces an on current Ion, and degrades driving capability. When the driving circuit is used, under the action of electromagnetic radiation and circuit coupling, a key node in the circuit can generate noise to influence the normal output of the driving circuit, so that a noise reduction circuit (the noise reduction circuit can comprise M3, M4, M13, M14, M16 and M17) is added in the driving circuit, when the noise reduction is carried OUT on a driving signal output end OUT of the driving circuit, the potential of a second node is kept at a high voltage for a long time, when the potential of P21 is kept at the high voltage for a long time, the drain-source voltage of M7 is larger, when the potential of P22 is kept at the high voltage for a long time, the drain-source voltage of M10 is larger, and when an oxide transistor is in a high-voltage-difference environment for a long time, the characteristic is more easily degraded, the threshold voltage of the oxide transistor continuously drifts, and when the driving capacity of the driving circuit at the end of the service life is reduced, the voltage lifting capacity of a first node is weak, the M7 or M10 fails to start, and the first node and the second node fails to compete, in a time period when the potential of the first node needs to be high voltage, the potential of the second node still keeps high voltage, so that the potential of the first node cannot rise to high voltage, the driving circuit cannot normally output, and the driving circuit fails.
In the related art, taking a 4K 240Hz (hertz) display product as an example, the resolution of the product is 3840 × 2160, which includes 2160 rows of pixels, and a pixel may include three pixel circuits, that is, 2160 stages of driving circuits are required to drive the 2160 rows of pixels, each row of pixels is electrically connected to a row of gate lines, each stage of driving circuits is electrically connected to a row of gate lines, wherein M12 is a transistor for outputting a driving signal in the driving circuit, each row of gate lines is loaded with 3840 × 3 transistors for outputting the driving signal, the resistance and the capacitance are relatively large, the refresh frequency of 240Hz makes the actual charging time of each row of pixels only 1.85us, and therefore the size of the transistor for outputting the driving signal is relatively large to ensure the driving capability. The cascade relation among the driving circuits is taken charge of by M15, for the driving module electrically connected with six clock signal lines, the P-th driving circuit provides input signals (P is a positive integer) for the P + 3-th driving circuit, the P + 1-th driving circuit provides input signals for the P + 4-th driving circuit, the P-th driving circuit provides reset signals for the P-4-th driving circuit, the P + 1-th driving circuit provides reset signals for the P-3-th driving circuit, the grid voltage and drain voltage of M1 in the P-th driving circuit are provided by the P-3-th driving circuit, namely, the carry signal output end of the P-3-th driving circuit loads the source capacitance of M1 in the P-th driving circuit and the drain capacitance of M1 in the P-th driving circuit, so that the high voltage waveform of the carry signal end of the P-3-th driving circuit is delayed, meanwhile, the threshold voltage of the M15 is not zero, and as the service time is prolonged, the characteristic drifts, which causes the voltage value of the high voltage signal output by the carry signal output terminal to be slightly lower than the potential of the output clock signal provided by the CLK, that is, the voltage of the first node of the P-th stage driving circuit to the gate of the M15 is weakened, the conduction current of the M15 is reduced, the carry signal output terminal provided by the P-th stage driving circuit is output to the M1 of the P + 3-th stage driving circuit, the potential of the first node of the P + 3-th stage driving circuit is further reduced, which affects the turn-on of the M15, that is, the carry signal output by the P + 3-th stage driving circuit is weakened, and so on, the potential of the first node of the 2160-th stage driving circuit is attenuated relative to the potential of the first node of the first stage driving circuit. At the end of the service life of the driving module, a driving circuit in the driving module is subjected to long-term bias voltage or the influence of severe use environment, the threshold voltage is deviated, the cascade attenuation inside the driving module is not serious, and the first node cannot be effectively charged, so that the driving circuit cannot be started.
Based on this, the embodiment of the invention controls the input clock signal to be written into the first node through the first node control circuit under the control of the input signal. When the characteristics of each transistor in the driving circuit have certain drift, the internal cascade signal in the driving module attenuates, and the attenuation only affects the grid potential of the transistor in the first node control circuit and does not affect the drain signal of the transistor, so that the influence of the cascade attenuation on the charging of the first node can be reduced to the maximum extent, the difference between the potential of the first node in the first-stage driving circuit in the driving module and the potential of the first node in the last-stage driving circuit in the driving module is greatly shortened, the service life of the driving module is prolonged, and the service life can be prolonged by 8 times.
The driving module provided by the embodiment of the invention comprises a plurality of stages of driving circuits.
In at least one embodiment of the present invention, the driving circuit may include a carry signal output terminal; the first control circuit is electrically connected with the reset end; the driving module is electrically connected with 2A clock signal lines, wherein A is a positive integer;
the carry signal output end of the nth-stage driving circuit included by the driving module is electrically connected with the input end of the (N + A) th-stage driving circuit included by the driving module and is used for providing an input signal for the input end of the (N + A) th-stage driving circuit;
the carry signal output end of the Mth-level driving circuit included in the driving module is electrically connected with the reset end of the Mth-A-1-level driving circuit included in the driving module and used for providing a reset signal for the reset end of the Mth-A-1-level driving circuit;
the input end of the nth-stage driving circuit included in the driving module is electrically connected with a first starting voltage line;
n is a positive integer, M is an integer greater than A +1, and N is a positive integer less than or equal to N.
In a specific implementation, the input clock signal terminal of the nth stage driving circuit may be electrically connected to the first start voltage line.
For example, when a is equal to 3, the driving module is electrically connected to six clock signal lines, the carry signal output terminal of the first stage driving circuit included in the driving module is electrically connected to the input terminal of the fourth stage driving circuit included in the driving module, and is configured to provide an input signal for the fourth stage driving circuit, the carry signal output terminal of the fifth stage driving circuit included in the driving module and the reset terminal of the first stage driving circuit included in the driving module provide a reset signal, and the input terminal of the third stage driving circuit included in the driving module and the input clock signal terminal of the third stage driving circuit are electrically connected to a first start voltage line.
For example, when a is equal to 4, the driving module is electrically connected to eight clock signal lines, the carry signal output terminal of the first stage driving circuit included in the driving module is electrically connected to the input terminal of the fifth stage driving circuit included in the driving module, and is configured to provide an input signal for the fifth stage driving circuit, the carry signal output terminal of the sixth stage driving circuit included in the driving module and the reset terminal of the first stage driving circuit included in the driving module provide a reset signal, and the input terminal of the fourth stage driving circuit included in the driving module and the input clock signal terminal of the fourth stage driving circuit are electrically connected to a first start voltage line.
For example, when a is equal to 2, the driving module is electrically connected to four clock signal lines, the carry signal output terminal of the first stage driving circuit included in the driving module is electrically connected to the input terminal of the third stage driving circuit included in the driving module, and is configured to provide an input signal for the third stage driving circuit, the carry signal output terminal of the fourth stage driving circuit included in the driving module and the reset terminal of the first stage driving circuit included in the driving module provide a reset signal, and the input terminals of the first two stages of driving circuits included in the driving module and the input clock signal terminals of the first two stages of driving circuits are electrically connected to a first start voltage line.
In specific implementation, an input clock signal end of an a + B stage driving circuit included in the driving module may be electrically connected to a B-th clock signal line, where the B-th clock signal line is used to provide an input clock signal for the input clock signal end of the a + B stage driving circuit included in the driving module;
b is a positive integer, and when B cannot be divided by 2A, B is the remainder obtained by dividing B by 2A; when B is divisible by 2A, B equals 2A. For example, when a is equal to 3, an input clock signal terminal of a fourth-stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an input clock signal for the fourth-stage driving circuit; an input clock signal end of a fifth driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an input clock signal for the fifth-stage driving circuit; an input clock signal end of a sixth driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an input clock signal for the sixth-stage driving circuit; an input clock signal end of a seventh driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an input clock signal for the seventh-stage driving circuit; an input clock signal end of an eighth driving circuit included in the driving module can be electrically connected with a fifth clock signal line, and the fifth clock signal line is used for providing an input clock signal for the eighth-stage driving circuit; an input clock signal end of a ninth driving circuit included in the driving module may be electrically connected to a sixth clock signal line, and the sixth clock signal line is configured to provide an input clock signal for the ninth driving circuit; and so on;
for example, when a is equal to 2, an input clock signal terminal of a third stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an input clock signal for the third stage driving circuit; the input clock signal end of a fourth driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an input clock signal for the fourth-stage driving circuit; an input clock signal end of a fifth driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an input clock signal for the fifth-stage driving circuit; an input clock signal end of a sixth driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an input clock signal for the sixth-stage driving circuit; and so on;
for example, when a is equal to 4, an input clock signal terminal of a fifth stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an input clock signal for the fifth stage driving circuit; an input clock signal end of a sixth driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an input clock signal for the sixth-stage driving circuit; an input clock signal end of a seventh driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an input clock signal for the seventh-stage driving circuit; an input clock signal end of an eighth driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an input clock signal for the eighth-stage driving circuit; an input clock signal end of a ninth driving circuit included in the driving module may be electrically connected to a fifth clock signal line, and the fifth clock signal line is configured to provide an input clock signal for the ninth driving circuit; an input clock signal end of a tenth driving circuit included in the driving module may be electrically connected to a sixth clock signal line, and the sixth clock signal line is configured to provide an input clock signal for the tenth driving circuit; an input clock signal end of an eleventh driving circuit included in the driving module can be electrically connected with a seventh clock signal line, and the seventh clock signal line is used for providing an input clock signal for the eleventh-stage driving circuit; an input clock signal end of a twelfth driving circuit included in the driving module can be electrically connected with an eighth clock signal line, and the eighth clock signal line is used for providing an input clock signal for the twelfth-stage driving circuit; and so on.
In at least one embodiment of the present invention, an output clock signal terminal of a C-th stage driving circuit included in the driving module is electrically connected to a C-th clock signal line, and the C-th clock signal line provides an output clock signal for the output clock signal terminal of the C-th stage driving circuit included in the driving module;
c is a positive integer; when C cannot be divided by 2A, C is the remainder obtained by dividing C by 2A; when C is divisible by 2A, C equals 2A.
For example, when a is equal to 3, an output clock signal terminal of a first stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an output clock signal for the first stage driving circuit; the output clock signal end of a second-stage driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an output clock signal for the second-stage driving circuit; an output clock signal end of a third-stage driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an output clock signal for the third-stage driving circuit; the output clock signal end of a fourth stage driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an output clock signal for the fourth stage driving circuit; an output clock signal end of a fifth-stage driving circuit included in the driving module can be electrically connected with a fifth clock signal line, and the fifth clock signal line is used for providing an output clock signal for the fifth-stage driving circuit; an output clock signal end of a sixth-stage driving circuit included in the driving module can be electrically connected with a sixth clock signal line, and the sixth clock signal line is used for providing an output clock signal for the sixth-stage driving circuit;
for example, when a is equal to 2, an output clock signal terminal of a first stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an output clock signal for the first stage driving circuit; the output clock signal end of a second-stage driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an output clock signal for the second-stage driving circuit; an output clock signal end of a third-stage driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an output clock signal for the third-stage driving circuit; the output clock signal end of a fourth stage driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an output clock signal for the fourth stage driving circuit;
for example, when a is equal to 4, an output clock signal terminal of a first stage driving circuit included in the driving module may be electrically connected to a first clock signal line, where the first clock signal line is used to provide an output clock signal for the first stage driving circuit; the output clock signal end of a second-stage driving circuit included in the driving module can be electrically connected with a second clock signal line, and the second clock signal line is used for providing an output clock signal for the second-stage driving circuit; an output clock signal end of a third-stage driving circuit included in the driving module can be electrically connected with a third clock signal line, and the third clock signal line is used for providing an output clock signal for the third-stage driving circuit; the output clock signal end of a fourth stage driving circuit included in the driving module can be electrically connected with a fourth clock signal line, and the fourth clock signal line is used for providing an output clock signal for the fourth stage driving circuit; an output clock signal end of a fifth-stage driving circuit included in the driving module can be electrically connected with a fifth clock signal line, and the fifth clock signal line is used for providing an output clock signal for the fifth-stage driving circuit; an output clock signal end of a sixth-stage driving circuit included in the driving module can be electrically connected with a sixth clock signal line, and the sixth clock signal line is used for providing an output clock signal for the sixth-stage driving circuit; an output clock signal end of a seventh-stage driving circuit included in the driving module can be electrically connected with a seventh clock signal line, and the seventh clock signal line is used for providing an output clock signal for the seventh-stage driving circuit; an output clock signal end of an eighth-stage driving circuit included in the driving module may be electrically connected to an eighth clock signal line, and the eighth clock signal line is configured to provide an output clock signal for the eighth-stage driving circuit.
The display device provided by the embodiment of the invention comprises the driving module.
Optionally, the display device includes two driving modules; the display device further comprises a display panel; the display panel includes a plurality of rows of pixel circuits;
the first driving module is arranged on a first side edge of the display panel, and the second driving module is arranged on a second side edge of the display panel;
the first driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits;
and the second driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits.
In a specific implementation, when a display panel in the display device is a large-sized display panel, the display device may include two driving modules, where the two driving modules are respectively disposed at opposite sides of the display panel, for example, a first driving module may be disposed at a left side of the display panel, and a second driving module may be disposed at a right side of the display panel;
the display panel may further include a plurality of rows of gate lines, each row of pixel circuits may be electrically connected to one row of gate lines, each stage of driving circuits in the first driving module may be electrically connected to a left end of one row of gate lines, respectively, and each stage of driving circuits in the second driving module may be electrically connected to a right end of one row of gate lines.
As shown in fig. 7, a Gate1 is labeled as a first row of Gate lines, a Gate2 is labeled as a second row of Gate lines, a Gate3 is labeled as a third row of Gate lines, a Gate4 is labeled as a fourth row of Gate lines, a Gate5 is labeled as a fifth row of Gate lines, and a Gate6 is labeled as a sixth row of Gate lines;
a first-stage driving circuit which is included in the first driving module and is denoted by G11, a second-stage driving circuit which is included in the first driving module and is denoted by G12, a third-stage driving circuit which is included in the first driving module and is denoted by G13, a fourth-stage driving circuit which is included in the first driving module and is denoted by G14, a fifth-stage driving circuit which is included in the first driving module and is denoted by G15, and a sixth-stage driving circuit which is included in the first driving module and is denoted by G16;
a first-stage driving circuit denoted by G21 and included in the second driving module, a second-stage driving circuit denoted by G22 and included in the second driving module, a third-stage driving circuit denoted by G23 and included in the second driving module, a fourth-stage driving circuit denoted by G24 and included in the second driving module, a fifth-stage driving circuit denoted by G25 and included in the second driving module, and a sixth-stage driving circuit denoted by G26 and included in the second driving module.
In at least one embodiment shown in fig. 7, the driving module is electrically connected to six clock signal lines, a is equal to 3.
IN fig. 7, reference numeral STV is a start voltage terminal of each stage of the driving circuit, reference numeral CLK is an output clock signal terminal of each stage of the driving circuit, reference numeral IN _ CLK is an input clock signal terminal of each stage of the driving circuit, reference numeral IN is an input terminal of each stage of the driving circuit, reference numeral OUT is a driving signal output terminal of each stage of the driving circuit, and reference numeral OUT _ C is a carry signal output terminal of each stage of the driving circuit; the label Rpu is the reset end of each stage of driving circuit;
as shown in fig. 7, the start voltage terminal of G11, the start voltage terminal of G12, the start voltage terminal of G13, the start voltage terminal of G14, the start voltage terminal of G15, and the start voltage terminal of G16 are electrically connected to a second start voltage line STV2, the second start voltage line STV2 being used to supply a second start voltage signal;
the input clock signal terminal of G11, the input clock signal terminal of G12, and the input clock signal terminal of G13 are electrically connected to a first start voltage line STV1, the first start voltage line STV1 supplying a first start voltage signal;
an input clock signal terminal of G14 is electrically connected to the first clock signal line CLK1, an input clock signal terminal of G15 is electrically connected to the second clock signal line CLK2, and an input clock signal terminal of G16 is electrically connected to the third clock signal line CLK 3;
the input terminal of G11, the input terminal of G12, and the input terminal of G13 are all electrically connected to the first start voltage line STV 1;
the driving signal output end of G11 is electrically connected with a Gate1, the driving signal output end of G12 is electrically connected with a Gate2, the driving signal output end of G13 is electrically connected with a Gate3, the driving signal output end of G14 is electrically connected with a Gate4, the driving signal output end of G15 is electrically connected with a Gate5, and the driving signal output end of G16 is electrically connected with a Gate 6;
the input end of G14 is electrically connected with the carry signal output end of G11, the input end of G15 is electrically connected with the carry signal output end of G12, and the input end of G16 is electrically connected with the carry signal output end of G13;
the carry signal output end of G15 is electrically connected with the reset end of G11, and the carry signal output end of G16 is electrically connected with the reset end of G12;
an output clock signal terminal of G11 is electrically connected to the first clock signal line CLK1, an output clock signal terminal of G12 is electrically connected to the second clock signal line CLK2, an output clock signal terminal of G13 is electrically connected to the third clock signal line CLK3, an output clock signal terminal of G14 is electrically connected to the fourth clock signal line CLK4, an output clock signal terminal of G15 is electrically connected to the fifth clock signal line CLK5, and an output clock signal terminal of G16 is electrically connected to the sixth clock signal line CLK 6;
a start voltage terminal of G21, a start voltage terminal of G22, a start voltage terminal of G23, a start voltage terminal of G24, a start voltage terminal of G25, and a start voltage terminal of G26 are electrically connected to a second start voltage line STV2, the second start voltage line STV2 being for supplying a second start voltage signal;
the input clock signal terminal of G21, the input clock signal terminal of G22, and the input clock signal terminal of G23 are electrically connected to a first start voltage line STV1, the first start voltage line STV1 supplying a first start voltage signal;
an input clock signal terminal of G24 is electrically connected to the first clock signal line CLK1, an input clock signal terminal of G25 is electrically connected to the second clock signal line CLK2, and an input clock signal terminal of G26 is electrically connected to the third clock signal line CLK 3;
the input terminal of G21, the input terminal of G22, and the input terminal of G23 are all electrically connected to the first start voltage line STV 1;
the driving signal output end of G21 is electrically connected with a Gate1, the driving signal output end of G22 is electrically connected with a Gate2, the driving signal output end of G23 is electrically connected with a Gate3, the driving signal output end of G24 is electrically connected with a Gate4, the driving signal output end of G25 is electrically connected with a Gate5, and the driving signal output end of G26 is electrically connected with a Gate 6;
the input end of G24 is electrically connected with the carry signal output end of G21, the input end of G25 is electrically connected with the carry signal output end of G22, and the input end of G26 is electrically connected with the carry signal output end of G23;
the carry signal output end of G25 is electrically connected with the reset end of G21, and the carry signal output end of G26 is electrically connected with the reset end of G22;
an output clock signal terminal of G21 is electrically connected to the first clock signal line CLK1, an output clock signal terminal of G22 is electrically connected to the second clock signal line CLK2, an output clock signal terminal of G23 is electrically connected to the third clock signal line CLK3, an output clock signal terminal of G24 is electrically connected to the fourth clock signal line CLK4, an output clock signal terminal of G25 is electrically connected to the fifth clock signal line CLK5, and an output clock signal terminal of G26 is electrically connected to the sixth clock signal line CLK 6.
In fig. 7, reference numeral VDD1 is a first control voltage terminal, reference numeral VDD2 is a second control voltage terminal, reference numeral LVGL is a first low voltage terminal, and reference numeral VGL is a second low voltage terminal.
As shown in fig. 8, when at least one embodiment of the driving module shown in fig. 7 is operated, the first control voltage provided by VDD1 and the second control voltage provided by VDD2 perform high-low voltage conversion every 2s to 3 s;
the first low voltage signal provided by the LVGL and the second low voltage signal provided by the VGL may be dc voltage signals;
but not limited thereto.
As shown in fig. 8, when the driving module shown in fig. 7 is operated in at least one embodiment, the duty ratio of the first clock signal provided by CLK1, the duty ratio of the second clock signal provided by CLK2, the duty ratio of the third clock signal provided by CLK3, the duty ratio of the fourth clock signal provided by CLK4, the duty ratio of the fifth clock signal provided by CLK5 and the duty ratio of the sixth clock signal provided by CLK6 are 50%;
the second clock signal is delayed by 1H (1H is one line driving time) from the first clock signal, the third clock signal is delayed by 1H (1H is one line driving time) from the second clock signal, the fourth clock signal is delayed by 1H (1H is one line driving time) from the third clock signal, the fifth clock signal is delayed by 1H (1H is one line driving time) from the fourth clock signal, and the sixth clock signal is delayed by 1H (1H is one line driving time) from the fifth clock signal;
the fourth clock signal is inverted with respect to the first clock signal, the fifth clock signal is inverted with respect to the second clock signal, and the sixth clock signal is inverted with respect to the third clock signal.
Fig. 9 is a simulation timing diagram of the driving module according to the embodiment of the invention.
In fig. 9, the nine waveforms from top to bottom are: a waveform diagram of a signal at the beginning of operation, a waveform diagram of a signal after 2 ten thousand hours of operation, a waveform diagram of a signal after 4 ten thousand hours of operation, a waveform diagram of a signal after 6 ten thousand hours of operation, a waveform diagram of a signal after 8 ten thousand hours of operation, a waveform diagram of a signal after 10 ten thousand hours of operation, a waveform diagram of a signal after 15 ten thousand hours of operation, a waveform diagram of a signal after 20 ten thousand hours of operation, and a waveform diagram of a signal after 25 ten thousand hours of operation;
in actual operation, the effective display area of the display panel is divided into 9 parts, and each stage of driving circuits included in the driving module respectively provide driving signals for each row of gate lines in the effective display area;
the waveform diagram of the signals of each row is as follows from left to right: a waveform diagram of a driving signal on a first row of gate lines in a first section, a waveform diagram of a driving signal on a first row of gate lines in a second section, a waveform diagram of a driving signal on a first row of gate lines in a third section, a waveform diagram of a driving signal on a first row of gate lines in a fourth section, a waveform diagram of a driving signal on a first row of gate lines in a fifth section, a waveform diagram of a driving signal on a first row of gate lines in a sixth section, a waveform diagram of a driving signal on a first row of gate lines in a seventh section, a waveform diagram of a driving signal on a first row of gate lines in an eighth section, and a waveform diagram of a driving signal on a first row of gate lines in a ninth section;
from the waveform diagrams, it can be seen that, by using the driving module according to the embodiment of the present invention, the lifetime is increased by 8 times compared with the original 19T1C architecture, and the lifetime is as long as 25 ten thousand hours, after the drain of the M1 is replaced with the input clock signal terminal IN _ CLK, the attenuation caused by the characteristic drift of each transistor IN the driving circuit IN the driving module will not affect the equilibrium stability relationship of the cascade connection inside the driving module, although the driving capability is inevitably reduced to some extent, the overall lifetime will not be affected.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A drive circuit is characterized by comprising a drive signal output end, a first node control circuit, a first control circuit, a second node control circuit and a drive output circuit;
the first node control circuit is respectively electrically connected with an input end, an input clock signal end and a first node, and is used for controlling the input clock signal end to provide an input clock signal to the first node under the control of an input signal provided by the input end;
the first control circuit is electrically connected with the first node and used for controlling the potential of the first node;
the second node control circuit is electrically connected with a second node and used for controlling the potential of the second node;
the driving output circuit is electrically connected with the first node, the second node and the driving signal output end respectively, and is used for controlling the driving signal output end to output a driving signal under the control of the potential of the first node and the potential of the second node.
2. The drive circuit according to claim 1, wherein the first node control circuit includes a first transistor;
the control electrode of the first transistor is electrically connected with the input end, the first electrode of the first transistor is electrically connected with the input clock signal end, and the second electrode of the first transistor is electrically connected with the first node.
3. The drive circuit according to claim 1 or 2, further comprising a carry signal output terminal and a carry output circuit;
the carry output circuit is respectively electrically connected with the first node, the second node, the output clock signal end, the first voltage end and the carry signal output end, and is used for controlling the carry signal output end to be electrically connected with the output clock signal end under the control of the potential of the first node and controlling the carry signal output end to be communicated with the first voltage end under the control of the potential of the second node.
4. The driving circuit according to claim 1 or 2, wherein the driving output circuit is further electrically connected to an output clock signal terminal and a second voltage terminal, respectively, for controlling the driving signal output terminal to be electrically connected to the output clock signal terminal under the control of the potential of the first node and controlling the driving signal output terminal to be connected to the second voltage terminal under the control of the potential of the second node;
the first control circuit is further respectively electrically connected with a reset end, an initial voltage end, the second node, the driving signal output end and the first voltage end, and is used for controlling the first node to be communicated with the first voltage end under the control of a reset signal provided by the reset end, controlling the first node to be communicated with the first voltage end under the control of a second initial voltage signal provided by the initial voltage end, controlling the second node to be communicated with the first voltage end under the control of the potential of the second node, and controlling the potential of the first node according to the driving signal.
5. The drive circuit according to claim 1 or 2, wherein the second node includes a first second node and a second node;
the second node control circuit is further electrically connected with the first control voltage end, the second control voltage end, the first node and the first voltage end respectively, and is used for controlling the potential of the first second node under the control of the first control voltage provided by the first control voltage end and the potential of the first node, and controlling the potential of the second node under the control of the second control voltage provided by the second control voltage end and the potential of the first node.
6. A driver module comprising a plurality of stages of driver circuits as claimed in any one of claims 1 to 5.
7. The driver module of claim 6, wherein the driver circuit comprises a carry signal output; the first node circuit is electrically connected with a reset terminal; the driving module is electrically connected with 2A clock signal lines, wherein A is a positive integer;
the carry signal output end of the nth-stage driving circuit included by the driving module is electrically connected with the input end of the (N + A) th-stage driving circuit included by the driving module and is used for providing an input signal for the input end of the (N + A) th-stage driving circuit;
the carry signal output end of the Mth-level driving circuit included in the driving module is electrically connected with the reset end of the Mth-A-1-level driving circuit included in the driving module and used for providing a reset signal for the reset end of the Mth-A-1-level driving circuit;
the input end of the nth-stage driving circuit included in the driving module is electrically connected with a first starting voltage line;
n is a positive integer, M is an integer greater than A +1, and N is a positive integer less than or equal to N.
8. The driving module according to claim 7, wherein an input clock signal terminal of the nth stage driving circuit is electrically connected to the first start voltage line.
9. The driver module as claimed in claim 7, wherein the input clock signal terminal of the a + B stage driver circuit included in the driver module is electrically connected to a B-th clock signal line for providing the input clock signal to the input clock signal terminal of the a + B stage driver circuit included in the driver module;
b is a positive integer; when B cannot be divided by 2A, B is the remainder of B divided by 2A; when B is divisible by 2A, B equals 2A.
10. The driver module of claim 7, wherein the output clock signal terminal of the C-th stage driver circuit included in the driver module is electrically connected to a C-th clock signal line, and the C-th clock signal line provides the output clock signal terminal of the C-th stage driver circuit included in the driver module with the output clock signal;
c is a positive integer; when C cannot be divided by 2A, C is the remainder obtained by dividing C by 2A; when C is divisible by 2A, C equals 2A.
11. A display device comprising a driving module according to any one of claims 6 to 10.
12. The display device according to claim 11, wherein the display device comprises two of the driving modules; the display device further comprises a display panel; the display panel includes a plurality of rows of pixel circuits;
the first driving module is arranged on a first side edge of the display panel, and the second driving module is arranged on a second side edge of the display panel;
the first driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits;
and the second driving module is electrically connected with the plurality of rows of pixel circuits and used for providing corresponding driving signals for the pixel circuits.
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