CN109671385A - Drive element of the grid, grid drive method, gate driving circuit and display device - Google Patents
Drive element of the grid, grid drive method, gate driving circuit and display device Download PDFInfo
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- CN109671385A CN109671385A CN201910151341.1A CN201910151341A CN109671385A CN 109671385 A CN109671385 A CN 109671385A CN 201910151341 A CN201910151341 A CN 201910151341A CN 109671385 A CN109671385 A CN 109671385A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The present invention provides a kind of drive element of the grid, grid drive method, gate driving circuit and display device.The drive element of the grid includes pull-up node control circuit, pull-down node control circuit, carry signal output end and carry signal output circuit；The pull-up node control circuit is used under the control for the first clock signal that the first clock signal input terminal inputs, and is controlled and is connected between the pull-up node and input terminal；The pull-down node control circuit is used under the control of the current potential of AC controling signal and the pull-up node that AC controling signal end inputs, controls the current potential of pull-down node；Under control of the carry signal generative circuit for the current potential of the pull-up node and the current potential of the pull-down node, the carry signal output end output carry signal is controlled；The input terminal is connect with adjacent upper level carry signal output end.The present invention solves the problems, such as that existing drive element of the grid charges and put the scarce capacity made an uproar to pull-up node.
Description
Technical field
The present invention relates to display actuation techniques field more particularly to a kind of drive element of the grid, grid drive method, grids
Driving circuit and display device.
Background technique
In existing GOA (Gate On Array, the gate driving circuit being set in array substrate) model, use
Pull-up node control transistor be pull-up node charge, and the pull-up node control transistor grid and source electrode all with it is defeated
Enter end connection, the drain electrode of pull-up node control transistor is connect with pull-up node, and pull-up node control transistor equivalent is
Diode, when pull-up node control transistor deteriorates, the input signal of input terminal input passes through the pull-up node control
Starting current is less than normal when the diode that combinations body pipe is formed is inputted, and leads to the charging ability decline to pull-up node, simultaneously
In existing GOA model, it is pull-up node denoising by pull-down node, subtracts in pulling ability of the pull-up node to pull-down node
In the case where weak, the current potential of pull-down node can further be pulled down node and drag down, and the input signal to decay in this way is transmitted to next
It can be constantly amplified decaying when grade drive element of the grid, eventually leading to GOA can not start.
Also, in existing drive element of the grid, pull-down node control circuit is in DC control signal and pull-up node
Current potential control under, control the current potential of pull-down node, the current potential of pull-down node is by DC control, there are Dc bias risk,
So that the threshold voltage of the transistor of the grid access DC control signal in pull-down node control circuit generates biggish drift.
Existing drive element of the grid is used to cascade using gate drive signal, so that the driving capability of gate driving output end is weak.
Summary of the invention
The main purpose of the present invention is to provide a kind of drive element of the grid, grid drive method, gate driving circuit and
Display device solves existing drive element of the grid and pull-up node is charged and put the scarce capacity made an uproar, and pull-down node controls
The threshold voltage of the transistor of grid access DC control signal in circuit generates biggish drift, and existing gate driving
The weak problem of the driving capability of the gate drive signal output end of unit.
In order to achieve the above object, the present invention provides a kind of drive element of the grid, which is characterized in that including pull-up node
Control circuit, pull-down node control circuit, carry signal output end and carry signal output circuit；
The control for the first clock signal that the pull-up node control circuit is used to input in the first clock signal input terminal
Under, it controls and is connected between the pull-up node and input terminal；
The AC controling signal and the pull-up that the pull-down node control circuit is used to input at AC controling signal end
Under the control of the current potential of node, the current potential of pull-down node is controlled；
Control of the carry signal generative circuit for the current potential of the pull-up node and the current potential of the pull-down node
Under, control the carry signal output end output carry signal；
The input terminal is connect with adjacent upper level carry signal output end.
The pull-up node control circuit includes pull-up node control transistor；
The control electrode of the pull-up node control transistor is connect with first clock signal input terminal, the pull-up section
First pole of point control transistor is connect with the pull-up node, the pull-up node control the second pole of transistor with it is described defeated
Enter end connection.
When implementation, the AC controling signal end is second clock signal input part.
When implementation, the pull-down node control circuit includes the first pull-down node control transistor and the second pull-down node control
Transistor processed；
The control electrode and first pull-down node of the first pull-down node control transistor control the first of transistor
Pole is all connect with the second clock signal input part, the second pole of the first pull-down node control transistor and the drop-down
Node connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, second pull-down node
First pole of control transistor is connect with the pull-down node, the second pole and first of the second pull-down node control transistor
Level terminal connection.
When implementation, the AC controling signal end includes the first control voltage end and the second control voltage end；The drop-down
Node control circuit includes the first pull-down control circuit and the second pull-down control circuit；The pull-down node includes the first drop-down section
Point and the second pull-down node；
First pull-down control circuit is used for the first control voltage and the pull-up in the first control voltage end input
Under the control of the current potential of node, the current potential of first pull-down node is controlled；
Second pull-down control circuit is used for the second control voltage and the pull-up in the second control voltage end input
Under the control of the current potential of node, the current potential of second pull-down node is controlled.
When implementation, the first pull-down node control circuit includes the first pull-down node control transistor and the second drop-down section
Point control transistor, the second pull-down node control circuit include third pull-down node control transistor and the 4th pull-down node
Control transistor；
The control electrode and first pull-down node of the first pull-down node control transistor control the first of transistor
Pole is all connect with the first control voltage end, the second pole of the first pull-down node control transistor and first drop-down
Node connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, second pull-down node
First pole of control transistor connect with first pull-down node, second pull-down node control transistor the second pole and
The connection of second electrical level end；
The control electrode and the third pull-down node of the third pull-down node control transistor control the first of transistor
Pole is all connect with the second control voltage end, the second pole of the third pull-down node control transistor and second drop-down
Node connection；
The control electrode of the 4th pull-down node control transistor is connect with the pull-up node, the 4th pull-down node
First pole of control transistor connect with second pull-down node, second pull-down node control transistor the second pole and
The connection of second electrical level end.
When implementation, drive element of the grid of the present invention further includes pull-up node squelch circuit, blank area reset circuit
With pull-down node squelch circuit, wherein
The pull-up node squelch circuit is used under the control for the reset signal that reset terminal inputs, to the pull-up node
It is denoised；
The blank area reset circuit is used under the control for the blank area reset signal that blank area reset terminal inputs, to institute
The current potential for stating pull-up node is resetted；
The pull-down node squelch circuit is used under the control of input signal, is denoised to pull-down node.
When implementation, drive element of the grid of the present invention further includes gate drive signal output end, accumulator and grid
Pole driving signal output circuit；
The accumulator is connect with the pull-up node, for maintaining the current potential of the pull-up node；
The gate drive signal output circuit be used for the current potential of the pull-up node, the current potential of the pull-down node and
Under the control of the reset signal of reset terminal input, the gate drive signal output end output gate drive signal is controlled.
The present invention also provides a kind of grid drive methods, applied to above-mentioned gate driving circuit, the gate driving
Method includes:
In the input phase of display cycle, the pull-up node control circuit is under the control of the first clock signal, control
It is charged by input signal to pull-up node, to control the current potential of pull-up node as effective voltage；Pull-down node control electricity
Road controls pull-down node under the control of the AC controling signal that AC controling signal end inputs and the current potential of the pull-up node
Current potential be dead voltage；
In the reseting stage and output cut-off holding stage that the display cycle includes, pull-up node control circuit is in the first clock
Under the control of signal, control denoises pull-up node；
The output end the holding stage, the pull-down node control circuit the AC controling signal and it is described on
Under the control for drawing the current potential of node, the current potential for controlling pull-down node is effective voltage；
In the display cycle, current potential and the pull-down node of the carry signal generative circuit for the pull-up node
Under the control of current potential, the carry signal output end output carry signal is controlled.
The present invention also provides a kind of gate driving circuits, including multistage above-mentioned drive element of the grid
Other than first order drive element of the grid, the carry signal output end of every level-one drive element of the grid and it is adjacent on
The input terminal of level-one drive element of the grid connects；
Other than afterbody drive element of the grid, the carry signal output end of every level-one drive element of the grid with it is adjacent
The reset terminal of next stage drive element of the grid connects.
The present invention also provides a kind of display devices, including above-mentioned gate driving circuit.
Compared with prior art, drive element of the grid of the present invention, grid drive method, gate driving circuit and aobvious
Showing device by pull-up node control circuit in input phase, it is upward by input signal under the control of the first clock signal
It draws node to charge, in reseting stage and output cut-off holding stage, pull-up node is denoised by the first clock signal,
And to denoise pull-up node not by pull-down node, so that it is lossless to charge in input phase to pull-up node, both possessed
Stronger noise removal capability, and there is stronger input signal transmission capacity, so that it is (thin that TFT occurs after finishing reliability evaluation
Film transistor) deterioration when GOA (Gate On Array, the gate driving circuit being set in array substrate) still have it is ideal
Output；Also, in drive element of the grid of the present invention, grid drive method, gate driving circuit and display device, under
It draws node control circuit under the control of AC controling signal and the current potential of pull-up node, controls the current potential of pull-down node, pull down
The current potential of node is controlled by AC signal, reduces Dc bias risk, to improve the pull-down node in pull-down node control circuit
The threshold voltage shift of transistor is controlled, the present invention is controlled using carry signal output circuit and exported by carry signal output end
Carry signal, to be used to cascade, to promote the driving capability of gate driving output end.
Detailed description of the invention
Fig. 1 is the structure chart of drive element of the grid described in the embodiment of the present invention；
Fig. 2 is the structure chart of drive element of the grid described in another embodiment of the present invention；
Fig. 3 is the structure chart of drive element of the grid described in further embodiment of this invention；
Fig. 4 is the structure chart of drive element of the grid described in yet another embodiment of the invention；
Fig. 5 is the structure chart of drive element of the grid described in another embodiment of the present invention；
Fig. 6 is the structure chart of drive element of the grid described in further embodiment of this invention；
Fig. 7 is the structure chart of drive element of the grid described in yet another embodiment of the invention；
Fig. 8 is the structure chart of drive element of the grid described in another embodiment of the present invention；
Fig. 9 is the circuit diagram of the first specific embodiment of drive element of the grid of the present invention；
Figure 10 is the working timing figure of the first specific embodiment of drive element of the grid of the present invention；
Figure 11 is the circuit diagram of the third specific embodiment of drive element of the grid of the present invention；
Figure 12 is the working timing figure of the third specific embodiment of drive element of the grid of the present invention；
Figure 13 is the circuit diagram of the 4th specific embodiment of drive element of the grid of the present invention；
Figure 14 is the working timing figure of the 4th specific embodiment of drive element of the grid of the present invention；
Figure 15 is the circuit diagram of the 4th specific embodiment of drive element of the grid of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The transistor used in all embodiments of the invention all can be triode, thin film transistor (TFT) or field-effect tube or its
The identical device of his characteristic.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to control electrode, will wherein claim a pole
For the first pole, another pole is known as the second pole.
In practical operation, when the transistor is triode, the control electrode can be base stage, and first pole can
Think collector, second pole can be with emitter；Alternatively, the control electrode can be base stage, described first can be extremely hair
Emitter-base bandgap grading, second pole can be with collector.
In practical operation, when the transistor is thin film transistor (TFT) or field-effect tube, the control electrode can be grid
Pole, described first can be extremely drain electrode, and described second extremely can be source electrode；Alternatively, the control electrode can be grid, described the
One extremely can be source electrode, and described second can be extremely drain electrode.
As shown in Figure 1, drive element of the grid described in the embodiment of the present invention includes pull-up node control circuit 10, drop-down section
Point control circuit 11, carry signal output end Out_C and carry signal output circuit 12；
The pull-up node control circuit 10 respectively with the first clock signal input terminal, pull-up node PU and input terminal
Input connection, for controlling the pull-up under the control for the first clock signal clk that the first clock signal input terminal inputs
It is connected between node PU and input terminal Input；
The pull-down node control circuit 11 respectively with pull-up node PU, pull-down node PD and AC controling signal end ACS
Connection, under the control of the current potential of AC controling signal and the pull-up node PU that AC controling signal end ACS is inputted,
Control the current potential of the pull-down node PD；
The carry signal generative circuit 12 is defeated with the pull-up node PU, the pull-down node PD and carry signal respectively
Outlet Out_C connection, under the control of the current potential of the current potential and pull-down node PD for the pull-up node PU, described in control
Carry signal output end Out_C output carry signal；
The input terminal Input is connect with adjacent upper level carry signal output end.
In the specific implementation, the AC controling signal end can be clock signal terminal, alternatively, the AC controling signal
End also may include the first control voltage end and the second control voltage end, the first control electricity of the first control voltage end input
Pressure and the second control voltage of the second control voltage end input are AC signal；But not limited to this.
Present invention drive element of the grid as shown in Figure 1 at work, the display cycle include the input phase set gradually,
Output stage, reseting stage and output cut-off holding stage；
In input phase, under the control of the first clock signal clk B, the pull-up node control circuit 10 control PU with
The effective voltage of Input connection, Input input charges to pull-up node PU, to control the current potential of PU as effective voltage；Under
Draw node control circuit 11 in the current potential of the AC controling signal end ACS AC controling signal inputted and the pull-up node PU
Under control, the current potential of control pull-down node PD is dead voltage；
In output stage, the current potential of PU, which is booted, to be drawn high, so that the current potential of PU is maintained effective voltage；
In reseting stage and output cut-off holding stage, under the control of the first clock signal clk B, the pull-up node
Control circuit 10 controls PU and connect with Input, and Input inputs dead voltage, to control the current potential of PU as dead voltage；
End the holding stage in the output, the pull-down node control circuit 11 is in the AC controling signal and described
Under the control of the current potential of pull-up node PU, the current potential of control pull-down node PD is effective voltage；
In the display cycle, carry signal generative circuit 12 is for the current potential of the pull-up node PU and drop-down section
Under the control of the current potential of point PD, the carry signal output end Out_C output carry signal is controlled.
In the specific implementation, the effective voltage is the voltage that can be controlled grid and access its transistor turns, for example,
When the transistor is n-type transistor, the effective voltage can be high voltage；It is described when the transistor is p-type transistor
Effective voltage can be low-voltage；But not limited to this；
The dead voltage is the voltage that can be controlled grid and access its transistor turns, for example, when the transistor is n
When transistor npn npn, the dead voltage can be low-voltage；When the transistor is p-type transistor, the dead voltage can be with
For high voltage；But not limited to this.
Pull-up node control circuit 10 in drive element of the grid described in the embodiment of the present invention is in input phase, in CLKB
Control under, node PU is pulled up by input signal and is charged, in reseting stage and output cut-off holding stage, by the
One clock signal CLKB to denoise pull-up node PU, and to denoise pull-up node PU not by pull-down node, thus
Input phase is lossless to pull-up node PU charging, has not only possessed stronger noise removal capability, but also has the transmitting of stronger input signal
Ability, so that (Gate On Array, is set to GOA when TFT (thin film transistor (TFT)) deterioration occurs after finishing reliability evaluation
Gate driving circuit in array substrate) still there is ideal output；Also, in drive element of the grid of the present invention, grid
In pole driving method, gate driving circuit and display device, pull-down node control circuit 11 is in AC controling signal and pull-up section
Under the control of the current potential of point PU, the current potential of pull-down node PD is controlled, the current potential of pull-down node PD is controlled by AC signal, is reduced straight
Bias risk is flowed, to improve the threshold voltage shift of the control transistor of the pull-down node in pull-down node control circuit 11, this hair
Bright embodiment passes through carry signal output end Out_C output carry signal using the control of carry signal output circuit 12, to be used for
Cascade, to promote the driving capability of gate driving output end, and can be promoted cold-starting VGH Margin (high voltage can
Become range).
Drive element of the grid described in the embodiment of the present invention controls pull-down node PD's using pull-down node control circuit 11
Current potential, the pull-down node PD reset gate drive signal and carry signal for controlling.
It is poor that the embodiment of the present invention is suitable for TFT stability poor Oxide (oxide) TFT panel or homogeneity
LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon) TFT panel, is also applied for a-Si (amorphous silicon) TFT
Panel, but not limited to this.
The embodiment of the present invention is based on existing GOA model and proposes a kind of follow-on drive element of the grid, passes through change
The charging modes and denoising mode of pull-up node PU, realize that reliability more preferably GOA signal exports.
In drive element of the grid described in the embodiment of the present invention, pull-down node no longer drags down the current potential of pull-up node PU,
And to the denoising of pull-up node PU using (CLK is the second clock exported for gate drive signal with second clock signal CLK
Signal) CLKB of reverse phase realizes, the charging ability of pull-up node PU can be not only promoted in this way, but also can guarantee stronger to upper
Draw the ability of node PU denoising.
Specifically, the pull-up node control circuit may include pull-up node control transistor；
The control electrode of the pull-up node control transistor is connect with first clock signal input terminal, the pull-up section
First pole of point control transistor is connect with the pull-up node, the pull-up node control the second pole of transistor with it is described defeated
Enter end connection.
As shown in Fig. 2, on the basis of the embodiment of drive element of the grid shown in Fig. 1, the pull-up node control electricity
Road 10 may include pull-up node control transistor M1；
The grid of M1 accesses CLKB, and the drain electrode of M1 is connect with Input, and the source electrode of M1 is connect with PU.
In the embodiment shown in Figure 2, M1 is n-type thin film transistor, and but not limited to this.
In the specific implementation, Input can connect with the gate drive signal output end of adjacent upper level drive element of the grid
It connects, in the preferred case, can also be connect with the carry signal output end of adjacent upper level drive element of the grid.
According to a kind of specific embodiment, the AC controling signal end is second clock signal input part；The drop-down
Node control circuit is connect with pull-down node, second clock signal input part and the pull-up node respectively, for described the
Under the control of the current potential of the second clock signal and pull-up node of two clock signal input terminals input, the drop-down section is controlled
The current potential of point.
In embodiments of the present invention, the pull-down node control circuit controls pull-down node by second clock signal
System, the current potential of pull-down node are controlled by AC signal, reduce Dc bias risk, to improve the threshold of pull-down node control transistor
Threshold voltage drift.
As shown in figure 3, on the basis of the embodiment of drive element of the grid shown in Fig. 1, the AC controling signal end
For the second clock signal input part for inputting second clock signal CLK；
The pull-down node control circuit 11 is used for the control in the current potential of second clock signal CLK and the pull-up node PU
Under system, the current potential of the pull-down node PD is controlled.
At work, pull-down node control circuit 11 is in PU for the embodiment of present invention drive element of the grid as shown in Figure 3
Current potential and CLK control under, control the current potential of PD.
Specifically, the pull-down node control circuit may include the first pull-down node control transistor and the second drop-down section
Point control transistor；
The control electrode and first pull-down node of the first pull-down node control transistor control the first of transistor
Pole is all connect with the second clock signal input part, the second pole of the first pull-down node control transistor and the drop-down
Node connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, second pull-down node
First pole of control transistor is connect with the pull-down node, the second pole and first of the second pull-down node control transistor
Level terminal connection.
As shown in figure 4, on the basis of the embodiment of present invention drive element of the grid shown in Fig. 3, the pull-down node
Control circuit 11 may include the first pull-down node control transistor M5 and the second pull-down node control transistor M6；
The leakage of the grid and first pull-down node control transistor M5 of the first pull-down node control transistor M5
Second clock signal CLK is all accessed in pole, and the source electrode and the pull-down node PD of the first pull-down node control transistor M5 connects
It connects；
The grid of the second pull-down node control transistor M6 is connect with the pull-up node PU, the second drop-down section
The drain electrode of point control transistor M6 connect with the pull-down node PD, second pull-down node control transistor M6 source electrode and
The connection of first low level end；First low level end is for inputting the first low level VGL.
In the embodiment shown in fig. 4, the first level terminal is the first low level end, and but not limited to this.
In the embodiment shown in fig. 4, M5 and M6 is n-type thin film transistor, and but not limited to this.
At work, when CLK is high level, M5 is opened present invention embodiment as shown in Figure 4, to control PD access
CLK；When the current potential of PU is high level, M6 is opened, to control PD access VGL.
According to another specific embodiment, the AC controling signal end may include the first control voltage end and second
Control voltage end；The pull-down node control circuit may include the first pull-down control circuit and the second pull-down control circuit；Institute
Stating pull-down node includes the first pull-down node and the second pull-down node；
First pull-down control circuit is used for the first control voltage and the pull-up in the first control voltage end input
Under the control of the current potential of node, the current potential of first pull-down node is controlled；
Second pull-down control circuit is used for the second control voltage and the pull-up in the second control voltage end input
Under the control of the current potential of node, the current potential of second pull-down node is controlled.
In embodiments of the present invention, the first pull-down control circuit that the pull-down node control circuit includes is in the first control
Under the control of voltage and the current potential of pull-up node, the current potential of the first pull-down node is controlled, the pull-down node control circuit includes
The second pull-down control circuit second control voltage and pull-up node current potential control under, control the second pull-down node electricity
Position.
In the specific implementation, the display time may include that multiple voltages provide the period, and each voltage provides period packet
It includes the first voltage set gradually and stage and second voltage offer stage is provided；
The stage is provided in the first voltage, the first control voltage is effective voltage, and the second control voltage is
Dead voltage；
The stage is provided in the second voltage, the first control voltage is dead voltage, and the second control voltage is
Effective voltage.
In embodiments of the present invention, the first control voltage and the second control voltage are alternating voltage, the first control
Voltage processed, the second control voltage spaces are effective voltage, so that the grid access first that the first pull-down control circuit includes
The transistor interval for grid access the second control voltage that transistor, the second pull-down control circuit of control voltage include is opened,
The current potential of pull-down node is controlled by exchange, reduces Dc bias risk, so as to improve the threshold voltage shift of transistor as above.
Specifically, the first pull-down node control circuit may include under the first pull-down node control transistor and second
Node control transistor is drawn, the second pull-down node control circuit may include third pull-down node control transistor and the 4th
Pull-down node controls transistor；
The control electrode and first pull-down node of the first pull-down node control transistor control the first of transistor
Pole is all connect with the first control voltage end, the second pole of the first pull-down node control transistor and first drop-down
Node connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, second pull-down node
First pole of control transistor connect with first pull-down node, second pull-down node control transistor the second pole and
The connection of second electrical level end；
The control electrode and the third pull-down node of the third pull-down node control transistor control the first of transistor
Pole is all connect with the second control voltage end, the second pole of the third pull-down node control transistor and second drop-down
Node connection；
The control electrode of the 4th pull-down node control transistor is connect with the pull-up node, the 4th pull-down node
First pole of control transistor connect with second pull-down node, second pull-down node control transistor the second pole and
The connection of second electrical level end.
As shown in figure 5, on the basis of the embodiment of drive element of the grid shown in Fig. 1, the pull-down node control electricity
Road includes the first pull-down control circuit 111 and the second pull-down control circuit 112；The pull-down node includes the first pull-down node
PD1 and the second pull-down node PD2；
First pull-down control circuit 111 controls voltage end, the pull-up node PU and described first with first respectively
Pull-down node PD1 connection, for the first control voltage VDDo's and pull-up node PU in the first control voltage end input
Under the control of current potential, the current potential of the first pull-down node PD1 is controlled；
Second pull-down control circuit 112 controls voltage end, the pull-up node PU and described second with second respectively
Pull-down node PD2 connection, for the second control voltage VDDe's and pull-up node PU in the second control voltage end input
Under the control of current potential, the current potential of the second pull-down node PD2 is controlled；
The carry signal output circuit 11 respectively with the first pull-down node PD1, the second pull-down node PD2,
The pull-up node PU is connected with carry signal output end Out_C, for the current potential in the current potential of PD1, the current potential of PD2 and PU
Under control, Out_C output carry signal is controlled.
As shown in fig. 6, on the basis of the embodiment of drive element of the grid shown in Fig. 5, the first pull-down node control
Circuit 111 processed includes that the first pull-down node control transistor M5A and the second pull-down node control transistor M6A, under described second
Drawing node control circuit 112 includes that third pull-down node control transistor M5B and the 4th pull-down node control transistor M6B；
The grid of the first pull-down node control transistor M5A and first pull-down node control transistor M5A's
Drain electrode is all connect with the first control voltage end, the source electrode and described first of the first pull-down node control transistor M5A
Pull-down node PD1 connection；
The grid of the second pull-down node control transistor M6A is connect with the pull-up node PU, second drop-down
The drain electrode of node control transistor M6A is connect with the first pull-down node PD1, and second pull-down node controls transistor
The source electrode of M6A is connect with the second low level end；Second low level end is for inputting the second low level LVGL；
The grid of the third pull-down node control transistor M5B and the third pull-down node control transistor M5B's
Drain electrode is all connect with the second control voltage end, the source electrode and described second of the third pull-down node control transistor M5B
Pull-down node PD2 connection；
The grid of the 4th pull-down node control transistor M6B is connect with the pull-up node PU, the 4th drop-down
The drain electrode of node control transistor M6B is connect with the second pull-down node PD2, and second pull-down node controls transistor
The source electrode of M6B is connect with second low level end.
In the embodiment shown in fig. 6, the second electrical level end is the second low level end, and but not limited to this.
In the embodiment shown in fig. 6, M5A, M6A, M5B and M6B are n-type thin film transistor, and but not limited to this.
The embodiment of present invention drive element of the grid as shown in FIG. 6 at work,
The stage is provided in the first voltage, the first control voltage VDDo is high voltage, the second control voltage
VDDe is low-voltage, and M5A is opened, and M5B shutdown, PD1 accesses VDDo；
The stage is provided in the first voltage, the current potential of PD2 is low-voltage；
The stage is provided in the second voltage, the first control voltage VDDo is low-voltage, the second control voltage
VDDe is high voltage, M5A shutdown, M5B opening, PD2 access VDDe；
The stage is provided in the second voltage, the current potential of PD1 is low-voltage.
Specifically, drive element of the grid described in the embodiment of the present invention can also include pull-up node squelch circuit, blank
Area's reset circuit and pull-down node squelch circuit, wherein
The pull-up node squelch circuit is used under the control for the reset signal that reset terminal inputs, to the pull-up node
It is denoised；
The blank area reset circuit is used under the control for the blank area reset signal that blank area reset terminal inputs, to institute
The current potential for stating pull-up node is resetted；
The pull-down node squelch circuit is used under the control of input signal, is denoised to pull-down node.
As shown in fig. 7, on the basis of the embodiment of drive element of the grid shown in Fig. 1, described in the embodiment of the present invention
Drive element of the grid further includes pull-up node squelch circuit 13, blank area reset circuit 14 and pull-down node squelch circuit 15,
In
The pull-up node squelch circuit 13 is connect with reset terminal Reset and pull-up node PU respectively, in reset terminal
Under the control of the reset signal of Reset input, the pull-up node PU is denoised；
The blank area reset circuit 14 is connect with blank area reset terminal T_RST and the pull-up node PU respectively, is used for
Under the control of the blank area reset signal of blank area reset terminal T_RST input, the current potential of the pull-up node PU is answered
Position；
The pull-down node squelch circuit 15 is connect with input terminal Input and the pull-down node PD respectively, for defeated
Under the control for entering signal, pull-down node PD is denoised.
In the specific implementation, drive element of the grid described in the embodiment of the present invention may include pull-up node squelch circuit
13, blank area reset circuit 14 and pull-down node squelch circuit 15, in reseting stage, reset signal is effective voltage, it is described on
Node squelch circuit 13 is drawn to denoise pull-up node PU；Blank time section between two frame picture display times, it is described
Blank area reset signal T_RST is effective voltage, and blank area reset circuit 14 resets the current potential of pull-up node PU, to prevent
Only AD (Abnormal Display, abnormal show) generation is not extended to next frame picture display time；In input phase, input
Signal is effective voltage, and pull-down node squelch circuit 15 denoises pull-down node PD.
Specifically, drive element of the grid described in the embodiment of the present invention can also include gate drive signal output end, storage
It can circuit and gate drive signal output circuit；
The accumulator is connect with the pull-up node, for maintaining the current potential of the pull-up node；
The gate drive signal output circuit be used for the current potential of the pull-up node, the current potential of the pull-down node and
Under the control of the reset signal of reset terminal input, the gate drive signal output end output gate drive signal is controlled.
As shown in figure 8, on the basis of the embodiment of drive element of the grid shown in Fig. 1, described in the embodiment of the present invention
Drive element of the grid further includes gate drive signal output end Gout, accumulator 16 and gate drive signal output circuit 17；
The accumulator 16 is connect with the pull-up node PU, for maintaining the current potential of the pull-up node PU；
The gate drive signal output circuit 17 respectively with the pull-up node PU, the pull-down node PD, reset terminal
Reset is connected with the gate drive signal output end Gout, for the current potential in the pull-up node PU, the pull-down node
Under the control of the current potential of PD and the reset signal of reset terminal Reset input, the gate drive signal output end is controlled
Gout exports gate drive signal.
Illustrate drive element of the grid of the present invention below by four specific embodiments.
As shown in figure 9, the first specific embodiment of drive element of the grid of the present invention includes pull-up node control electricity
Road 10, pull-down node control circuit 11, gate drive signal output end Gout, accumulator 16 and gate drive signal output electricity
Road 17；
The pull-up node control circuit 10 includes that pull-up node controls transistor M1；
The grid of M1 accesses CLKB, and the drain electrode of M1 is connect with Input, and the source electrode of M1 is connect with PU.
The pull-down node control circuit 11 includes the first pull-down node control transistor M5 and the control of the second pull-down node
Transistor M6；
The leakage of the grid and first pull-down node control transistor M5 of the first pull-down node control transistor M5
Second clock signal CLK is all accessed in pole, and the source electrode and the pull-down node PD of the first pull-down node control transistor M5 connects
It connects；
The grid of the second pull-down node control transistor M6 is connect with the pull-up node PU, the second drop-down section
The drain electrode of point control transistor M6 connect with the pull-down node PD, second pull-down node control transistor M6 source electrode and
The connection of first low level end；First low level end is for inputting the first low level VGL；
The accumulator 16 includes storage capacitance Cst；
The first end of the storage capacitance Cst is connect with the pull-up node PU, the second end of the storage capacitance Cst with
The gate drive signal output end Gout connection；
The gate drive signal output circuit 17 includes first gate driving signal output transistor M3, second grid drive
Dynamic signal output transistor M13 and third gate drive signal output transistor M4；
The grid of M3 is connect with PU, and the drain electrode of M3 accesses CLK, and the source electrode of M3 is connect with Gout；
The grid of M13 is connect with PD, and the drain electrode of M13 is connect with Gout, and the source electrode of M13 accesses VGL；
The grid of M4 is connect with Reset, and the drain electrode of M4 is connect with Gout, and the source electrode of M13 accesses VGL.
First specific embodiment of present invention drive element of the grid as shown in Figure 9 can also include carry signal output electricity
Road (being not shown in Fig. 9) and carry signal output end (in Fig. 9) are not shown；The carry signal output circuit is used to save in pull-up
Under the current potential of point PU and the current potential of pull-down node PD, carry signal output end output carry signal is controlled, can be believed by carry
Number output end is cascaded.
In first specific embodiment of drive element of the grid shown in Fig. 9, all transistors are all n-type thin film crystal
Pipe, but not limited to this.
First specific embodiment of present invention drive element of the grid as shown in Figure 9 can promote filling for pull-up node PU
Electric energy power, and guarantee on the basis of having the stronger ability to pull-up node PU denoising, the number of the transistor of use is reduced, is subtracted
Small GOA frame, and PU is to exchange control with PD, and Dc bias risk reduces；
As shown in Figure 10, the first specific embodiment of present invention drive element of the grid as shown in Figure 9 at work, is shown
Period includes the input phase T1 set gradually, output stage T2, reseting stage T3 and output cut-off holding stage T4；
In input phase T1, Input input high level, CLK is low level, and CLKB is high level, and Reset inputs low electricity
Flat, M1 is opened, and is charged with the high level inputted by Input for Cst, so that the current potential of PU is high level, M3 is opened, and Gout is defeated
Low level out；
In output stage T2, Input input low level, CLK is high level, and CLKB is low level, and Reset inputs low electricity
Flat, the current potential of M1 shutdown, PU is drawn high by Cst bootstrapping, and M3 is opened, and Gout exports high level；
In reseting stage T3, Input input low level, CLK is low level, and CLKB is high level, the high electricity of Reset input
Flat, M1 is opened, so that PU is connect with Input, is denoised to PU, so that the current potential of PU is low level；M4 is opened, so that Gout
Export low level；
End holding stage T4, Input input low level in output, is divided into high level, low level, the interval CLKB between CLK
For low level, high level, Reset input low level, when CLKB is high level, M1 is opened, to denoise to PU；When CLK is height
When level, M5 is opened, and the current potential of PD is drawn high as high level.
As shown in figure 11, the second specific embodiment of drive element of the grid of the present invention includes pull-up node control electricity
Road 10, pull-down node control circuit 11, gate drive signal output end Gout, accumulator 16, gate drive signal output electricity
Road 17, carry signal output end Out_C, carry signal output circuit 12, pull-up node squelch circuit 13, blank area reset circuit
14 and pull-down node squelch circuit 15；
The pull-up node control circuit 10 includes that pull-up node controls transistor M1；
The grid of M1 accesses CLKB, and the drain electrode of M1 is connect with Input, and the source electrode of M1 is connect with PU.
The pull-down node control circuit 11 includes the first pull-down node control transistor M5 and the control of the second pull-down node
Transistor M6；
The leakage of the grid and first pull-down node control transistor M5 of the first pull-down node control transistor M5
Second clock signal CLK is all accessed in pole, and the source electrode and the pull-down node PD of the first pull-down node control transistor M5 connects
It connects；
The grid of the second pull-down node control transistor M6 is connect with the pull-up node PU, the second drop-down section
The drain electrode of point control transistor M6 connect with the pull-down node PD, second pull-down node control transistor M6 source electrode and
The connection of first low level end；First low level end is for inputting the first low level VGL；
The accumulator 16 includes storage capacitance Cst；
The first end of the storage capacitance Cst is connect with the pull-up node PU, the second end of the storage capacitance Cst with
The gate drive signal output end Gout connection；
The gate drive signal output circuit 17 includes first gate driving signal output transistor M3, second grid drive
Dynamic signal output transistor M13 and third gate drive signal output transistor M4；
The grid of M3 is connect with PU, and the drain electrode of M3 accesses CLK, and the source electrode of M3 is connect with Gout；
The grid of M13 is connect with PD, and the drain electrode of M13 is connect with Gout, and the source electrode of M13 accesses VGL；
The grid of M4 is connect with Reset, and the drain electrode of M4 is connect with Gout, and the source electrode of M13 accesses VGL；
The carry signal output circuit 12 includes the first carry signal output transistor M11, the output of the second carry signal
Transistor M12 and carry signal denoise transistor M120；
The grid of M11 is connect with PU, and the drain electrode of M11 accesses CLK, and the source electrode of M11 is connect with Out_C；
The grid of M12 is connect with PD, and the drain electrode of M12 is connect with Out_C, and the source electrode of M12 accesses the second low-voltage LVGL；
The grid of M120 is connect with Reset, and the drain electrode of M120 is connect with Out_C, and the source electrode of M120 accesses the second low-voltage
LVGL；
The pull-up node squelch circuit 13 includes that pull-up node drives transistor M2；
The grid of M2 is connect with reset terminal Reset, and the drain electrode of M2 is connect with PU, and the source electrode of M2 accesses LVGL；
The blank area reset circuit 14 includes blank area reset transistor M15；
M15 is connect with blank area reset terminal T_RST, and the drain electrode of M15 is connect with PU, and the source electrode of M15 accesses LVGL；
The pull-down node squelch circuit 15 includes that pull-down node denoises transistor M7；
The grid of M7 is connect with input terminal Input, and the drain electrode of M7 is connect with PD, and the source electrode of M7 accesses LVGL.
In second specific embodiment of the drive element of the grid shown in Figure 11, all transistors are all n-type thin film crystalline substance
Body pipe, but not limited to this；And Input is connect with the carry signal output end of adjacent upper level, Reset and adjacent next stage grid
The carry signal output end of pole driving unit connects.
As shown in figure 12, the second specific embodiment of present invention drive element of the grid as shown in figure 11 at work, is shown
Show that the period includes the input phase T1 set gradually, output stage T2, reseting stage T3 and output cut-off holding stage T4；
In input phase T1, Input input high level, CLK is low level, and CLKB is high level, and Reset inputs low electricity
Flat, M1 is opened, and is charged with the high level inputted by Input for Cst, so that the current potential of PU is high level, M3 and M11 are opened,
Gout and Out_C exports low level；M7 is opened, to control PD access LVGL；
In output stage T2, Input input low level, CLK is high level, and CLKB is low level, and Reset inputs low electricity
Flat, the current potential of M1 shutdown, PU is drawn high by Cst bootstrapping, and M3 and M11 are opened, and Gout and Out_C export high level；
In reseting stage T3, Input input low level, CLK is low level, and CLKB is high level, the high electricity of Reset input
Flat, M1 is opened, so that PU is connect with Input, is denoised to PU, so that the current potential of PU is low level；M2 is opened, and is connect with controlling PU
Enter LVGL；M4 is opened, so that Gout exports low level, M120 is opened, so that Out_C exports low level；
End holding stage T4, Input input low level in output, is divided into high level, low level, the interval CLKB between CLK
For low level, high level, Reset input low level, when CLKB is high level, M1 is opened, to denoise to PU；When CLK is height
When level, M5 is opened, and the current potential of PD is drawn high as high level, so that Gout and Out_C export low level.
In blank time section TB, T_RST input high level, M15 is opened, to control PU access LVGL.
In the present invention as shown in fig. 13 that the second specific embodiment of drive element of the grid, M1 is controlled by exchange, is not allowed
The deterioration in characteristics due to caused by Dc bias is easily formed, and the current potential of pull-up node PU passes through not by the control of pull-down node PD
The M1 of CLKB control denoises PU, is conducive to charge to PU, and PD is exchanged by CLK and controlled, while being drawn by Input and PU
It is low, it is ensured that normal output.
As shown in figure 13, the third specific embodiment of drive element of the grid of the present invention includes pull-up node control electricity
Road 10, pull-down node control circuit, carry signal output end Out_C, carry signal output circuit 12, pull-up node squelch circuit
13, blank area reset circuit 14, pull-down node squelch circuit 15, gate drive signal output end Gout, accumulator 16 and grid
Pole driving signal output circuit 17；
The pull-up node control circuit 10 includes that pull-up node controls transistor M1；
The grid of M1 accesses CLKB, and the drain electrode of M1 is connect with Input, and the source electrode of M1 is connect with PU；
The pull-down node control circuit includes the first pull-down control circuit 111 and the second pull-down control circuit 112；
The first pull-down node control circuit 111 includes the first pull-down node drop-down section of control transistor M5A and second
Point control transistor M6A, the second pull-down node control circuit 112 include third pull-down node control transistor M5B and the
Four pull-down nodes control transistor M6B；
The grid of the first pull-down node control transistor M5A and first pull-down node control transistor M5A's
Drain electrode is all connect with the first control voltage end, the source electrode of the first pull-down node control transistor M5A and the first drop-down
Node PD1 connection；
The grid of the second pull-down node control transistor M6A is connect with the pull-up node PU, second drop-down
The drain electrode of node control transistor M6A is connect with the first pull-down node PD1, and second pull-down node controls transistor
The source electrode of M6A is connect with the second low level end；Second low level end is for inputting the second low level LVGL；
The grid of the third pull-down node control transistor M5B and the third pull-down node control transistor M5B's
Drain electrode is all connect with the second control voltage end, the source electrode of the third pull-down node control transistor M5B and the second drop-down
Node PD2 connection；
The grid of the 4th pull-down node control transistor M6B is connect with the pull-up node PU, the 4th drop-down
The drain electrode of node control transistor M6B is connect with the second pull-down node PD2, and second pull-down node controls transistor
The source electrode of M6B is connect with second low level end；
The accumulator 16 includes storage capacitance Cst；
The first end of the storage capacitance Cst is connect with the pull-up node PU, the second end of the storage capacitance Cst with
The gate drive signal output end Gout connection；
The carry signal output circuit 12 includes the first carry signal output transistor M11, the output of the second carry signal
Transistor M12A and the second carry signal output transistor M12B；
The grid of M11 is connect with PU, and the drain electrode of M11 accesses CLK, and the source electrode of M11 is connect with Out_C；
The grid of M12A is connect with PD1, and the drain electrode of M12A is connect with Out_C, and the source electrode of M12A accesses the second low-voltage
LVGL；
The grid of M12B is connect with PD2, and the drain electrode of M12B is connect with Out_C, and the source electrode of M12B accesses the second low-voltage
LVGL；
The pull-up node squelch circuit 13 includes that pull-up node drives transistor M2；
The grid of M2 is connect with reset terminal Reset, and the drain electrode of M2 is connect with PU, and the source electrode of M2 accesses LVGL；
The blank area reset circuit 14 includes blank area reset transistor M15；
M15 is connect with blank area reset terminal T_RST, and the drain electrode of M15 is connect with PU, and the source electrode of M15 accesses LVGL；
The pull-down node squelch circuit 15 includes the first pull-down node denoising transistor M7A and the denoising of the second pull-down node
Transistor M7B；
The grid of M7A is connect with input terminal Input, and the drain electrode of M7A is connect with PD1, and the source electrode of M7A accesses LVGL；
The grid of M7B is connect with input terminal Input, and the drain electrode of M7B is connect with PD2, and the source electrode of M7B accesses LVGL；
The gate drive signal output circuit 17 includes first gate driving signal output transistor M3, second grid drive
Dynamic signal output transistor M13A, third gate drive signal output transistor M13B and the 4th gate drive signal export crystal
Pipe M4；
The grid of M3 is connect with PU, and the drain electrode of M3 accesses CLK, and the source electrode of M3 is connect with Gout；
The grid of M13A is connect with PD1, and the drain electrode of M13A is connect with Gout, and the source electrode of M13A accesses VGL；
The grid of M13B is connect with PD2, and the drain electrode of M13B is connect with Gout, and the source electrode of M13B accesses VGL；
The grid of M4 is connect with Reset, and the drain electrode of M4 is connect with Gout, and the source electrode of M13 accesses VGL.
In the third specific embodiment of the drive element of the grid shown in Figure 13, all transistors are all n-type thin film crystalline substance
Body pipe, but not limited to this；And Input is connect with the carry signal output end of adjacent upper level, Reset and adjacent next stage grid
The carry signal output end of pole driving unit connects.
As shown in figure 14, the present invention as shown in fig. 13 that drive element of the grid third specific embodiment at work, show
Show that the period includes the input phase T1 set gradually, output stage T2, reseting stage T3 and output cut-off holding stage T4；
Assuming that the display cycle was located in the first voltage offer stage, VDDo is high voltage, and VDDe is low-voltage, in blank
In period TB, VDDo is switched to low-voltage by high voltage, and VDDe is switched to high voltage, and the high electricity of T_RST input by low-voltage
Pressure；
In input phase T1, Input input high level, CLK is low level, and CLKB is high level, and Reset inputs low electricity
Flat, M1 is opened, and is charged with the high level inputted by Input for Cst, so that the current potential of PU is high level, M3 and M11 are opened,
Gout and Out_C exports low level；M7A and M7B is opened, and all accesses LVGL to control PD1 and PD2；
In output stage T2, Input input low level, CLK is high level, and CLKB is low level, and Reset inputs low electricity
Flat, the current potential of M1 shutdown, PU is drawn high by Cst bootstrapping, and M3 and M11 are opened, and Gout and Out_C export low level；
In reseting stage T3, Input input low level, CLK is low level, and CLKB is high level, the high electricity of Reset input
Flat, M1 is opened, so that PU is connect with Input, is denoised to PU, so that the current potential of PU is low level；M2 is opened, and is connect with controlling PU
Enter LVGL；M4 is opened, so that Gout exports low level；And since VDDo at this time is high level, the current potential of PU is low level, then
M5A is opened, and M6A shutdown draws high the current potential of PD1 for high level, and M12A is opened so that Gout and Out_C all export it is low
Level；
End holding stage T4, Input input low level in output, is divided into high level, low level, the interval CLKB between CLK
For low level, high level, Reset input low level, when CLKB is high level, M1 is opened, to denoise to PU；And due at this time
VDDo is high level, and the current potential of PU is low level, then M5A is opened, and M6A shutdown draws high the current potential of PD1 for high level；?
Under the control of PD1, M13A and M12A are opened, so that Gout and Out_C export low level；
In blank time section TB, T_RST input high level, M15 is opened, to control PU access LVGL.
The present invention as shown in fig. 13 that drive element of the grid third specific embodiment at work, the interval VDDo, VDDe
For high level, so that the interval M5A, M5B is opened, the current potential of pull-down node is controlled by exchange, reduces Dc bias risk, from
And improve the threshold voltage shift of transistor as above.
As shown in figure 15, on the basis of the third specific embodiment of drive element of the grid as shown in fig. 13 that of the invention,
Pull-up node control circuit 10 in 4th specific embodiment of drive element of the grid of the present invention further includes pull-up control
Transistor M16；
The drain electrode of the grid and M16 of M16 is all connect with input terminal Input, and the source electrode of M16 is connect with pull-up node PU；
In Figure 15, M16 is n-type thin film transistor, and but not limited to this.
4th specific embodiment of present invention drive element of the grid as shown in figure 15 is using M1 and M16 together in input rank
Section charges to pull-up node PU.
Grid drive method described in the embodiment of the present invention is applied to above-mentioned gate driving circuit, the gate driving side
Method includes:
In the input phase of display cycle, the pull-up node control circuit is under the control of the first clock signal, control
It is charged by input signal to pull-up node, to control the current potential of pull-up node as effective voltage；Pull-down node control electricity
Road controls pull-down node under the control of the AC controling signal that AC controling signal end inputs and the current potential of the pull-up node
Current potential be dead voltage；
In the reseting stage and output cut-off holding stage that the display cycle includes, pull-up node control circuit is in the first clock
Under the control of signal, control denoises pull-up node；
The output end the holding stage, the pull-down node control circuit the AC controling signal and it is described on
Under the control for drawing the current potential of node, the current potential for controlling pull-down node is effective voltage；
In the display cycle, current potential and the pull-down node of the carry signal generative circuit for the pull-up node
Under the control of current potential, the carry signal output end output carry signal is controlled.
In grid drive method described in the embodiment of the present invention, pull-up node control circuit is in input phase, first
Under the control of clock signal, node is pulled up by input signal and is charged, ends the holding stage in reseting stage and output,
Pull-up node is denoised by the first clock signal, and to denoise pull-up node not by pull-down node, thus defeated
Entering the stage charges to pull-up node lossless, has not only possessed stronger noise removal capability, but also have stronger input signal transmission capacity,
So that (Gate On Array, is set to array base to GOA when TFT (thin film transistor (TFT)) deterioration occurs after finishing reliability evaluation
Gate driving circuit on plate) still there is ideal output.
In grid drive method described in the embodiment of the present invention, pull-down node control circuit is in AC controling signal and upper
Under the control for drawing the current potential of node, the current potential of pull-down node is controlled, the current potential of pull-down node is controlled by AC signal, reduces direct current
Bias risk, to improve the threshold voltage shift of the control transistor of the pull-down node in pull-down node control circuit.
Gate driving circuit described in the embodiment of the present invention includes multistage above-mentioned drive element of the grid；
Other than first order drive element of the grid, the carry signal output end of every level-one drive element of the grid and it is adjacent on
The input terminal of level-one drive element of the grid connects；
Other than afterbody drive element of the grid, the carry signal output end of every level-one drive element of the grid with it is adjacent
The reset terminal of next stage drive element of the grid connects.
Display device described in the embodiment of the present invention includes above-mentioned gate driving circuit.
Display device provided by the embodiment of the present invention can be mobile phone, tablet computer, television set, display, notebook
Any products or components having a display function such as computer, Digital Frame, navigator.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (11)
1. a kind of drive element of the grid, which is characterized in that including pull-up node control circuit, pull-down node control circuit, carry
Signal output end and carry signal output circuit；
The pull-up node control circuit is used under the control for the first clock signal that the first clock signal input terminal inputs, control
It makes and is connected between the pull-up node and input terminal；
The AC controling signal and the pull-up node that the pull-down node control circuit is used to input at AC controling signal end
Current potential control under, control the current potential of pull-down node；
Under control of the carry signal generative circuit for the current potential of the pull-up node and the current potential of the pull-down node, control
Make the carry signal output end output carry signal；
The input terminal is connect with adjacent upper level carry signal output end.
2. drive element of the grid as described in claim 1, which is characterized in that the pull-up node control circuit includes pull-up section
Point control transistor；
The control electrode of the pull-up node control transistor is connect with first clock signal input terminal, the pull-up node control
First pole of transistor processed is connect with the pull-up node, the second pole of the pull-up node control transistor and the input terminal
Connection.
3. drive element of the grid as described in claim 1, which is characterized in that the AC controling signal end is second clock letter
Number input terminal.
4. drive element of the grid as claimed in claim 3, which is characterized in that the pull-down node control circuit include first under
Node control transistor and the second pull-down node is drawn to control transistor；
The control electrode and first pull-down node of the first pull-down node control transistor control the first pole of transistor all
It is connect with the second clock signal input part, the second pole of the first pull-down node control transistor and the pull-down node
Connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, the second pull-down node control
First pole of transistor is connect with the pull-down node, the second pole of the second pull-down node control transistor and the first level
End connection.
5. drive element of the grid as described in claim 1, which is characterized in that the AC controling signal end includes the first control
Voltage end and the second control voltage end；The pull-down node control circuit includes the first pull-down control circuit and the second drop-down control
Circuit；The pull-down node includes the first pull-down node and the second pull-down node；
First pull-down control circuit is used for the first control voltage and the pull-up node in the first control voltage end input
Current potential control under, control the current potential of first pull-down node；
Second pull-down control circuit is used for the second control voltage and the pull-up node in the second control voltage end input
Current potential control under, control the current potential of second pull-down node.
6. drive element of the grid as claimed in claim 5, which is characterized in that the first pull-down node control circuit includes the
One drop-down node control transistor and the second pull-down node control transistor, and the second pull-down node control circuit includes third
Pull-down node controls transistor and the 4th pull-down node controls transistor；
The control electrode and first pull-down node of the first pull-down node control transistor control the first pole of transistor all
It is connect with the first control voltage end, the second pole of the first pull-down node control transistor and first pull-down node
Connection；
The control electrode of the second pull-down node control transistor is connect with the pull-up node, the second pull-down node control
First pole of transistor is connect with first pull-down node, the second pole and second of the second pull-down node control transistor
Level terminal connection；
The control electrode and the third pull-down node of the third pull-down node control transistor control the first pole of transistor all
It is connect with the second control voltage end, the second pole of the third pull-down node control transistor and second pull-down node
Connection；
The control electrode of the 4th pull-down node control transistor is connect with the pull-up node, the 4th pull-down node control
First pole of transistor is connect with second pull-down node, the second pole and second of the second pull-down node control transistor
Level terminal connection.
7. the drive element of the grid as described in any claim in claim 1 to 6, which is characterized in that further include pull-up section
Point squelch circuit, blank area reset circuit and pull-down node squelch circuit, wherein
The pull-up node squelch circuit is used under the control for the reset signal that reset terminal inputs, and is carried out to the pull-up node
Denoising；
The blank area reset circuit is used under the control for the blank area reset signal that blank area reset terminal inputs, on described
The current potential of node is drawn to be resetted；
The pull-down node squelch circuit is used under the control of input signal, is denoised to pull-down node.
8. the drive element of the grid as described in any claim in claim 1 to 6, which is characterized in that further include that grid drives
Dynamic signal output end, accumulator and gate drive signal output circuit；
The accumulator is connect with the pull-up node, for maintaining the current potential of the pull-up node；
The gate drive signal output circuit is used in the current potential of the pull-up node, the current potential of the pull-down node and reset
Under the control for holding the reset signal of input, the gate drive signal output end output gate drive signal is controlled.
9. a kind of grid drive method, which is characterized in that applied to the grid as described in any claim in claim 1 to 8
Pole driving circuit, the grid drive method include:
In the input phase of display cycle, under the control of the first clock signal, control passes through the pull-up node control circuit
Input signal charges to pull-up node, to control the current potential of pull-up node as effective voltage；Pull-down node control circuit exists
Under the control of the current potential of the AC controling signal and pull-up node of AC controling signal end input, the electricity of pull-down node is controlled
Position is dead voltage；
In the reseting stage and output cut-off holding stage that the display cycle includes, pull-up node control circuit is in the first clock signal
Control under, control pull-up node is denoised；
End the holding stage in the output, the pull-down node control circuit is saved in the AC controling signal and the pull-up
Under the control of the current potential of point, the current potential for controlling pull-down node is effective voltage；
In the display cycle, carry signal generative circuit is for the current potential of the pull-up node and the current potential of the pull-down node
Control under, control the carry signal output end output carry signal.
10. a kind of gate driving circuit, which is characterized in that including multistage as described in any claim in claim 1 to 8
Drive element of the grid
Other than first order drive element of the grid, the carry signal output end of every level-one drive element of the grid and adjacent upper level
The input terminal of drive element of the grid connects；
Other than afterbody drive element of the grid, the carry signal output end of every level-one drive element of the grid with it is adjacent next
The reset terminal connection of grade drive element of the grid.
11. a kind of display device, which is characterized in that including gate driving circuit as claimed in claim 10.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910151341.1A CN109671385B (en) | 2019-02-28 | 2019-02-28 | Gate driving unit, gate driving method, gate driving circuit and display device |
| PCT/CN2020/074587 WO2020173293A1 (en) | 2019-02-28 | 2020-02-10 | Gate drive component, gate drive method, gate drive circuit, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910151341.1A CN109671385B (en) | 2019-02-28 | 2019-02-28 | Gate driving unit, gate driving method, gate driving circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109671385A true CN109671385A (en) | 2019-04-23 |
| CN109671385B CN109671385B (en) | 2020-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910151341.1A Active CN109671385B (en) | 2019-02-28 | 2019-02-28 | Gate driving unit, gate driving method, gate driving circuit and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109671385B (en) |
| WO (1) | WO2020173293A1 (en) |
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| WO2020173293A1 (en) * | 2019-02-28 | 2020-09-03 | 京东方科技集团股份有限公司 | Gate drive component, gate drive method, gate drive circuit, and display device |
| CN112562566A (en) * | 2020-12-10 | 2021-03-26 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method and display device |
| CN112927645A (en) * | 2021-03-26 | 2021-06-08 | 京东方科技集团股份有限公司 | Driving circuit, driving method and display device |
| CN113990233A (en) * | 2021-10-21 | 2022-01-28 | 福州京东方光电科技有限公司 | Drive circuit, drive module and display device |
| CN114495783A (en) * | 2020-10-27 | 2022-05-13 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit, gate driving method and display device |
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Also Published As
| Publication number | Publication date |
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| WO2020173293A1 (en) | 2020-09-03 |
| CN109671385B (en) | 2020-12-22 |
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