CN113987991B

CN113987991B - Signal transmission device and electronic equipment

Info

Publication number: CN113987991B
Application number: CN202111156065.1A
Authority: CN
Inventors: 毛洪艳; 林杰
Original assignee: Spreadtrum Semiconductor Nanjing Co Ltd
Current assignee: Spreadtrum Semiconductor Nanjing Co Ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2022-09-27
Anticipated expiration: 2041-09-29
Also published as: CN113987991A

Abstract

The embodiment of the application provides a signal transmission device and electronic equipment. The signal transmission device comprises a plurality of pins; the plurality of pins include a ground pin and a pin for transmitting a signal; the pins for transmitting signals comprise a first pin group and a second pin group; the first pin group is distributed in an M x N area, and the M x N area comprises at least one and at most M or N grounding pins; the second pin group is distributed in an area of S x T, and the area of S x T comprises at least one and at most S or T grounding pins; the first pin group is used for transmitting data signals; the second pin group is used for transmitting address signals. By some embodiments of the present application, the total number of pins for transmitting signals and the number of ground pins in the signal transmission device is reduced, thereby occupying less package area of the signal transmission device.

Description

Signal transmission device and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to a signal transmission device and electronic equipment.

Background

A chip is a general term for semiconductor device products. Different chips have different functions, and the normal operation of the electronic equipment needs the communication between the chips with different functions to be ensured.

Double data rate SDRAM (DDR) is a memory space that can be addressed directly. A chip that needs to communicate with the DDR is referred to as a first chip, and the first chip is connected to the DDR through a Printed Circuit Board (PCB), thereby implementing storage or reading of data.

How to realize the connection of the first chip and the DDR with less chip packaging area is the direction of continuous efforts of researchers in the field.

Disclosure of Invention

According to the embodiments of the present application, the total number of the pins for transmitting signals and the number of the ground pins in the signal transmission device is reduced, so that the signal transmission device occupies a smaller packaging area.

In a first aspect, an embodiment of the present application provides a signal transmission apparatus, including:

a plurality of pins;

the plurality of pins include a ground pin and a pin for transmitting a signal; the pins for transmitting signals comprise a first pin group and a second pin group;

the first pin group is distributed in an M x N area; the region of M x N comprises at least one, at most M or N grounding pins; the M and the N are integers greater than or equal to 2;

the second pin group is distributed in the region of S x T; the region of S x T comprises at least one, at most S or T grounding pins; s and T are integers greater than or equal to 2;

the first pin group is used for transmitting data signals; the second pin group is used for transmitting address signals.

In the embodiment of the present application, the arrangement of the pins in the signal transmission device may be understood as an arrangement of signal pins related to a (system on chip, SOC) and an external storage control interface.

In the signal transmission device provided in the embodiment of the present application, the first pin group is configured to transmit a data signal, and the second pin group is configured to transmit an address signal, where the number of ground pins in an M × N region distributed in the first pin group is at least one, and at most M or at most N; the number of the grounding pins in the S x T area distributed by the second pin group is at least one, at most S or at most T, and the number of the grounding pins is reduced while the signal quality is ensured by adjusting the arrangement mode of the signal transmission pins, so that the packaging area of the signal transmission device is reduced.

In a possible implementation manner, the first pin group is further configured to transmit a first clock signal, and pins for transmitting the first clock signal are adjacent to each other at an oblique angle; the first clock signal is used for synchronization of the data signal;

the second pin group is also used for transmitting a second clock signal, and pins for transmitting the second clock signal are adjacent in an oblique angle; the second clock signal is used for synchronization of the address signal.

It can be understood that the clock signal of the DDR is a differential clock signal, and the pins for transmitting the clock signal are arranged adjacently at an oblique angle, which may be beneficial to the PCB outgoing line and the coupling of the clock signal.

In a possible implementation manner, the pins outside the M × N region and adjacent to the pins in the M × N region at an oblique angle are the ground pins; and the pins outside the area of S and T and adjacent to the pins in the area of S and T in an oblique angle are the grounding pins.

In the embodiment of the application, the pins adjacent to the region of M × N and the region of S × T and the pins in the region of M × N and the region of S × T in an oblique angle are set as the grounding pins, so that the signal quality can be improved.

In a possible implementation manner, the number of pins in the first pin group is equal to 11, the M is equal to 5, and the N is equal to 5; the number of pins in the second pin group is equal to 11, S is equal to 5, and T is equal to 5.

In the above case, the M × N region and the S × T region include 11 pins for transmitting signals and 1 ground pin, respectively, and the ground pins may be provided in any of the M × N region and the S × T region. It is understood that the transmission quality of the signal can be ensured by the ground pins inside and outside the region of M × N and the region of S × T, and the total number of the pins and the ground pins for transmitting the signal is reduced, thereby reducing the occupied package area of the signal transmission device.

In a possible implementation manner, in the region of M × N, the number of pins corresponding to M being equal to 1 is equal to 2; one pin positioned on the first symmetrical center line of the M x N area is the grounding pin;

in the region of S x T, the number of the pins corresponding to the S equal to 1 is equal to 2; one pin located on the symmetrical center line of the region of S x T is the grounding pin.

Through the mode, one pin on the first symmetrical center line of the M x N area and one pin on the second symmetrical center line of the S x T area are set as the grounding pins, and compared with the mode that the grounding pins are arranged on the places except the symmetrical center lines, the grounding isolation degree among transmission signals can be improved, and the signal quality is improved.

In a possible implementation manner, in the region of M × N, the pin corresponding to M equal to 1 and N equal to 2 and the pin corresponding to M equal to 2 and N equal to 1 are used for transmitting the first clock signal; one pin which is positioned on the symmetrical center line of the M x N area and N is equal to 3 is the grounding pin; the first symmetrical center line comprises a symmetrical center line which is symmetrical up and down or a symmetrical center line which is symmetrical left and right;

in the region of S × T, the pin corresponding to S equal to 1 and T equal to 2 and the pin corresponding to S equal to 2 and T equal to 1 are used for transmitting the second clock signal; one pin which is positioned on a second symmetrical center line of the S x T area and the T is equal to 3 is the grounding pin; the second symmetrical center line includes a symmetrical center line which is symmetrical up and down or a symmetrical center line which is symmetrical left and right.

In this way, each of the 11 pins for transmitting signals can be made adjacent to the ground pin, thereby improving signal quality. In addition, the clock signal is arranged at the upper left corner of the M x N area and the S x T area, so that the DDR can be better adapted to external connection, the connecting line of the signal transmission device and the DDR is not crossed, and the normal transmission of the signal is ensured.

In a possible implementation manner, in the region of M × N, the pin corresponding to M being equal to 4 and N being equal to 3 is the ground pin; in the region of S × T, the pin corresponding to S equal to 4 and T equal to 3 is the ground pin.

Through the mode, on one hand, the quality of the signals transmitted by the signal transmission device can be ensured, namely, each signal can be separated by the grounding signal, and the signal transmission device has good ground isolation; the total number of pins for transmitting signals and the total number of ground pins can be reduced, so that the packaging area is reduced.

On the other hand, the grounding pins in the M × N region and the S × T region can be used as reference grounding signals of the whole group of signals, and the signal quality is further improved.

Finally, the order and the number of layers of the PCB can be reduced through the mode, namely, the signal wiring can be realized through the 2-order PCB and the 2-layer wiring layer, and the PCB development cost is saved.

In a possible implementation manner, the first pin group is further configured to transmit a first control signal, where the first control signal is used to control the data signal;

the second pin group is also used for transmitting a first chip selection signal and a first clock enable signal.

In a possible implementation manner, in a case that the number of bits of the data signal is greater than 8, the apparatus further includes a third pin group, the third pin group being distributed in an X Y region, the X Y region including at least one, at most the X, or the Y ground pins; the X and the Y are integers greater than or equal to 2;

the first pin group is used for transmitting high 8-bit signals in the data signals, and the third data signal group is used for transmitting low 8-bit signals in the data signals; or, the first pin group is used for transmitting a low 8-bit signal in the data signal, and the third pin group is used for transmitting a high 8-bit signal in the data signal.

In a second aspect, an embodiment of the present application provides an electronic device, which includes the signal transmission apparatus in the first aspect or any one of the possible implementation manners of the first aspect.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present application, the drawings used in the embodiments or the background art of the present application will be briefly described below.

Fig. 1 is a schematic diagram of a communication system provided in an embodiment of the present application;

fig. 2 is a schematic diagram of a pin in an orthogonal arrangement according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a pin in an oblique arrangement according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating signal types of a DDR provided in the embodiment of the present application;

fig. 5 is a schematic layout diagram of a pin for transmitting DDR signals according to an embodiment of the present application;

fig. 6 is a schematic diagram of a signal transmission apparatus according to an embodiment of the present application;

fig. 7 is a schematic diagram of another signal transmission apparatus provided in the embodiment of the present application;

fig. 8 is a schematic diagram of another signal transmission apparatus provided in the embodiment of the present application;

fig. 9 is a schematic diagram of an arrangement of 5 rows and 5 columns of pins according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a signal transmission device with a ground pin disposed on a symmetrical center line according to an embodiment of the present application;

fig. 11 is a schematic diagram of another signal transmission device provided in an embodiment of the present application, in which a ground pin is disposed on a symmetric center line;

fig. 12 is a schematic diagram of another signal transmission apparatus provided in the embodiment of the present application;

fig. 13 is a schematic pin layout diagram of a signal transmission apparatus for transmitting a 16-bit DDR signal according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a pin arrangement for transmitting 16-bit DDR signals according to an embodiment of the present disclosure;

fig. 15 is a schematic diagram of a wiring manner of a first wiring layer according to an embodiment of the present application;

fig. 16 is a schematic diagram of a wiring manner of the second wiring layer according to an embodiment of the present application.

Detailed Description

The terminology used in the following embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items.

In order to more clearly describe the aspects of the present application, some terms related to the embodiments of the present application will be described below.

(1) Chip and method for manufacturing the same

An Integrated Circuit (IC) may be understood as a kind of micro electronic device or component. Illustratively, the components and wiring required for transistors, resistors, capacitors and inductors of a circuit are interconnected together by certain processes, fabricated on one or more small semiconductor wafers or dielectric substrates, and then packaged in a package to form a microstructure having the required circuit functions, which may be understood as an integrated circuit.

A chip may be understood as a product formed by different types of integrated circuits or a single type of integrated circuit. It will be appreciated that different chips have different functions.

For example, a Central Processing Unit (CPU) may be understood as a chip for interpreting computer instructions and processing data in computer software.

A baseband chip may be understood as a chip for synthesizing a baseband signal or decoding a received baseband signal. Specifically, when the electronic device needs to transmit a signal, the baseband chip encodes a voice signal or other data signals, such as source coding and channel coding; and the electronic equipment correspondingly decodes the baseband code when receiving the baseband code.

A double data rate SDRAM (DDR) may be understood as a chip for storing data. In particular, DDR is a memory space that can be addressed directly by the CPU, and can transfer data once in each of the rising and falling clock periods, and the data can be stored and read at a fast rate.

It will be appreciated that the functionality and variety of chips is numerous and will not be enumerated here.

(2) Packaging and pin arrangement for chips

It can be understood that, for convenience of placement, circuit protection, and enhanced electrical heating performance, the integrated circuit needs to be packaged to obtain a corresponding chip. After packaging, the contacts on the chip are wired to pins on the package housing, which in turn are connected to other devices via wires on a Printed Circuit Board (PCB), thereby enabling communication between the chip and the other devices.

Referring to fig. 1, fig. 1 is a schematic diagram of a communication system according to an embodiment of the present disclosure.

As shown in fig. 1, the portion 100 may be understood as a circuit board, such as a PCB, for supporting the connection of the first device 101 and the second device 102. The first device 101 may be understood as a chip, such as a CPU, a baseband chip, and a DDR. The second device 102 may also be understood as a chip, such as a CPU, a baseband chip, and a DDR, etc. It is understood that the first device 101 and the second device 102 may be the same type of chip or different types of chips.

The 103 part may be understood as a communication line between the first device 101 and the second device 102 for communication between the first device 101 and the second device 102. It is understood that the communication line 103 may include a plurality of lines, i.e., the first device 101 and the second device 102 communicate through a plurality of wires, and exemplarily, the communication line 103 may include a plurality of power lines, a plurality of clock lines, a plurality of data lines, a plurality of control lines, and the like. In some embodiments, the first device 101 may be directly connected to the second device 102 through the communication line 103, or may be connected to other components before being connected to the second device 102.

It is understood that there are many types of chip packaging, and the packaging of chips is different, and the shape and distribution of pins are also different. For example, the chip may be a Dual Inline Package (DIP), a plastic square flat package (PQFP), a Thin Small Outline Package (TSOP), a Ball Grid Array (BGA), or the like. Thus, for example, the first device 101 or the second device 102 may be connected to the circuit board 100 by soldering or may be mounted on the circuit board 100 by a socket.

The product using BGA packaging technology has only one third of the volume of TSOP package at the same capacity. In addition, the BGA package method has a faster and more efficient heat dissipation path than the conventional TSOP package method. Input/output (I/O) terminals of a BGA package are distributed in an array of circular or columnar solder joints beneath the package. It will be appreciated that the pins of a chip using a BGA package may be arranged differently.

For example, please refer to fig. 2, fig. 2 is a schematic diagram illustrating a pin in an orthogonal arrangement according to an embodiment of the present disclosure.

Fig. 2 can be understood as a top view of the chip 20, and the chip 20 includes 7 rows and 7 columns, for example, with 49 pins. The distance between the adjacent pins in each row of pins is equal, and the distance between the adjacent pins in each column of pins is equal; the distance between adjacent rows is the same as the distance between adjacent columns; an included angle between a connecting line formed by the pins in any row and a connecting line formed by the pins in any column is 90 degrees. As shown in fig. 2, the connection line formed by the pin in the 4 th row and the connection line formed by the pin in the 5 th column form an angle of 90 degrees, that is, the two are perpendicular.

For example, please refer to fig. 3, fig. 3 is a schematic diagram illustrating a pin in a skew arrangement according to an embodiment of the present disclosure.

Fig. 3 can be understood as a top view of the chip 30, and the chip 30 includes 11 rows and 11 columns for 60 pins. The distance between the adjacent pins in each row of pins is equal, and the distance between the adjacent pins in each column of pins is equal; the distance between adjacent rows is the same as the distance between adjacent columns.

Assuming that the lead pin corresponding to the 8 th row and the 7 th column in fig. 3 is the first lead pin, the lead pin of the row where the first lead pin is located forms the first connection line, such as the straight line 301 in fig. 3.

The second pin is a pin closest to the first pin in a row of pins adjacent to the row where the first pin is located, specifically, the second pin may be a pin corresponding to the 8 th row in the 7 th row in fig. 3, or a pin corresponding to the 6 th row in the 7 th row, or a pin corresponding to the 8 th row in the 9 th row, or a pin corresponding to the 6 th row in the 9 th row, and for convenience of understanding, the pin corresponding to the 6 th row in the 7 th row is used as the second pin.

The first lead and the second lead form a second connection line, such as line 302 in fig. 3. The angle between the first line and the second line is 45 degrees, as shown in fig. 3, the straight line 301 and the straight line 302 are oblique, and the angle between the two lines is 45 degrees.

With the rapid development of semiconductor technology, the integration level of the system is improved, the chip size is smaller and smaller, the functions are more and more powerful, and the product is lighter and thinner. The number of signals within the chip is increasing. With the increase of the running speed of the chip, the DDR speed is increased, and the requirement on the DDR signal quality is higher. Therefore, higher requirements are put on the arrangement of the DDR signal pins in the chip.

With the rapid development of semiconductor technology, the number of signals in a chip is more and more, the running speed of the chip is faster and faster, and the functions are more and more powerful. For example, DDR5 has higher performance and lower power consumption than previous versions of DDR (e.g., DDR3, DDR4, etc.).

For example, please refer to fig. 4, fig. 4 is a schematic diagram illustrating signal types of a DDR according to an embodiment of the present disclosure.

As shown in fig. 4, the DDR may include 33 signals (which may be understood as DDR signals), each of which may correspond to one pin. Wherein:

the clock input (clock input) signals are denoted by CK _ T and CK _ C. For DDR, the clock signal is a clock differential signal, all address, control signals, and the like are sampled at the intersection of the rising edge (CK _ T) and the falling edge (CK _ C) of the clock cycle, and thus, CK _ T and CK _ C need to be coupled to each other as the clock signal input of DDR to be effective.

The clock enable (CKE) signal is used to control clock signals internal to the DDR. When CKE is high, the internal clock signal, device input buffering, and output driver units are enabled.

The Chip Select (CS) signal is used to latch the chip. When CS is high, all commands are ignored. In some embodiments, CS1 may be reserved to be compatible with other chips.

A command/address input (CA) signal may be used as an address line or as a command code.

Data input/output (DQ) signals can be understood as bidirectional data buses. The DDR shown in fig. 4 is a 16-bit chip, and thus, there are 16 DQ signals in total.

The data strobe (DQS) clock signal is also a differential clock signal that is asserted simultaneously with write data when input and asserted simultaneously with read data when output. Each 8-bit data signal corresponds to a pair of DQS signals, e.g., for a 16-bit DDR, the lower 8-bit data signals correspond to DQS0_ T and DQS0_ C; the high 8-bit data signals correspond to DQS1_ T and DQS1_ C.

A data mask/data bus inversion (DMI) signal is used to indicate data that needs to be masked and data that needs to be inverted on the bus.

It will be appreciated that the number of signals required for different DDRs may vary. Illustratively, an 8-bit DDR may include a CS signal and a CKE signal; a 16-bit single wafer package (die) DDR may include one CS signal and one CKE signal, while a 16-bit dual wafer package DDR may include two CS signals and two CKE signals; a 32-bit DDR may include two CS signals and two CKE signals, etc.

It is to be understood that, if the second device 102 in the communication system shown in fig. 1 is a DDR, the communication line 103 may include a communication line corresponding to the above 33 signals. In addition, the first device 101 needs to arrange pins for transmitting DDR signals, so that the pins for transmitting DDR signals occupy a smaller chip package area, and simultaneously, the quality of DDR signals is ensured.

For example, in the case where the first device 101 is a BGA package, the pins of the first device 101 may be arranged in the manner shown in fig. 5. Fig. 5 shows a total of 19 rows and 10 columns of cells. It is to be understood that, since the first device 101 employs a BGA package, although 190 cells are provided in total in fig. 5, the blank cells do not correspond to pins, and the remaining non-blank cells all correspond to one pin.

As shown in fig. 5, a plurality of pins in rows 2 to 6 are used to transmit the data signals DQ8-DQ10 of the upper 8 bits, and the corresponding clock signals (DQs1_ C and DQs1_ T) and DMI signal (DMI 1). Wherein:

pins of the 2 nd, 4 th and 6 th columns are used for transmitting DQ8-DQ10 and DMI 1; the pins of row 3, column 9 and row 2, column 8 are used to transmit DQS1_ C and DQS1_ T. The remaining pins are ground pins, i.e., for transmitting ground signals (GND).

A plurality of pins of 2 nd, 3 rd, 5 th, 7 th and 8 th columns in the 8 th to 12 th rows are used to transmit chip select signals CS0 and CS1, address signals CA0-CA5, clock signals CK _ T and CK _ C, and a clock enable signal CKE.

The plurality of pins in rows 14 through 18 are used to transmit the lower 8-bit data signals DQ0-DQ7, as well as the corresponding clock signals (DQs0_ C and DQs0_ T) and DMI signal (DMI 0). Wherein:

pins of the 2 nd, 4 th and 6 th columns are used for transmitting DQ0-DQ7 and DMI 0; the pins of row 17, column 9 and row 18, column 8 are used to transmit DQS0_ C and DQS0_ T.

It will be appreciated that if the second device 102 is a 16-bit single wafer package DDR, then the first device 101 may use one CS signal (i.e., CS0 or CS1) and the other CS signal as a spare.

It is understood that, in addition to the above pins for transmitting the DDR signal, the remaining pins may be used for transmitting the GND signal.

As can be known from fig. 5, the pins for transmitting the DDR signal and the ground pins occupy 19 rows and 10 columns of pins, and the pins for transmitting the DDR signal are arranged in the manner shown in fig. 5, so that the package area occupied by the first device 101 is large, and the total number of integrated signals of the first device 101 is small.

Based on the above problems, embodiments of the present application provide a signal transmission device and an electronic device. By some embodiments of the present application, the total number of pins for transmitting signals and the number of ground pins in the signal transmission device is reduced, thereby occupying less package area of the signal transmission device. In the embodiment of the present application, the signal transmission device may be understood as a device for communicating with a DDR, and the signal transmission device may be specifically understood as a chip. Illustratively, the signal transmission device may be a CPU or a baseband chip, etc.

In the embodiment of the application, the signal transmission device comprises a plurality of pins; the plurality of pins include a ground pin and a pin for transmitting a signal; the pins for transmitting signals comprise a first pin group and a second pin group;

the first pin group is distributed in an M x N area; said region of M x N comprising at least one, at most said M or said N of said ground pins; m and N are integers not less than 2;

the second pin group is distributed in the region of S x T; said region of S x T includes at least one, at most said S or said T of said ground pins; s and T are integers of 2 or more;

It can be understood that the signal transmission device provided in the embodiment of the present application is packaged by using a BGA packaging technology, and pins of the signal transmission device are arranged in a 45-degree skew manner, and the description of the 45-degree skew arrangement may refer to the description in fig. 3, which is not repeated herein.

For example, please refer to fig. 6, fig. 6 is a schematic diagram of a signal transmission apparatus according to an embodiment of the present application.

Fig. 6 can be understood as a top view of the signal transmission device 60, and the signal transmission device 60 shown in fig. 6 includes a plurality of pins, and the plurality of pins included in the signal transmission device 60 may be, for example, 16 rows and 16 columns of pins.

It is understood that in the embodiment of the present application, the signal transmission device 60 includes a plurality of pins, which can establish a connection with other devices (e.g., DDR) through the PCB, thereby achieving communication between the signal transmission device 60 and other devices. Therefore, a part of the pins in the signal transmission device 60 will be used for transmission of DDR signals.

In the embodiment of the present application, the pins in the signal transmission device 60 include a ground pin and a pin for transmitting a signal. For example, the ground pin may be understood as a pin for transmitting a ground signal, and the pin for transmitting a signal may be understood as a pin for transmitting a DDR signal to a DDR. It is understood that the signals transmitted to the DDR by the signal transmission device 60 may include data signals and address signals. Here, the plurality of pins for transmitting the data signal may be understood as the first pin group, and the plurality of pins for transmitting the address signal may be understood as the second pin group.

It will be appreciated that the signal transmission means 60 may arrange the pins for transmitting signals in a variety of ways. In the embodiment of the present application, the first pin group is arranged in the region of M × N, and it can be understood that the pins in the first pin group occupy M rows and N columns in the signal transmission device. And at least one, at most M or N grounding pins are also included in the region of M x N.

For example, please refer to fig. 6, wherein fig. 6 is a schematic pin layout diagram of a signal transmission device according to an embodiment of the present disclosure. As shown in fig. 6, a portion 601 in fig. 6 can be understood as the region of M × N. For example, the first pin group may include 11 pins, 12 pins, and the like, and the present embodiment takes 12 pins as an example for description.

It is understood that the 12 pins may be arranged in various ways as long as the region that satisfies M × N occupied by the first pin group includes at least one, at most M, or N grounding pins.

For example, the first pin group may occupy 5 rows and 7 columns of pins, in this case, the area of 5 rows and 7 columns may include 18 pins, 12 pins of which may be used to set the first pin group, and the remaining 6 pins may be used to set the ground pin.

For example, the 12 pins may also occupy an area of 5 rows and 6 columns, in this case, the area of 5 rows and 6 columns may include 15 pins, where 12 pins may be used to set the first pin group, and the remaining 3 pins may be used to set the ground pin.

For example, the 12 pins may also occupy an area of 5 rows and 5 columns, in this case, the area of 5 rows and 5 columns may include 13 pins, where 12 pins may be used to set the first pin group, and the remaining 1 pin may be used to set a ground pin.

Next, the first lead group will be described by taking the lead occupying 5 rows and 7 columns as an example.

As in portion 601 of fig. 6, the white pin in portion 601 may be understood as a pin for transmitting a data signal. For example, the first pin group occupies 5 rows and 7 columns of pins, which means that M is equal to 5 and N is equal to 7.

Illustratively, in the area of 5 rows and 7 columns, 6 grounding pins, such as the black pins in the portion 601, may be included, which may be understood as grounding pins. It is understood that the arrangement positions of the grounding pins included in the region of M × N may be changed, that is, the 6 grounding pins may be placed at any position in the region of 5 rows and 7 columns. For example, the above 6 ground pins can also refer to a part 701 in fig. 7 and a part 801 in fig. 8.

It is understood that the number of the ground pins included in the M × N region may also vary, and it is only necessary that at least one ground pin is included in the M × N region, and the number of the ground pins does not exceed the number of rows of the M × N region, or the number of the ground pins does not exceed the number of columns of the M × N region. Illustratively, the number of the ground pins in the area of 5 rows and 7 columns may also be 5, 4, 3, or the like.

Similarly, in the embodiment of the present application, the second pin group is arranged in the region of S × T, and it can be understood that the pins in the second pin group occupy S rows and T columns in the signal transmission device. The region of S x T also comprises at least one grounding pin, at most S or T grounding pins.

Exemplarily, the portion 602 in fig. 6 may be understood as the region of S × T described above. Like the above-mentioned portion 601, the number of the leads in the second lead group may be 11, 12, 14, etc., and this embodiment will be described by taking the example that the second lead group includes 14 leads.

It is understood that the 14 pins may be arranged in various ways as long as the region that satisfies S × T occupied by the second pin group includes at least one, at most S, or T grounding pins.

For example, the second pin group may occupy 5 rows and 7 columns of pins, in which case, the area of 5 rows and 7 columns may include 18 pins, of which 14 pins may be used to set the second pin group, and the remaining 4 pins may be used to set the ground pin.

For example, the 14 pins may also occupy an area of 5 rows and 6 columns, in this case, the area of 5 rows and 6 columns may include 15 pins, where 14 pins may be used to set the second pin group, and the remaining 1 pin may be used to set a ground pin.

For example, the 12 pins may also occupy an area of 6 rows and 5 columns, in this case, the area of 6 rows and 5 columns may include 15 pins, 14 of the pins may be used to set the second pin group, and the remaining 1 pin may be used to set the ground pin.

Next, the second lead group will be described by taking the lead occupying 5 rows and 7 columns as an example.

As shown in portion 602 of fig. 6, the white pin in portion 602 may be understood as a pin for transmitting an address signal. For example, the second pin group occupies 5 rows and 7 columns of pins, which means that S is equal to 5 and T is equal to 7. Illustratively, in the area of 5 rows and 7 columns, 4 grounding pins, such as the black pins in the portion 602, may be included, which may be understood as grounding pins.

It is understood that the arrangement positions of the grounding pins included in the region of S × T may be changed, that is, the 4 grounding pins may be placed at any position in the region of the 5 rows and 7 columns. For example, the above-mentioned 4 ground pins can also be referred to as part 702 in fig. 7 and part 802 in fig. 8.

It is understood that the number of the ground pins included in the region of S × T may also vary, and it is only necessary that at least one ground pin is included in the region of S × T, and the number of the ground pins does not exceed the number of rows of the region of S × T, or the number of the ground pins does not exceed the number of columns of the region of S × T. Illustratively, the number of the ground pins in the area of 5 rows and 7 columns may also be 3, 2 or 1, etc.

In the signal transmission device provided in the embodiment of the present application, the first pin group is configured to transmit a data signal, and the second pin group is configured to transmit an address signal, where the number of ground pins in an M × N region distributed in the first pin group is at least one, and at most M or at most N; the number of the grounding pins in the S-T area distributed by the second pin group is at least one, at most S or at most T, and the number of the grounding pins is reduced while the signal quality is ensured by adjusting the arrangement mode of the signal transmission pins, so that the packaging area occupied by the signal transmission device is reduced.

In some embodiments, the first pin group is further configured to transmit a first clock signal, and the pins for transmitting the first clock signal are adjacent to each other at an oblique angle; the first clock signal is used for synchronizing the data signal;

Illustratively, as shown in part 701 of fig. 7, two gray pins, i.e., the pin corresponding to row 3, column 10 and the pin corresponding to row 4, column 11, can be understood as diagonally adjacent pins for transmitting the first clock signal. As shown in fig. 7 at 702, two gray pins, i.e., the pin corresponding to row 10, column 13 and the pin corresponding to row 9, column 14, can be understood as pins adjacent to each other at an oblique angle for transmitting the second clock signal.

It is to be understood that the pins for transmitting the first clock signal may be arranged at other positions in the region of M × N; the pins for transmitting the second clock signal may be arranged at other positions in the region of S × T, which may specifically refer to

portions

801 and 802 in fig. 8, and details are not repeated here.

In other embodiments, the pins outside the M × N region and adjacent to the pins in the M × N region at an oblique angle are the ground pins; and the pins outside the area of S x T and adjacent to the pins in the area of S x T in an oblique angle are the grounding pins.

Illustratively, as shown in fig. 8, the black pins in column 9, row 2, row 8, and row 14 may be understood as pins that are adjacent to the pins in the region of M × N or the region of S × T at an oblique angle. In the embodiment of the application, the pins adjacent to the M x N area and the S x T area in the oblique angle are set as the grounding pins, so that the signal quality can be improved.

In still other embodiments, the number of pins in the first pin group is equal to 11, M is equal to 5, and N is equal to 5; the number of pins in the second pin group is equal to 11, S is equal to 5, and T is equal to 5.

In this way, the M × N region is a 5-row and 5-column region, and the S × T region is a 5-row and 5-column region. The number of pins in the first pin group is equal to 11, and the first pin group may include, for example, 8 pins for transmitting a data signal, 2 pins for transmitting a clock signal (which may be understood as the first clock signal), and 1 pin for transmitting a first control signal, which is used for controlling the data signal and may be understood as the DMI signal.

Similarly, the number of pins in the second pin group is equal to 11, and the second pin group may include, for example, 6 pins for transmitting an address signal, 2 pins for transmitting a clock signal (which may be understood as the second clock signal), 2 pins for transmitting a first chip select signal, and 1 pin for transmitting a first clock enable signal. The first chip select signal may be a CS signal, and the first clock enable signal may be a CKE signal.

It is understood that, when the M × N region is a region of 5 rows and 5 columns and the S × T region is a region of 5 rows and 5 columns, the arrangement may be as shown in fig. 9 (a), or as shown in fig. 9 (B). It is understood that, in the case of the arrangement as shown in fig. 9 (a), the number of the ground pins included therein may be 1 or 2; in the case of the arrangement as shown in fig. 9 (B), the number of the ground pins included therein is 1.

In still other embodiments, in the region of M × N, the number of pins corresponding to M being equal to 1 is equal to 2; one pin located on the first symmetric center line of the M x N area is the grounding pin; the first symmetrical center line comprises a symmetrical center line which is symmetrical up and down or a symmetrical center line which is symmetrical left and right;

in the region of S x T, the number of the pins corresponding to the S equal to 1 is equal to 2; one pin located on a second symmetric center line of the region of S × T is the grounding pin, and the second symmetric center line includes a symmetric center line that is vertically symmetric or a symmetric center line that is horizontally symmetric.

For example, please refer to fig. 10, wherein fig. 10 is a schematic diagram of another signal transmission apparatus provided in the embodiment of the present application. As part 1001 in fig. 10, the region of M × N may be understood as including 5 rows and 5 columns. In this case, the number of the 1 st row pins corresponding to M being equal to 1 is 2, that is, in the above case, the M × N region adopts the arrangement manner as shown in fig. 9 (B). Illustratively, as in part 1001 of fig. 10, where row 1 includes two pins, row 2 includes 3 pins, row 3 includes 2 pins, row 4 includes 3 pins, and row 5 includes 2 pins.

It is understood that the pins of part 1001 in fig. 10 are symmetrically distributed. Illustratively, the pins in the portion 1001 may be understood as being symmetrical up and down, wherein the pin corresponding to row 6, column 13 and the pin corresponding to row 6, column 15 may be understood as the pin at the first symmetrical center. Illustratively, the pins in the 1001 part may also be understood as left-right symmetrical, wherein the pins corresponding to the 14 th column in the 5 th row and the 14 th column in the 7 th row may also be understood as the pins at the first symmetrical center.

In summary, the pins of 4 in portion 1002 of fig. 10 can be understood as the pins on the first symmetric center line of the region of M × N.

Similarly, the portion 1003 in fig. 10 can be understood as the region of S × T, which includes 5 rows and 5 columns, wherein the 1 st row includes 2 pins. The pins of 4 as in part 1004 of fig. 10 can be understood as pins on the second symmetric center line of the region of S x T described above.

Fig. 10 exemplarily sets a pin corresponding to 14 th row in portion 1002 as a ground pin, and sets a pin corresponding to 13 th column in portion 1004 in row 12 as a ground pin. Through the mode, one pin on the first symmetrical center line of the M x N area and one pin on the second symmetrical center line of the S x T area are set as the grounding pins, and compared with the mode that the grounding pins are arranged on the places except the symmetrical center lines, the grounding isolation degree between transmission signals can be improved, and the signal quality is improved.

In still other embodiments, in the region of M × N, the pins corresponding to M equal to 1 and N equal to 2 and the pins corresponding to M equal to 2 and N equal to 1 are used for transmitting the first clock signal; one pin which is located on a first symmetrical center line of the M x N area and N is equal to 3 is the grounding pin;

in the region of S × T, the pin corresponding to S equal to 1 and T equal to 2 and the pin corresponding to S equal to 2 and T equal to 1 are used for transmitting the second clock signal; and one pin which is positioned on the symmetrical center line of the S-T area and the T is equal to 3 is the grounding pin.

For example, the signal transmission device shown in fig. 10 is taken as a basis for explanation, please refer to fig. 11, and fig. 11 is a schematic diagram of another signal transmission device provided in the embodiment of the present application.

As shown in fig. 11, a portion 1101 in fig. 11 can be understood as the region of M × N described above. Where M equals 5, N equals 5, and the number of pins in the first row of portion 1101 equals 2. As can be understood from the description related to fig. 10, the pins in the portion 1102 in fig. 11 are located on the first symmetric center line, and the pins in the portion 1102 correspond to the 3 rd column of the portion 1001, that is, N is equal to 3. In this embodiment, one pin in the portion 1102 is set as a ground pin, and exemplarily, a pin corresponding to the 7 th row and the 14 th column is set as a ground pin.

In addition, in this embodiment, the pin corresponding to the condition that M is equal to 1 and N is equal to 2 and the pin corresponding to the condition that M is equal to 2 and N is equal to 1 are used for transmitting the first clock signal. As in section 1001, the pins corresponding to row 4, column 13 and the pins corresponding to column 12 (e.g., the gray pins in section 1101) can be understood as pins for transmitting the first clock signal described above.

Similarly, the portion 1103 in fig. 11 can be understood as the region of S × T described above. Wherein S is equal to 5, T is equal to 5, and the number of pins in the first row of the 1103 portion is equal to 2. As will be understood from the description related to fig. 10, the pin in the portion 1104 in fig. 11 is located on the second symmetric centerline, and the pin in the portion 1104 corresponds to the 3 rd column of the portion 1003, that is, T is equal to 3. In this embodiment, one pin in the portion 1104 is set as a ground pin, and exemplarily, a pin corresponding to the 11 th row and the 14 th column is set as a ground pin.

In addition, the pin corresponding to S equal to 1 and T equal to 2 and the pin corresponding to S equal to 2 and T equal to 1 are used for transmitting the second clock signal. As in section 1003, the pins corresponding to row 10, column 13 and row 11, column 12 (e.g., the gray pins in section 1103) can be understood as the pins for transmitting the first clock signal.

It will be appreciated that the 11 pins for transmitting signals can each be located adjacent to a ground pin by the ground pin in section 1002, the ground pin in section 1004, and the ground pins around

sections

1001 and 1003, thereby improving signal quality. In addition, the clock signal is arranged at the upper left corner of the M x N area and the S x T area, so that the DDR can be better adapted to external connection, the connecting line of the signal transmission device and the DDR is not crossed, and the normal transmission of the signal is ensured.

In still other embodiments, in the region of M × N, the pin corresponding to M being equal to 4 and N being equal to 3 is the ground pin; in the region of S × T, the pin corresponding to S equal to 4 and T equal to 3 is the ground pin.

For example, please refer to fig. 12, fig. 12 is a schematic diagram of another signal transmission apparatus according to an embodiment of the present application. It is to be understood that fig. 12 is based on fig. 11 and further defines the location of the ground pin. As shown in fig. 12, a region 1201 may be regarded as the region M × N, and a region 1202 may be regarded as the region S × T. As shown in fig. 12, the pins in the 7 th row and the 14 th column in the M × N region are set as ground pins, and the pins in the 13 th row and the 14 th column in the S × T region are set as ground pins.

Through the mode, on one hand, the quality of the signals transmitted by the signal transmission device can be ensured, namely, each signal can be separated by the grounding signal, and the signal transmission device has good ground isolation; and the number of pins for transmitting signals and the number of grounding pins can be reduced, so that the packaging area is reduced.

Finally, the order and the number of layers of the PCB can be reduced through the mode, namely, the signals can be wired through the 2-order PCB and the 2-layer wiring board, and the development cost of the PCB is saved.

In still other embodiments, in the case that the number of bits of the data signal is greater than 8, the apparatus further includes a third pin group, the third pin group being distributed in an X Y region, the X Y region including at least one, at most the X, or the Y ground pins; x and Y are integers of 2 or more;

the first pin group is used for transmitting high-order 8-bit signals in the data signals, and the third data signal group is used for transmitting low-order 8-bit signals in the data signals; or, the first pin group is used for transmitting a low 8-bit signal of the data signals, and the third pin group is used for transmitting a high 8-bit signal of the data signals.

Illustratively, the 16-bit DDR signal shown in fig. 4 is taken as an example for explanation. For example, referring to fig. 13, fig. 13 is a schematic pin layout diagram of a signal transmission apparatus for transmitting a 16-bit DDR signal according to an embodiment of the present disclosure. It is understood that the signal transmission device 130 in fig. 13 is packaged by BGA packaging technology, and the leads are arranged at 45 degree skew.

First, the DDR signals that the signal transmission device 130 needs to transmit are grouped. Illustratively, the address signal and the signal related to the address signal are one set, and each 8-bit data signal and the signal related to the 8-bit data signal are one set. The data signals with 8 high bits are a group, and the data signals with 8 low bits are a group. Illustratively, the signals shown in fig. 4 may be divided into 3 groups.

The group 1 includes a group of address signals CA0 through CA5, a pair of chip select signals CS0 and CS1, clock signals CK _ T, CK _ C, and CKE signals. It is understood that in the case of a single wafer package for a 16-bit DDR, only one chip select signal may be included in the 1 st group, i.e., any one of the chip select signals (CS0 or CS1) in the 1 st group may be used as a spare signal. In the case of a 16-bit DDR employing a dual wafer package, the group 1 signal may include two chip select signals, which may include CS0 and CS1, for example.

Group 2 includes the first 8-bit data signals DQ0 through DQ7 for DDR, the corresponding clock signals DQS0_ T, DQS0_ C, and the DMI signal.

Group 3 includes the second 8-bit data signals DQ8-DQ15 for DDR, the corresponding clock signals QS 1-T, DQS1_ C and DMI signals.

In the embodiment of the present application, if there is a higher-order data signal in the DDR, the process may be repeated in the same way, that is, each 8-bit data signal, the corresponding clock signal, and the DMI signal form a group. Illustratively, the DDR includes 32-bit data signals, and then the address signals and associated signals are grouped, and the 32-bit data signals are grouped by bit number every 8 bits, for a total of 4 groups.

In this embodiment, the pins of the signal transmission device (which may be referred to as signal pins, or signal BALL) may be understood as an M-row and N-column dot array, such as signal transmission device 130 in fig. 13, where the signal transmission device 130 includes a plurality of pins, and exemplarily, the signal transmission device 130 includes 27 rows and 25 columns of pins.

In this embodiment, as shown in fig. 13 at

part

1301, 19 rows and 6 columns of pins in the signal transmission apparatus 130 are taken to transmit DDR signals. It is understood that the portion 1301 is located at the edge of the signal transmission device 130 to facilitate the pin of the signal transmission device 130 to be out of the line and to save the pin of the signal transmission device 130.

In particular, for ease of understanding, the pins of section 1301 are numbered, the occupied columns may be respectively represented by letters, and the occupied rows may be represented by numbers. Illustratively, as shown in fig. 13 at 1302, a column of pins nearest to the edge of the signal transmission device is numbered a, and extends into the signal transmission device along the transverse direction of the signal transmission device, and the serial number of each column of pins is A, B, C, D, E, F in turn. Each row of pins is denoted from top to bottom by the

numbers

1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, respectively.

For example, when the signal transmission device 130 uses the 19 rows and 6 columns of pins to transmit the 3 sets of DDR signals, the pins used for each set of signals are arranged along the longitudinal direction of the signal transmission device 130, and a row of ground pins is included between each set of signals. For ease of understanding, referring to FIG. 14, each non-blank cell in FIG. 14 corresponds to a pin as in portion 1302 of FIG. 13. As shown in fig. 14, group 3 signals are transmitted using pins in rows 2 through 6; group 1 signals are transmitted using pins in rows 2 through 6; group 2 signals are transmitted using pins in rows 2 through 6. In addition, the pin of the 7 th row and the pin of the 13 th row are used for transmitting a ground signal; the pin of the 1 st row and the pin of the 19 th row are used for transmitting a ground signal, and the pin of the F-th column is used for transmitting a ground signal.

As shown in fig. 14, each group of signals occupies 5 rows and 5 columns of pins in the signal transmission device 130. Wherein:

row 1 (e.g., row 2, row 8, row 14) within a group occupies 2 pins for transmitting 2 signals.

Row 2 (e.g., row 3, row 9, row 15) within the group occupies 3 pins for transmitting 3 signals.

Row 3 (e.g., row 4, row 10, row 16) within the group occupies 2 pins for transmitting 2 signals.

Row 4 (e.g., row 5, row 11, row 17) within a group occupies 3 pins for transmitting 3 signals.

Row 5 (e.g., row 6, row 12, row 18) within the group occupies 2 pins for transmitting 2 signals.

Thus, the number of pins contained in each row within a group, i.e., the number of signals transmitted, is 2, 3, 2, 3, 2 in sequence. In this embodiment, the pins corresponding to the 1 st row and the 4 th column and the pins corresponding to the 2 nd row and the 5 th column in the group are used for transmitting the clock signal of the group. On one hand, the signal transmission device 130 and the DDR can be ensured to have no crossed wiring, and signal transmission is ensured; on the other hand, the above arrangement is advantageous for coupling between two clock signals. For example, a pin corresponding to D2 and a pin corresponding to E3 are used for transmitting differential clock signals DQS1_ T and DQS1_ C of a high 8-bit data signal; the pin corresponding to the D8 and the pin corresponding to the E9 are used for transmitting differential clock signals CK _ T and CK _ C; the pin corresponding to the D14 and the pin corresponding to the E15 are used for transmitting differential clock signals DQS1_ T and DQS1_ C of the low 8-bit data signal.

In this embodiment, D2 represents column D, row 2, and so on.

In this embodiment, the pins corresponding to the 4 th row and the 3 rd column in the group are used for transmitting a ground signal, and serve as a reference ground for the whole group of signals, so as to improve the signal quality. For example, the pin corresponding to C5, the pin corresponding to C11, and the pin corresponding to C17 are all used for transmitting ground signals.

In this embodiment, other pins in the group may transmit the remaining signals according to actual conditions. For example, DQ8-DQ15 or DMI1 signals can be transmitted by pins corresponding to A3, a5, B2, B4, B6, C3, D4, D6 and E5; the CA0-CA5, the CS signals and the CKE signals can be transmitted by pins corresponding to A9, A11, B8, B10, B12, C9, D10, D12 and E11; DQ0-DQ7 or DMI0 signals can be transmitted by pins corresponding to A15, A17, B14, B16, B18, C15, D16, D18 and E17.

The present application also provides a signal wiring board based on the design of the pins as in section 1302 in fig. 16. The signal wiring board can be understood as a PCB, DDR signal wiring can be achieved by adopting 2-level boards and 2 wiring layer surfaces, the number of layers of the required signal wiring board is small, the order is low, and therefore the design cost of the signal wiring board is reduced.

Illustratively, the signal wiring board includes a first wiring layer and a second wiring layer; a first wiring layer for wiring signals transmitted by pins in the A-th and B-th columns of the signal transmission device; and the second wiring layer is used for wiring signals transmitted by pins of the C-th column, the D-th column, the E-th column and the F-th column of the signal transmission device.

For example, please refer to fig. 15, where fig. 15 is a schematic diagram of a wiring manner of a first wiring layer according to an embodiment of the present application. As shown in fig. 15, the first wiring layer of the signal wiring board can be used for wiring signals transmitted by the pins of the a-th column and the B-th column. The black pins in the A-th row and the B-th row can be understood as grounding pins, the other non-black pins can be understood as pins for transmitting DDR signals, and each DDR signal line can be isolated and protected by a grounding signal line, so that the quality of the DDR signals is improved.

In some embodiments, the signal wiring board further includes a third wiring layer for providing the first ground plane, the third wiring layer being located between the first wiring layer and the second wiring layer, providing a complete reference ground plane for the first wiring layer and the second wiring layer, and providing a complete isolation layer between the first wiring level and the second wiring level, thereby improving signal quality.

It should be noted that the black square in the portion 1501 in fig. 15 can be understood as a hole for transmitting a ground signal on the signal board. It is understood that the ground signal can be connected to the first ground plane by punching a hole in the signal wiring board. Furthermore, each signal can be protected by a grounding signal on the signal wiring board, grounding isolation is provided for each transmission signal, and the quality of the transmission signal is improved.

For example, please refer to fig. 15, where fig. 15 is a schematic diagram of a wiring manner of a second wiring layer according to an embodiment of the present application. The second wiring layer of the signal wiring board may be used for wiring signals transmitted by pins of the C-th column, the D-th column, the E-th column, and the F-th column. The black pin may be understood as a ground pin, and the remaining non-black pins may be understood as pins for transmitting DDR signals.

In particular, the gray pin can be understood as a pin for transmitting a clock signal, and as shown in fig. 16, the clock signals can be isolated without using a ground signal, so that the two clock signals can be coupled to ensure the validity of the clock signals. Other white can be understood as pins for transmitting DDR signals, and each DDR signal line can be isolated and protected by a grounding signal line, so that the DDR signal quality is high.

In summary, when the signal transmission apparatus 130 designs the signals transmitted by the pins in the above manner, it can be ensured that the clock signals can be coupled with each other for transmission, and also that each of the other DDR signals is isolated by the ground signal, thereby ensuring high transmission quality of the DDR signals. In addition, when the signal transmitted by the pin is designed in the above manner, the number of pins occupied by the signal transmission device 130 is small, the packaging area occupied by the signal transmission device 130 is small, and the signal transmission device 130 can be used for transmitting more signals. Finally, when the signals transmitted by the pins are designed in the mode, DDR signal wiring can be achieved by using 2 wiring layers, and therefore wiring cost is saved.

It is understood that the signal transmission device provided by the present application may further include a fourth pin group, a fifth pin group, a sixth pin group, and the like. In a case where the number of bits of the data signal is 32 bits, the first pin group, the third pin group, the fourth pin group, and the sixth pin group are used to transmit the 32-bit data signal, and each pin group may be used to transmit a continuous 8-bit data signal; the second pin group and the fifth pin group are used for transmitting address signals, chip selection signals, clock enabling signals and the like.

It is understood that the 32-bit DDR group of pins for transferring address signals includes two chip select signals and two clock enable signals. That is, the second pin group and the fifth pin group include two CS signals and two CKE signals, respectively. Since the requirement for the non-data signal rate is low, one ground pin around the region of S × T may be reduced to set one of the two CS signals, or may be set inside the region of S × T, which is not limited in this application.

In some embodiments, in the case that the number of the chip selection signals is greater than or equal to 2, pins for transmitting the chip selection signals are arranged adjacently; and under the condition that the number of the clock enabling signals is greater than or equal to 2, pins for transmitting the clock enabling signals are adjacently arranged.

It is understood that the above description can be repeated in the case that the number of bits of the data signal is 64 bits.

The embodiment of the application also provides electronic equipment which comprises the signal transmission device. Illustratively, the electronic device may include one or more of:

a charging management module for receiving charging input from the charger. The charger can be a wireless charger or a wired charger.

The mobile communication module can provide a solution including wireless communication of 2G/3G/4G/5G and the like applied to the module switching device. The mobile communication module may include at least one filter, a switch, a power amplifier, a Low Noise Amplifier (LNA), and the like.

The wireless communication module may provide a solution for wireless communication including a Wireless Local Area Network (WLAN) (e.g., a wireless fidelity (Wi-Fi) network), Bluetooth (BT), a Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), and the like, which is applied to the module switching device.

In some embodiments, the signal transmission device may be included in the mobile communication module or the wireless communication module. In other embodiments, the signaling device may be used to communicate with the DDR, read data from the DDR, store data to the DDR, or the like. For example, the electronic device may be a physical device such as a mobile phone, a wearable device, and an in-vehicle device, which is not limited in this application.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the above claims.

Claims

1. A signal transmission apparatus, characterized in that the apparatus comprises:

a plurality of pins;

the plurality of pins comprise a ground pin and a pin for transmitting signals; the pins for transmitting signals comprise a first pin group and a second pin group;

the first pin group is distributed in an M x N area; said region of M x N comprises at least one, at most said M or said N of said ground pins; said M and said N are integers greater than or equal to 2;

the second pin group is distributed in the region of S x T; said region of S x T comprises at least one, at most said S or said T of said ground pins; s and T are integers greater than or equal to 2;

the first pin group is used for transmitting data signals, transmitting first clock signals, and the pins for transmitting the first clock signals are adjacent in an oblique angle; the first clock signal is used for synchronization of the data signal;

the second pin group is used for transmitting address signals, transmitting second clock signals and enabling pins for transmitting the second clock signals to be adjacent in an oblique angle; the second clock signal is used for synchronization of the address signal;

the number of pins in the first pin group is equal to 11, M is equal to 5, and N is equal to 5; the number of pins in the second pin group is equal to 11, S is equal to 5, and T is equal to 5;

in the region of M × N, the number of pins corresponding to M equal to 1 is equal to 2; one pin positioned on the first symmetrical center line of the M x N area is the grounding pin; the first symmetrical center line comprises a symmetrical center line which is symmetrical up and down or a symmetrical center line which is symmetrical left and right;

in the region of S x T, the number of the pins corresponding to the S equal to 1 is equal to 2; one pin positioned on a second symmetrical center line of the S x T area is the grounding pin; the second symmetrical center line comprises a symmetrical center line which is symmetrical up and down or a symmetrical center line which is symmetrical left and right.

2. The device of claim 1, wherein the pins outside the region of M x N and adjacent to the pins in the region of M x N at oblique angles are the ground pins; and the pins outside the area of S x T and adjacent to the pins in the area of S x T in an oblique angle are the grounding pins.

3. The apparatus according to claim 2, wherein in the region of M x N, the pin corresponding to M equal to 1 and N equal to 2 and the pin corresponding to M equal to 2 and N equal to 1 are used for transmitting the first clock signal; one pin which is positioned on a first symmetrical center line of the region of M x N and N is equal to 3 is the grounding pin;

in the region of S × T, the pin corresponding to S equal to 1 and T equal to 2 and the pin corresponding to S equal to 2 and T equal to 1 are used for transmitting the second clock signal; and one pin which is positioned on a second symmetrical center line of the S x T area and the T is equal to 3 is the grounding pin.

4. The apparatus of claim 3, wherein in the region of M x N, the pin corresponding to M equal to 4 and N equal to 3 is the ground pin; in the region of S × T, the pin corresponding to S equal to 4 and T equal to 3 is the ground pin.

5. The apparatus of any of claims 1-4, wherein the first pin group is further configured to transmit a first control signal, the first control signal being configured to control the data signal;

the second pin group is also used for transmitting a first chip selection signal and a first clock enabling signal.

6. The apparatus of claim 5, wherein in the case that the number of bits of the data signal is greater than 8, the apparatus further comprises a third pin group, the third pin group being distributed within an X Y region; said region of X Y comprises at least one, at most said X or said Y of said ground pins; said X and said Y are integers greater than or equal to 2;

the first pin group is used for transmitting an upper 8-bit signal in the data signals, and the third data signal group is used for transmitting a lower 8-bit signal in the data signals; or, the first pin group is used for transmitting a low 8-bit signal in the data signal, and the third pin group is used for transmitting a high 8-bit signal in the data signal.

7. An electronic device, characterized in that the electronic device comprises a signal transmission arrangement according to any one of claims 1-6.