CN113972260A - 一种高可靠性的沟槽栅型碳化硅mosfet器件 - Google Patents

一种高可靠性的沟槽栅型碳化硅mosfet器件 Download PDF

Info

Publication number
CN113972260A
CN113972260A CN202111044550.XA CN202111044550A CN113972260A CN 113972260 A CN113972260 A CN 113972260A CN 202111044550 A CN202111044550 A CN 202111044550A CN 113972260 A CN113972260 A CN 113972260A
Authority
CN
China
Prior art keywords
region
type
gate
equivalent resistance
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111044550.XA
Other languages
English (en)
Inventor
盛况
任娜
林超彪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZJU Hangzhou Global Scientific and Technological Innovation Center
Original Assignee
ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZJU Hangzhou Global Scientific and Technological Innovation Center filed Critical ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority to CN202111044550.XA priority Critical patent/CN113972260A/zh
Publication of CN113972260A publication Critical patent/CN113972260A/zh
Priority to US17/903,029 priority patent/US20230072827A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、N‑型漂移区、第一P区、P+接触区、N+接触区、位于第一P区和N+接触区之间的N型等效电阻区、栅介质层、槽栅、隔离介质层、源电极、漏电极。本发明提出的SiC MOSFET器件通过增加一个N型等效电阻区，起到串联电阻的作用，当器件发生短路时，降低了器件的饱和电流，提高了其短路能力。

Description

一种高可靠性的沟槽栅型碳化硅MOSFET器件
技术领域
本发明涉及一种半导体器件，更具体地说，本发明涉及一种高可靠性的沟槽栅型碳化硅MOSFET器件。
背景技术
碳化硅(SiC)材料作为一种宽禁带半导体材料，具有高击穿场强、高饱和电子漂移速率、高热导率等优点，因此碳化硅功率半导体器件可以实现高压、大功率、高频、高温应用，可以提高电力电子装置的效率、降低装置体积和重量，比传统硅基器件更具优越性。
碳化硅MOSFET是新型宽禁带功率半导体器件之一，相比Si MOSFET或Si IGBT而言，SiC MOSFET具有更低的导通电阻，更强的耐高温能力和更快的开关速度。然而由于其较小的芯片面积、较高的电流密度以及较薄的栅极氧化物，SiC MOSFET的短路可靠性受到考验。目前商业化的碳化硅MOSFET主要分为两类：平面型和沟槽栅型。平面型的制作工艺相对沟槽栅型简单，但是带来的缺点是元胞面积增加以及导通电阻变大。传统的沟槽栅型MOSFET结构如图1所示，其能够实现更小的元胞尺寸，以及更高的沟道迁移率，从而大大降低了器件的导通电阻，是碳化硅MOSFET的重要发展分支。
沟槽栅型MOSFET相比于平面型MOSFET有更好的沟道利用率，以及消除了JFET区带来的电阻，但是其深槽刻蚀技术在工艺上有较大的挑战。刻蚀表面的形貌，包括刻蚀深度、刻蚀的垂直角度、刻蚀侧壁以及刻蚀底部的粗糙度、槽底角等，都对器件的性能有较大的影响。
碳化硅沟槽栅型MOSFET工作在阻断状态时，通过N-漂移区中形成的耗尽区来承受较高的反向偏压，由于碳化硅材料具有比较高的临界击穿电场，漂移区槽栅底部的位置会有电场集中效应，在临近击穿时会达到很高的电场。在阻断状态下，氧化层电场强度大约是碳化硅材料中最高电场的2.8倍，再加上曲率效应使得氧化层拐角聚集极高的电场，长时间工作在高电场下会导致栅氧化层发生退化，这就对栅介质的可靠性提出了很高的要求。
在实际电路中，可能会出现两种短路故障。第一种故障称之带负载短路：器件在正常工作时，负载突然短路，器件就从正常工作状态迅速转换成高压、大电流的工作状态；另一种故障称之为硬开关短路：当器件的初始状态是关断的，负载已经短路，此时突然给器件一个开通信号，漏源极仍然承受很高的电压，则器件从零电流状态迅速跳转至承受大电流的状态。器件短路时，会流过较大的电流，此时器件会产生很高的热量。由于沟槽栅型MOSFET的面积小，比导通电阻小，所以会产生更大的短路电流，对器件的可靠性提出严峻的挑战。
发明内容
本发明的目的在于提出一种高可靠性的沟槽栅型碳化硅MOSFET器件。通过在第一P区上部加入一个较低掺杂的N型等效电阻区，从而等效于在器件导通时，在器件的源极区域增加了一个串联电阻。当器件发生短路时，该串联电阻能够起到降低饱和电流的作用，从而提高了器件的短路能力。
根据本发明一实施例提出了一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、以及贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区。
根据本发明又一实施例提出了一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区以及形成于栅介质与N型等效电阻区之间的第二P区，其中N型等效电阻区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二P区的掺杂浓度大于N-型漂移区的掺杂浓度。
根据本发明又一实施例提出了一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区以及形成于栅介质与N型等效电阻区之间的第二P区，和形成于第一P区和N-型漂移区之间的N_CSL电流扩散区，其中N型等效电阻区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二P区的掺杂浓度大于N-型漂移区的掺杂浓度，N_CSL电流扩散区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度。
器件所用材料为SiC材料，也可为其他半导体材料。
本发明的有益效果为：当器件发生短路时，N型等效电阻区起到串联电阻的作用，能够降低器件的饱和电流，提高器件的短路能力。
附图说明
图1为传统的沟槽栅型SiC MOSFET器件；
图2为本发明一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图3为本发明一实施例的如图2所示的沟槽栅型碳化硅MOSFET器件在正向导通时的等效电流路径图；
图4为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图5为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图6为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图7为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图8为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图9为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图10为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图11为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图12为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图13为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图14为为本发明一实施例的如图13所示的沟槽栅型碳化硅MOSFET器件的等效电流路径图；
图15为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图16为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图17为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图18为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图；
图19为本发明另一实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件的结构示意图。
1为N+型衬底、2为N-型漂移区、3为第一P区、4为N+接触区、5为P+接触区、6为槽栅、7为栅介质、8为N_CSL电流扩散区、9为N型等效电阻区、10为第二N区、11为P+屏蔽层、12为第二P区，13为漏电极、14为源电极、15为隔离介质区，其中N+型衬底1掺杂浓度和N+接触区4浓度相近，N_CSL电流扩散区8浓度与N型等效电阻区9以及第二N区10浓度相近，掺杂浓度排序为：N+型衬底1，N+接触区4>N_CSL电流扩散区8，N型等效电阻区9，第二N区10>N-型漂移区；P型掺杂浓度排序为：P+接触区5>P+屏蔽层11>第一P区3、第二P区12。本发明实施例中所提到的N+掺杂可以是但不限于大于或等于1×1019cm-3，N掺杂可以是但不限于1×1016cm-3到1×1017cm-3，N-掺杂可以是但不限于5×1015cm-3到8×1015cm-3，P+掺杂可以是但不限于大于或等于1×1019cm-3，P掺杂可以是但不限于1×1017cm-3。
具体实施方式
下面将结合附图详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了便于对本发明的透彻理解，阐述了大量特定细节。本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
如图2所示，本实施例的一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底1、位于N+型衬底1下方的漏电极13、位于N+型衬底1上方的N-型漂移区2、栅介质7、槽栅区6、位于N-型漂移区2上方的第一P区3、位于第一P区3上方的N型等效电阻区9、位于N型等效电阻区9上方的N+接触区4、位于N+接触区4上方的源电极14、位于槽栅区6上方的隔离介质区15以及贯通N+接触区4、N型等效电阻区9并且延伸到第一P区3的P+接触区5。其中栅介质7位于槽栅区6周围并位于N-型漂移区2；所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N-型漂移区2；所述N型等效电阻区9的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度。
本实施例的工作原理为：
当器件工作在导通状态时，在栅介质7上施加正偏压，会在第一P区3感应出电子反型层，在漏电极13与源电极14之间施加一定的正向电压后，第一电流Ia(图3中带箭头的线条代表第一电流Ia的流通路径)经过N+型衬底1、N-型漂移区2、第一P区3中的导电沟道、N型等效电阻区9以及N+接触区4到达源极，其等效电流路径如图3所示，其中N型等效电阻区9可以等效为第一电阻Ra。当器件发生短路时，由于存在N型等效电阻区9，能够降低器件的饱和电流，提高了器件的短路能力，增强器件的可靠性。
如图4所示，本实施例的器件结构和图2所示实施例的区别在于：所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N-型漂移区2。
如图5所示，本实施例的器件结构和图2所示实施例的区别在于：在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8面积较小，只分布在栅介质7侧壁，未分布在栅介质7的底部。这样做的好处是：在正向导通状态下，N_CSL电流扩散区8由于掺杂浓度较高，能够起到扩散电流的作用，减小器件的导通电阻。
如图6所示，本实施例的器件结构和图5所示实施例的区别在于：P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N_CSL电流扩散区8。
如图7所示，本实施例的器件结构和图6所示实施例的区别在于：P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3、N_CSL电流扩散区8并延伸到N-型漂移区2。
如图8所示，本实施例的器件结构和图5所示实施例的区别在于：N_CSL电流扩散区8面积较大，分布在栅介质7的侧壁和栅介质7的底部。这样做的好处是：能够进一步降低器件的导通电阻。
如图9所示，本实施例的器件结构和图2所示实施例的区别在于：所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N-型漂移区2，在P+接触区5和N-型漂移区2之间设置有第二N区10。这样做的好处是：在阻断状态下，击穿点发生在P+接触区5和第二N区10的交界处，能够有效防止栅介质的击穿或者退化，对栅介质起到了保护的作用。
如图10所示，本实施例的器件结构和图2所示实施例的区别在于：所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N-型漂移区2，在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8面积较小，只分布在栅介质7侧壁，未分布在栅介质7的底部，在P+接触区5和N-型漂移区2之间设置有第二N区10。
如图11所示，本实施例的器件结构和图2所示实施例的区别在于：在栅介质7底部设置有P+屏蔽层11，其中P+接触区5可以只贯通N+接触区4、N型等效电阻区9、第一P区3，也可以延伸到N-型漂移区2。这样做的好处是：在阻断状态下，P+屏蔽层11能够对栅介质7底部的电场起到屏蔽作用，降低栅介质7拐角处的场强，保护了栅介质7。
如图12所示，本实施例的器件结构和图11所示实施例的区别在于：在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8既可以只分布在栅介质7侧壁，也可以分布在栅介质7侧壁和底部。
如图13所示，本实施例的器件结构和图2所示实施例的区别在于：在栅介质7与N型等效电阻区9之间增设了第二P区12，其中P+接触区5可以只贯通N+接触区4、N型等效电阻区9、第一P区3，也可以延伸到N-型漂移区2。其中N型等效电阻区9的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二P区的掺杂浓度大于N-型漂移区的掺杂浓度；所述第二P区12位于槽栅区6的垂直侧壁处且与所述第一P区3接触。该器件在正向导通时的等效电流路径如图14所示，其中第二P区12可以等效为第二电阻Rb。这样做的好处是：在短路发生时，第二电流Ib(图14中带箭头的线条代表第二电流Ib的流通路径)会经过第二P区12感应出的电子反型层流到源极，降低了器件的饱和电流，提高了其短路能力。
如图15所示，本实施例的器件结构和图13所示实施例的区别在于：在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8既可以只分布在栅介质7侧壁，也可以分布在栅介质7侧壁和底部。
如图16所示，本实施例的器件结构和图13所示实施例的区别在于：在栅介质7底部设置有P+屏蔽层11。
如图17所示，本实施例的器件结构和图16所示实施例的区别在于：在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8既可以只分布在栅介质7侧壁，也可以分布在栅介质7侧壁和底部。
如图18所示，本实施例的器件结构和图13所示实施例的区别在于：所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3并延伸到N-型漂移区2，在P+接触区5和N-型漂移区2之间设置有第二N区10。
如图19所示，本实施例的器件结构和图18所示实施例的区别在于：在第一P区3和N-型漂移区2之间存在N_CSL电流扩散区8，N_CSL电流扩散区8面积较小，只分布在栅介质7侧壁，未分布在栅介质7的底部，所述P+接触区5贯通N+接触区4、N型等效电阻区9、第一P区3、N_CSL电流扩散区8并延伸到N-型漂移区2。
在本发明的其它实施例中，上述的各掺杂类型可以相应变为相反的掺杂，例如P型掺杂变为N型掺杂的同时N型掺杂变为P型掺杂。
本发明涉及多个不同区域的组合结构和应用，在本发明实施例中未一一列举，本领域技术人员应当知悉，在其它实施例中，基于本发明结构的不同组合也应当作为本发明的实施例之一。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (10)

1.一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、以及贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区。
2.根据权利要求1所述的沟槽栅型碳化硅MOSFET器件，其中所述P+接触区贯通N+接触区、N型等效电阻区、第一P区并延伸到N-型漂移区。
3.根据权利要求1所述的沟槽栅型碳化硅MOSFET器件，其中N型等效电阻区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度。
4.根据权利要求1所述的沟槽栅型碳化硅MOSFET器件，还包括：形成于第一P区和N-型漂移区之间的N_CSL电流扩散区、形成于P+接触区和N-型漂移区之间的第二N区、形成于栅介质底部的P+屏蔽层或形成于栅介质与N型等效电阻区之间的第二P区中的一个、两个或多个。
5.根据权利要求4所述的沟槽栅型碳化硅MOSFET器件，其中当所述沟槽栅型碳化硅MOSFET器件包括N_CSL电流扩散区时，P+接触区贯通N接触区、N型等效电阻区、第一P区并延伸到N_CSL电流扩散区，或者P+接触区贯通N接触区、N型等效电阻区、第一P区、N_CSL电流扩散区并延伸到N-型漂移区。
6.根据权利要求5所述的沟槽栅型碳化硅MOSFET器件，其中N_CSL电流扩散区只分布在栅介质侧壁，未分布在栅介质的底部。
7.根据权利要求4所述的沟槽栅型碳化硅MOSFET器件，其中N_CSL电流扩散区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二N区的掺杂浓度大于N-型漂移区的掺杂浓度，P+屏蔽层的掺杂浓度小于P+接触区的掺杂浓度且大于第一P区或第二P区的掺杂浓度。
8.一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区以及形成于栅介质与N型等效电阻区之间的第二P区，其中N型等效电阻区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二P区的掺杂浓度大于N-型漂移区的掺杂浓度。
9.根据权利要求8所述的沟槽栅型碳化硅MOSFET器件，其中第二P区位于沟槽栅的垂直侧壁处且与第一P区接触。
10.一种高可靠性的沟槽栅型碳化硅MOSFET器件，包括：N+型衬底、位于N+型衬底下方的漏电极、位于N+型衬底上方的N-型漂移区、槽栅区、栅介质、位于N-型漂移区上方的第一P区、位于第一P区上方的N型等效电阻区、位于N型等效电阻区上方的N+接触区、位于N+接触区上方的源电极、位于槽栅区上方的隔离介质区、贯通N+接触区、N型等效电阻区并且延伸到第一P区的P+接触区以及形成于栅介质与N型等效电阻区之间的第二P区，和形成于第一P区和N-型漂移区之间的N_CSL电流扩散区，其中N型等效电阻区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度，第二P区的掺杂浓度大于N-型漂移区的掺杂浓度，N_CSL电流扩散区的掺杂浓度大于N-型漂移区的掺杂浓度且小于N+接触区的掺杂浓度。
CN202111044550.XA 2021-09-07 2021-09-07 一种高可靠性的沟槽栅型碳化硅mosfet器件 Pending CN113972260A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202111044550.XA CN113972260A (zh) 2021-09-07 2021-09-07 一种高可靠性的沟槽栅型碳化硅mosfet器件
US17/903,029 US20230072827A1 (en) 2021-09-07 2022-09-05 Trench gate silicon carbide mosfet with high reliability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111044550.XA CN113972260A (zh) 2021-09-07 2021-09-07 一种高可靠性的沟槽栅型碳化硅mosfet器件

Publications (1)

Publication Number Publication Date
CN113972260A true CN113972260A (zh) 2022-01-25

Family

ID=79586903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111044550.XA Pending CN113972260A (zh) 2021-09-07 2021-09-07 一种高可靠性的沟槽栅型碳化硅mosfet器件

Country Status (2)

Country Link
US (1) US20230072827A1 (zh)
CN (1) CN113972260A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117673165A (zh) * 2024-02-01 2024-03-08 深圳天狼芯半导体有限公司 深沟槽源极碳化硅器件及其制备方法、芯片

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117673165A (zh) * 2024-02-01 2024-03-08 深圳天狼芯半导体有限公司 深沟槽源极碳化硅器件及其制备方法、芯片

Also Published As

Publication number Publication date
US20230072827A1 (en) 2023-03-09

Similar Documents

Publication Publication Date Title
JP3968912B2 (ja) ダイオード
CN110518065B (zh) 低功耗高可靠性的沟槽型碳化硅mosfet器件
US10115815B2 (en) Transistor structures having a deep recessed P+ junction and methods for making same
CN109244136B (zh) 槽底肖特基接触SiC MOSFET器件
Takei et al. 600 V-IGBT with reverse blocking capability
CN111048585B (zh) 一种含有背面槽型介质及浮空区的逆导型igbt
US20150187678A1 (en) Power semiconductor device
CN109888007B (zh) 具有二极管钳位载流子存储层的soi ligbt器件
CN112928156B (zh) 一种浮空p柱的逆导型槽栅超结IGBT
CN111834449B (zh) 一种具有背面双mos结构的快速关断rc-igbt器件
JP3214343B2 (ja) 絶縁ゲート型サイリスタ
KR20100085508A (ko) 전계 분산 효과를 갖는 수직 게이트형 바이폴라 트렌지스터
CN113972260A (zh) 一种高可靠性的沟槽栅型碳化硅mosfet器件
CN108766998B (zh) 一种具有凹槽栅型jfet结构的igbt器件
CN109065629B (zh) 一种槽栅超结器件
US11984473B2 (en) Semiconductor device
JP7476129B2 (ja) 半導体装置及び半導体回路
CN109065626B (zh) 一种具有介质阻挡层的槽栅dmos器件
GB2612636A (en) Semiconductor device
US9209287B2 (en) Power semiconductor device
CN110265477B (zh) 具有pnp穿通三极管的igbt器件
CN111697070A (zh) 一种逆导型igbt器件
CN107248532B (zh) 一种超结dmos器件
CN112271208A (zh) 碳化硅单栅极双沟道晶闸管输运igbt及制造方法
US20150076595A1 (en) Power semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination