CN113964124A - Semiconductor contact structure, manufacturing method thereof and semiconductor memory - Google Patents
Semiconductor contact structure, manufacturing method thereof and semiconductor memory Download PDFInfo
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- CN113964124A CN113964124A CN202010702155.5A CN202010702155A CN113964124A CN 113964124 A CN113964124 A CN 113964124A CN 202010702155 A CN202010702155 A CN 202010702155A CN 113964124 A CN113964124 A CN 113964124A
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- side wall
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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Abstract
The disclosure provides a semiconductor contact structure, a manufacturing method thereof and a semiconductor memory. The semiconductor contact structure of the present disclosure includes: a semiconductor substrate; an active region defined by the device isolation region; a buried gate structure formed in the semiconductor substrate; and a contact structure formed between the buried gate structures; wherein the contact structure is self-aligned with the buried gate structure. This disclosure compares advantage with prior art and lies in: the photoetching alignment process is not needed, the contact position is in the central position of the two insulators, and the defects caused by electric leakage are prevented; the area of opposite contact with the bit line is reduced, and the capacitance of the bit line can be reduced; by means of the side wall process of the contact structure, a process window adjacent to the active region can be increased.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a semiconductor contact structure, a manufacturing method thereof and a semiconductor memory.
Background
As the line width of semiconductor circuits becomes narrower, the process difficulty increases, and the alignment of two different lithographic patterns becomes increasingly important. If the two lithographic patterns are misaligned, the semiconductor device may leak current, which may cause semiconductor defects.
FIG. 1A illustrates a plan view of a prior art semiconductor contact structure; FIG. 1B shows a cross-sectional view taken along lines a-a 'and B-B' of FIG. 1A.
Ideally, as shown in fig. 1a, the semiconductor devices are separated by an insulator in the middle, and the contact structure 100 connecting the upper and lower portions should be located at the center of the two insulators in the lower portion of the structure shown. However, as a result of the conventional photo alignment (photo alignment) technique, the contact 100 is not located at the center of the two insulators, and the insulators may be damaged when the contact is made, resulting in a poor semiconductor. Therefore, it is very important to develop Self-alignment (Self-alignment) technology.
Disclosure of Invention
The purpose of the present disclosure is to provide a semiconductor contact structure, a method for manufacturing the semiconductor contact structure, a semiconductor memory and an electronic device.
A first aspect of the present disclosure provides a semiconductor contact structure, comprising:
a semiconductor substrate;
an active region defined by the device isolation region;
a buried gate structure formed in the semiconductor substrate; and
a contact structure formed between the buried gate structures;
wherein the contact structure is self-aligned with the buried gate structure.
A second aspect of the present disclosure provides a method for manufacturing a semiconductor contact structure, including:
providing a semiconductor substrate; the semiconductor substrate comprises an active region defined by a device isolation region and a buried gate structure formed in the semiconductor substrate;
carrying out first selective etching on the semiconductor substrate between the buried gate structures to form a contact hole exposing the surface of the active region;
performing second selective etching on the semiconductor substrate downwards aiming at the contact hole to form a contact groove, wherein the area of the bottom surface of the contact hole is larger than that of the top surface of the contact groove;
forming a second contact side wall on the side wall of the contact groove, and forming a first contact side wall on the side wall of the contact hole;
and forming a contact plug in a space surrounded by the first contact side wall and the second contact side wall.
A third aspect of the present disclosure provides a semiconductor memory comprising:
the semiconductor contact structure as described in the first aspect.
A fourth aspect of the present disclosure provides an electronic device, comprising:
the semiconductor memory as described in the third aspect.
This disclosure compares advantage with prior art and lies in:
(1) according to the semiconductor contact structure, a photoetching alignment process is not needed, the contact position is located in the center of the two insulators, and the defects caused by electric leakage are prevented.
(2) The semiconductor contact structure provided by the disclosure reduces the area in relative contact with the bit line, and can reduce the capacitance of the bit line.
(3) The semiconductor contact structure provided by the disclosure can increase a process window adjacent to the active region by virtue of a side wall process of the contact structure.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1A illustrates a plan view of a prior art semiconductor contact structure;
FIG. 1B shows a cross-sectional view taken along lines a-a 'and B-B' of FIG. 1A;
fig. 2A illustrates a plan view of a semiconductor contact structure provided by the present disclosure;
FIG. 2B shows a cross-sectional view taken along lines a-a 'and B-B' of FIG. 2A;
fig. 3 shows a flow chart of a method of fabricating a semiconductor contact structure provided by the present disclosure;
fig. 4 to 6 are schematic cross-sectional views of the device structure in the method for manufacturing the semiconductor contact structure shown in fig. 3.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to solve the problems in the prior art, embodiments of the present disclosure provide a semiconductor contact structure and a method for manufacturing the same, a semiconductor memory and an electronic device, which are described below with reference to the accompanying drawings.
Fig. 2A illustrates a plan view of a semiconductor contact structure provided by the present disclosure. Fig. 2B shows a cross-sectional view taken along lines a-a 'and B-B' of fig. 2A. Wherein, the left drawing c in fig. 2A is a plan view horizontally taken along the line c in fig. 2B, and the right drawing c 'is a plan view horizontally taken along the line c' in fig. 2B. As shown in fig. 2A and 2B, the semiconductor contact structure includes: a semiconductor substrate 100, a buried gate structure 200, and a contact structure 300, a bit line may be formed on the upper portion of the contact structure 300, and the contact structure 300 may function to connect the upper bit line and the lower active region 120.
Specifically, the semiconductor substrate 100 includes an active region 120 defined by a device isolation region 110, a buried gate structure 200 formed in the semiconductor substrate 100; and a contact structure 300 formed between the buried gate structures 200. Wherein the contact structure 300 is self-aligned with the buried gate structure 200.
Specifically, the contact structure 300 is wide at the top and narrow at the bottom, and includes a contact sidewall 310 and a contact plug 320, where the contact sidewall 310 includes a first contact sidewall 311 located above and a second contact sidewall 312 located below. Specifically, the contact plug 320 is formed in the space surrounded by the contact sidewall 310. Since the contact structure 300 is wide at the top and narrow at the bottom, the contact plug 320 therein is smaller than that in the prior art, so that the area of the contact with the bit line is reduced, and the bit line capacitance can be reduced.
In some embodiments of the present disclosure, the specific material of the contact plug 320 may be polysilicon, and the specific material of the contact sidewall 310 may be silicon nitride.
In some embodiments of the present disclosure, the buried gate structure 200 may include: a gate dielectric layer 210 (e.g., a silicon oxide material), a gate electrode layer 230 (e.g., a metal tungsten material), and a gate mask layer 240 (e.g., a silicon nitride material) are stacked, but a gate blocking layer 220 (e.g., a titanium nitride material) may also be included and disposed between the gate electrode layer 230 and the gate dielectric layer 210. Specifically, the buried gate structure 200 includes a gate dielectric layer 210 located on the outer side, a gate electrode layer 230 located below and surrounded by the gate dielectric layer 210, and a gate mask layer 240 located above, the first contact sidewall 311 is formed on the outer side of the gate mask layer 240, and the second contact sidewall 312 is formed on the outer side of the gate dielectric layer 210.
In some embodiments of the present disclosure, as shown in fig. 2B, the gate mask layer 240 is flush with the top surface of the contact plug 320.
In some embodiments of the present disclosure, the active region 120 comprises a first material, the gate dielectric layer 210 comprises a second material, and the etching selectivity of the first material and the etching selectivity of the second material are different, that is, the gate dielectric layer 210 may be selectively etched first, and then the active region 120 may be selectively etched. Specifically, the first material may be a silicon material, and the second material may be a silicon oxide material.
Compared with the prior art, the semiconductor contact structure provided by the disclosure does not need to adopt a photoetching alignment process, and the contact position is in the central position of the two insulators, so that the defect caused by electric leakage is prevented. The contact area with respect to the bit line is reduced, and the bit line capacitance can be reduced. By means of the side wall process of the contact structure, a process window adjacent to the active region can be increased.
The present disclosure also provides a method for manufacturing a semiconductor contact structure, which is used for manufacturing the semiconductor contact structure in the above embodiments. As shown in fig. 3, the method comprises the steps of:
step S101: a semiconductor substrate is provided.
Referring to fig. 4, the semiconductor substrate 100 includes an active region 120 defined by a device isolation region 110, and a buried gate structure 200 formed in the semiconductor substrate 100, where the buried gate structure 200 includes a gate dielectric layer 210 (e.g., a silicon oxide material), a gate electrode layer 230 (e.g., a metal tungsten material), and a gate mask layer 240 (e.g., a silicon nitride material), which are stacked, and of course, a gate blocking layer 220 (e.g., a titanium nitride material) disposed between the gate electrode layer 230 and the gate dielectric layer 210. Specifically, the buried gate structure 200 includes a gate dielectric layer 210 located on the outer side, a gate electrode layer 230 located below and surrounded by the gate dielectric layer 210, and a gate mask layer 240 located above, the first contact sidewall 311 is formed on the outer side of the gate mask layer 240, and the second contact sidewall 312 is formed on the outer side of the gate dielectric layer 210.
In some embodiments of the present disclosure, the active region 120 comprises a first material, the gate dielectric layer 210 comprises a second material, and the etching selectivity of the first material and the etching selectivity of the second material are different, that is, the gate dielectric layer 210 may be selectively etched first, and then the active region 120 may be selectively etched. Specifically, the first material may be a silicon material, and the second material may be a silicon oxide material.
Step S102: and carrying out first selective etching on the semiconductor substrate between the buried gate structures to form a contact hole exposing the surface of the active region.
With continued reference to fig. 4, under the protection of the mask 400, the semiconductor substrate 100 is selectively etched for the first time between the buried gate structures 200, the interlayer dielectric layer (not shown) between the buried gate structures 200 and the upper portion of the gate dielectric layer 210 in the buried gate structure 200 are removed by the selective etching, and a contact hole a exposing the surface of the active region 120 is formed.
Step S103: and performing second selective etching on the semiconductor substrate downwards aiming at the contact hole to form a contact groove, wherein the area of the bottom surface of the contact hole is larger than that of the top surface of the contact groove.
Referring to fig. 5, on the basis of the first selective etching, a second selective etching is performed on the semiconductor substrate 100 downward with respect to the contact hole a, taking the gate dielectric layer 210 remaining in the buried gate structures 200 as a reference, and the active region 120 between the buried gate structures 200 is selectively etched downward, so as to form a contact groove B between the buried gate structures 200, wherein the area of the bottom surface of the contact hole a is larger than the area of the top surface of the contact groove B in contact therewith, as shown in the figure.
Step S104: and forming a second contact side wall on the side wall of the contact groove, and forming a first contact side wall on the side wall of the contact hole.
Referring to fig. 6, second contact spacers 312 are formed on the sidewalls of the contact grooves B, and first contact spacers 311 are formed on the sidewalls of the contact holes a.
Step S105: a contact plug 320 is formed in a space surrounded by the first contact sidewall 311 and the second contact sidewall 312.
On the basis of the structure shown in fig. 6, polysilicon is deposited to form the contact plug 320 at a time, and then the excessive polysilicon outside the contact hole is removed by an etch-back process, so that the top surfaces of the contact plug 320 and the gate mask layer 240 are flush, thereby forming the structure shown in fig. 2B.
Compared with the prior art, the semiconductor contact structure manufactured by the method does not need a photoetching alignment process, and the contact position is in the central position of the two insulators, so that the defects caused by electric leakage are prevented. The contact area with respect to the bit line is reduced, and the bit line capacitance can be reduced. By means of the side wall process of the contact structure, a process window adjacent to the active region can be increased.
The embodiment of the present disclosure also provides a semiconductor memory, which includes the semiconductor contact structure described in the above embodiment, and the semiconductor memory may be, for example, a semiconductor memory such as a DRAM.
As shown in fig. 2A and 2B, the semiconductor contact structure includes: a semiconductor substrate 100, a buried gate structure 200, and a contact structure 300, a bit line may be formed on the upper portion of the contact structure 300, and the contact structure 300 may function to connect the upper bit line and the lower active region 120.
Specifically, the semiconductor substrate 100 includes an active region 120 defined by a device isolation region 110, a buried gate structure 200 formed in the semiconductor substrate 100; and a contact structure 300 formed between the buried gate structures 200. Wherein the contact structure 300 is self-aligned with the buried gate structure 200.
Specifically, the contact structure 300 is wide at the top and narrow at the bottom, and includes a contact sidewall 310 and a contact plug 320, where the contact sidewall 310 includes a first contact sidewall 311 located above and a second contact sidewall 312 located below. Specifically, the contact plug 320 is formed in the space surrounded by the contact sidewall 310. Since the contact structure 300 is wide at the top and narrow at the bottom, the contact plug 320 therein is smaller than that in the prior art, so that the area of the contact with the bit line is reduced, and the bit line capacitance can be reduced.
In some embodiments of the present disclosure, the specific material of the contact plug 320 may be polysilicon, and the specific material of the contact sidewall 310 may be silicon nitride.
In some embodiments of the present disclosure, the buried gate structure 200 may include: a gate dielectric layer 210 (e.g., a silicon oxide material), a gate electrode layer 230 (e.g., a metal tungsten material), and a gate mask layer 240 (e.g., a silicon nitride material) are stacked, but a gate blocking layer 220 (e.g., a titanium nitride material) may also be included and disposed between the gate electrode layer 230 and the gate dielectric layer 210. Specifically, the buried gate structure 200 includes a gate dielectric layer 210 located on the outer side, a gate electrode layer 230 located below and surrounded by the gate dielectric layer 210, and a gate mask layer 240 located above, the first contact sidewall 311 is formed on the outer side of the gate mask layer 240, and the second contact sidewall 312 is formed on the outer side of the gate dielectric layer 210.
In some embodiments of the present disclosure, as shown in fig. 2B, the gate mask layer 240 is flush with the top surface of the contact plug 320.
In some embodiments of the present disclosure, the active region 120 comprises a first material, the gate dielectric layer 210 comprises a second material, and the etching selectivity of the first material and the etching selectivity of the second material are different, that is, the gate dielectric layer 210 may be selectively etched first, and then the active region 120 may be selectively etched. Specifically, the first material may be a silicon material, and the second material may be a silicon oxide material.
The embodiment of the present disclosure also provides an electronic device, which includes the semiconductor memory in the above embodiment. The electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, or a mobile power source.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (14)
1. A semiconductor contact structure, comprising:
a semiconductor substrate;
an active region defined by the device isolation region;
a buried gate structure formed in the semiconductor substrate; and
a contact structure formed between the buried gate structures;
wherein the contact structure is self-aligned with the buried gate structure.
2. The semiconductor contact structure of claim 1, wherein the contact structure is wide at the top and narrow at the bottom and comprises a contact sidewall and a contact plug, and the contact sidewall comprises a first contact sidewall located above and a second contact sidewall located below.
3. The semiconductor contact structure of claim 2, wherein the buried gate structure comprises:
the gate structure comprises a gate dielectric layer positioned on the outer side, a gate electrode layer positioned below and a gate mask layer positioned above, wherein the gate dielectric layer is surrounded by the gate dielectric layer, the first contact side wall is formed on the outer side of the gate mask layer, the second contact side wall is formed on the outer side of the gate dielectric layer, and the side surface of the gate mask layer except the part in contact with the second contact side wall is surrounded by the gate dielectric layer.
4. The semiconductor contact structure of claim 3, wherein the gate mask layer is flush with a top surface of the contact plug.
5. The semiconductor contact structure of claim 4, wherein the active region comprises a first material and the gate dielectric layer comprises a second material, and wherein the first material and the second material have different etch selectivities.
6. The semiconductor contact structure of claim 5, wherein the first material is silicon and the second material is silicon oxide.
7. A method for fabricating a semiconductor contact structure, comprising:
providing a semiconductor substrate; the semiconductor substrate comprises an active region defined by a device isolation region and a buried gate structure formed in the semiconductor substrate;
carrying out first selective etching on the semiconductor substrate between the buried gate structures to form a contact hole exposing the surface of the active region;
performing second selective etching on the semiconductor substrate downwards aiming at the contact hole to form a contact groove, wherein the area of the bottom surface of the contact hole is larger than that of the top surface of the contact groove;
forming a second contact side wall on the side wall of the contact groove, and forming a first contact side wall on the side wall of the contact hole;
and forming a contact plug in a space surrounded by the first contact side wall and the second contact side wall.
8. The method according to claim 7, wherein the buried gate structure comprises a gate dielectric layer at the outer side, a gate electrode layer at the lower side surrounded by the gate dielectric layer, and a gate mask layer at the upper side.
9. The method of claim 8, wherein the step of performing the first selective etching to form the contact hole comprises:
and selectively etching to remove the interlayer dielectric layer between the buried gate structures and the upper side part of the gate dielectric layer in the buried gate structures.
10. The method of claim 9, wherein the step of performing the second selective etch to form the contact recess comprises:
and aiming at the contact hole, taking the residual gate dielectric layer in the buried gate structure as a reference, and etching the active region between the buried gate structures downwards.
11. The method of claim 8, wherein the gate mask layer is flush with a top surface of the contact plug.
12. A semiconductor memory, comprising:
the semiconductor contact structure of any of claims 1 to 6.
13. An electronic device, comprising:
the semiconductor memory according to claim 12.
14. The electronic device of claim 13, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010702155.5A CN113964124A (en) | 2020-07-21 | 2020-07-21 | Semiconductor contact structure, manufacturing method thereof and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010702155.5A CN113964124A (en) | 2020-07-21 | 2020-07-21 | Semiconductor contact structure, manufacturing method thereof and semiconductor memory |
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| Publication Number | Publication Date |
|---|---|
| CN113964124A true CN113964124A (en) | 2022-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010702155.5A Pending CN113964124A (en) | 2020-07-21 | 2020-07-21 | Semiconductor contact structure, manufacturing method thereof and semiconductor memory |
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| Country | Link |
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| CN (1) | CN113964124A (en) |
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- 2020-07-21 CN CN202010702155.5A patent/CN113964124A/en active Pending
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