CN113920936B - Signal monitoring circuit, display control circuit and display device - Google Patents
Signal monitoring circuit, display control circuit and display device Download PDFInfo
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- CN113920936B CN113920936B CN202111212139.9A CN202111212139A CN113920936B CN 113920936 B CN113920936 B CN 113920936B CN 202111212139 A CN202111212139 A CN 202111212139A CN 113920936 B CN113920936 B CN 113920936B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 250
- 230000002159 abnormal effect Effects 0.000 claims abstract description 73
- 230000000087 stabilizing effect Effects 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000005070 sampling Methods 0.000 claims description 3
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- 230000003139 buffering effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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Abstract
The application discloses a signal monitoring circuit, display control circuit and display device relates to and shows technical field, can monitor multichannel drive signal. A signal monitoring circuit comprising: the display driving system comprises at least two input modules, a display driving module and a display driving module, wherein the input modules are used for accessing display driving signals to be monitored to form monitoring electric signals, and the monitoring electric signals are used for indicating abnormal states of the display driving signals to be monitored; the control module is electrically connected with all the input modules and is used for outputting an abnormal monitoring result when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state.
Description
Technical Field
The application relates to the technical field of display, in particular to a signal monitoring circuit, a display control circuit and a display device.
Background
Currently, in the field of display technology, it is required to monitor whether driving signals of various power supplies for driving a display panel are normal. For example, when the power-off operation is performed, the anode driving power is turned off first, and when it is monitored that the power-off operation is performed, the black screen operation is performed, and it is also necessary to monitor whether the clock low level signal is normal or not to confirm whether the driving inside the screen is normal or not. In other cases, it is also necessary to monitor other types of signals to confirm whether the driving signal input into the display panel is normal or not, so as to ensure the normal display of the display panel.
However, current monitoring chips are generally used for monitoring the driving signals, and the current monitoring chips monitor the current of the driving signals, but it is difficult for the current monitoring chips to monitor whether the state of the multipath driving signals is normal.
Disclosure of Invention
The embodiment of the application provides a signal monitoring circuit, a display control circuit and a display device, which can monitor multipath driving signals.
In a first aspect of embodiments of the present application, there is provided a signal monitoring circuit, including:
the display driving system comprises at least two input modules, a display driving module and a display driving module, wherein the input modules are used for accessing display driving signals to be monitored to form monitoring electric signals, and the monitoring electric signals are used for indicating abnormal states of the display driving signals to be monitored;
the control module is electrically connected with all the input modules and is used for outputting an abnormal monitoring result when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state.
In some embodiments, the control module includes a first switching device;
the monitoring electric signals received by the control module are used for controlling the first switching device to be turned on or turned off, so that the control module outputs the abnormal monitoring result when at least one display driving signal to be monitored corresponding to the monitoring electric signals is in an abnormal state.
In some embodiments, the first switching device is configured to be turned on or turned off when the display driving signals to be monitored corresponding to all the received monitoring electrical signals are in a normal state, and the first switching device is configured to be turned off or turned on when the display driving signals to be monitored corresponding to at least one monitoring electrical signal are received to be in an abnormal state.
In some embodiments, the control module includes an output unit;
the first end of the first switching device is used for being connected with constant voltage, the second end of the first switching device is electrically connected with all the input modules, the third end of the first switching device is electrically connected with the output unit, and the first switching device is used for conducting the first end and the third end when being started.
In some embodiments, the first switching device includes a first MOS transistor, a gate of the first MOS transistor is electrically connected to all the input modules, a source of the first MOS transistor is used for grounding, and a drain of the first MOS transistor is electrically connected to the output unit.
In some embodiments, the output unit includes a first voltage division unit, one end of which is used for accessing a constant power supply voltage, and the other end of which is electrically connected to the third end of the first switching device.
In some embodiments, the output unit further includes a voltage stabilizing device, one end of the voltage stabilizing device is electrically connected to one end of the first voltage dividing unit connected to the constant power voltage, and the other end of the voltage stabilizing device is electrically connected to the first end. In some embodiments, the device further comprises a voltage buffer unit disposed between the input module and the control module;
the voltage buffer unit comprises a capacitor and a resistor which are connected in parallel.
In some embodiments, the number of input modules is three, the display driving signal to be monitored includes a power driving signal and an external system state signal, and the power driving signal includes at least one of an anode driving signal, a clock high level signal and a clock low level signal, where each input module is used for accessing one display driving signal to be monitored.
In some embodiments, at least one of the input modules comprises a second switching device;
the display driving signal to be monitored, which is accessed by the input module, is used for controlling the second switching device to be turned on or turned off.
In some embodiments, the input module for accessing the clock low level signal includes a second voltage division unit and the second switching device, one end of the second voltage division unit is used for accessing a constant power supply voltage, and the other end of the second voltage division unit is electrically connected with the second switching device.
In some embodiments, the second voltage dividing unit includes two resistors, two resistors are connected in series, one resistor is used for connecting the clock low level signal, and the other resistor is used for connecting the constant voltage source voltage;
the second switching device is connected between the two resistors.
In some embodiments, the input module for accessing the anode driving signal includes a third voltage dividing unit having one end for accessing the anode driving signal and the other end for connecting to the control module.
In some embodiments, the second switching device includes a second MOS transistor, a gate of the second MOS transistor is used for accessing the display driving signal to be monitored, a source of the second MOS transistor is used for grounding, and a drain of the second MOS transistor is electrically connected with the control module.
In a second aspect of embodiments of the present application, there is provided a display control circuit including:
the signal monitoring circuit of the first aspect;
the driving control circuit is electrically connected with the signal monitoring circuit and is used for adjusting the current display driving signal under the condition that the signal monitoring circuit outputs an abnormal monitoring result.
In some implementations, the display control circuit provided in the embodiments of the present application further includes:
the power management chip is used for being connected with a main board power supply, and is electrically connected with the drive control circuit and the signal monitoring circuit respectively;
the signal monitoring circuit is used for sampling and monitoring the power supply driving signal through the power supply management chip.
In a third aspect provided by an embodiment of the present application, there is provided a display device, including:
the display control circuit according to the second aspect;
and the display panel is electrically connected with the display control circuit.
According to the signal monitoring circuit, the display control circuit and the display device, at least two input modules are arranged to be electrically connected with the control module together, each input module is used for being connected with a display driving signal to be monitored to form a monitoring electric signal, and the monitoring electric signal is used for indicating an abnormal state of the display driving signal to be monitored; and outputting an abnormal monitoring result when the display driving signal to be monitored corresponding to the at least one monitoring electric signal is in an abnormal state through the setting control module. The control module is electrically connected with at least two input modules, and when at least one monitoring electric signal is in an abnormal state, the control module outputs an abnormal monitoring structure, so that a plurality of display driving signals to be monitored can be monitored simultaneously. The signal monitoring circuit that this embodiment provided adopts integrated circuit's form to replace the current monitoring chip, a signal monitoring circuit's integrated circuit can realize monitoring at least two kinds simultaneously and wait to monitor the drive signal, can monitor two way at least display drive signal simultaneously promptly, on realizing the basis to multichannel drive signal monitoring, can save the use of current monitoring chip, practice thrift the cost, and signal monitoring circuit's simple structure, easy realization, device low cost is great to the scope of the monitoring of display drive signal, the monitoring effect is stronger.
Drawings
FIG. 1 is a schematic block diagram of a signal monitoring circuit according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of another signal monitoring circuit according to an embodiment of the present application;
FIG. 3 is a schematic block diagram of a signal monitoring circuit according to an embodiment of the present application;
FIG. 4 is a schematic block diagram of a signal monitoring circuit according to an embodiment of the present application;
FIG. 5 is a schematic block diagram of a display control circuit according to an embodiment of the present application;
FIG. 6 is a schematic block diagram of another display control circuit provided in an embodiment of the present application;
fig. 7 is a schematic block diagram of a display device according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the following detailed description of the technical solutions of the embodiments of the present specification is made through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more cases.
Currently, in the field of display technology, it is required to monitor whether driving signals of various power supplies for driving a display panel are normal. For example, when the power-off operation is performed, the anode driving power is turned off first, and when it is monitored that the power-off operation is performed, the black screen operation is performed, and it is also necessary to monitor whether the clock low level signal is normal or not to confirm whether the driving inside the screen is normal or not. In other cases, it is also necessary to monitor other types of signals to confirm whether the driving signal input into the display panel is normal or not, so as to ensure the normal display of the display panel. However, current monitoring chips are generally used for monitoring the driving signals, and the current monitoring chips monitor the current of the driving signals, but it is difficult for the current monitoring chips to monitor whether the state of the multipath driving signals is normal.
In view of this, the embodiments of the present application provide a signal monitoring circuit, a display control circuit, and a display device, which are capable of monitoring a multi-path driving signal.
In a first aspect of the embodiments of the present application, a signal monitoring circuit is provided, and fig. 1 is a schematic block diagram of a signal monitoring circuit provided in an embodiment of the present application. As shown in fig. 1, a signal monitoring circuit provided in an embodiment of the present application includes: the display driving signal to be monitored is connected to the input module 100 to form a monitoring electric signal, and the monitoring electric signal is used for indicating the abnormal state of the display driving signal to be monitored; the control module 200 is electrically connected to all the input modules 100, and the control module 200 is configured to output an abnormal monitoring result when the display driving signal to be monitored corresponding to the at least one monitoring electrical signal is in an abnormal state.
As shown in fig. 1, the signal monitoring circuit includes three input modules 100, and the input terminals 110 of the three input modules 100 may be used to respectively access the first display driving signal to be monitored S1, the second display driving signal to be monitored S2, and the third display driving signal to be monitored S3. The output ends 120 of the three input modules 100 are connected together to form a common potential point, the first display driving signal S1 to be monitored passes through the corresponding input module 100 to be connected to form a first monitoring electric signal TS1, the second display driving signal S2 to be monitored passes through the corresponding input module 100 to be connected to form a second monitoring electric signal TS2, the third display driving signal S3 to be monitored passes through the corresponding input module 100 to be connected to form a third monitoring electric signal TS3, the first monitoring electric signal TS1, the second monitoring electric signal TS2 and the third monitoring electric signal TS3 form an integrated monitoring electric signal TS at the common potential point, the integrated monitoring electric signal TS at the common potential point can be used as an input signal of the control module 200, and the integrated monitoring electric signal TS can generate a monitoring result RS after passing through the control module 200. It is easy to understand that the three input modules 100 are commonly connected to a common potential point, if the display driving signal to be monitored, which is connected to any one of the input modules 100, is in an abnormal state, the integrated monitoring electrical signal TS formed at the common potential point is in an abnormal state, and if the display driving signals to be monitored, which are connected to all of the input modules 100, are in a normal state, the integrated monitoring electrical signal TS formed at the common potential point is in a normal state. If the control module 200 receives the integrated monitoring electric signal TS of the normal state of the common potential point, a normal monitoring result RS is output, and if the control module 200 receives the integrated monitoring electric signal TS of the abnormal state of the common potential point, an abnormal monitoring result RS is output. Whether the state to current monitoring chip is difficult to monitor multichannel drive signal is normal, the signal monitoring circuit that this application embodiment provided adopts integrated circuit's form to replace current monitoring chip, the integrated circuit of a signal monitoring circuit can realize monitoring simultaneously at least two kinds of display drive signals that wait to monitor, can monitor two way at least display drive signals promptly simultaneously, on the basis of realizing monitoring multichannel drive signal, can save the use of current monitoring chip, save the cost, and signal monitoring circuit's simple structure, easy realization, device low cost is great to the scope of the monitoring of display drive signal, the monitoring effect is stronger.
It should be noted that the number of the input modules 100 shown in fig. 1 is 3, which is merely illustrative and not a specific limitation of the embodiments of the present application.
According to the signal monitoring circuit provided by the embodiment of the application, at least two input modules 100 are arranged to be electrically connected with the control module 200 together, each input module 100 is used for being connected with a display driving signal to be monitored to form a monitoring electric signal, and the monitoring electric signal is used for indicating the abnormal state of the display driving signal to be monitored; and outputting an abnormal monitoring result by setting the control module 200 when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state. The control module 200 is electrically connected to at least two input modules 100, and when at least one monitoring electric signal is in an abnormal state, the control module 200 outputs an abnormal monitoring structure, so that a plurality of display driving signals to be monitored can be monitored simultaneously. The signal monitoring circuit that this embodiment provided adopts integrated circuit's form to replace the current monitoring chip, a signal monitoring circuit's integrated circuit can realize monitoring at least two kinds simultaneously and wait to monitor the drive signal, can monitor two way at least display drive signal simultaneously promptly, on realizing the basis to multichannel drive signal monitoring, can save the use of current monitoring chip, practice thrift the cost, and signal monitoring circuit's simple structure, easy realization, device low cost is great to the scope of the monitoring of display drive signal, the monitoring effect is stronger.
In some embodiments, the control module includes a first switching device; the monitoring electric signals received by the control module are used for controlling the first switching device to be turned on or turned off, so that the control module outputs an abnormal monitoring result when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state.
In some embodiments, the first switching device is configured to be turned on or turned off when all the display driving signals to be monitored corresponding to the received monitoring electrical signals are in a normal state, and the first switching device is configured to be turned off or turned on when at least one display driving signal to be monitored corresponding to the received monitoring electrical signals is in an abnormal state.
For example, with continued reference to fig. 1, when at least one display driving signal to be monitored is in an abnormal state, the monitoring electric signal formed correspondingly is in an abnormal state, and then the integrated monitoring electric signal TS formed at the common potential point is in an abnormal state, and the integrated monitoring electric signal TS in the abnormal state can control the first switching device to be turned off; when all the display driving signals to be monitored are in a normal state, all the corresponding monitoring electric signals are in a normal state, the integrated monitoring electric signals TS formed at the common potential point are in a normal state, and the integrated monitoring electric signals TS in the normal state can control the first switching device to be turned on. On the contrary, for example, the normal integrated monitoring electrical signal TS can control the first switching device to be turned off, and the abnormal integrated monitoring electrical signal TS can control the first switching device to be turned on, which is not limited in the embodiment of the present application. The on and off of the first switching device may enable the control module 200 to output different electrical signals, where the different electrical signals output by the first switching device in the on or off state may be used as a normal monitoring result or an abnormal monitoring result, for example, when the first switching device is on, the control module 200 correspondingly outputs the normal monitoring result, when the first switching device is off, the control module 200 correspondingly outputs the abnormal monitoring result, or when the first switching device is off, the control module 200 correspondingly outputs the normal monitoring result, and when the first switching device is on, the control module 200 correspondingly outputs the abnormal monitoring result.
According to the signal monitoring circuit provided by the embodiment of the application, the first switching device is arranged in the control module 200, and the first switching device can be controlled to be turned on or turned off by the monitoring electric signal so as to control the control module 200 to output different electric signals to represent different monitoring results, and finally, the abnormal monitoring results are output when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state. The switch characteristics of the switch device are utilized to realize that the control module outputs different monitoring results under the condition of inputting monitoring electric signals in different states, so that the monitoring of the multi-channel display driving signals to be monitored can be easily realized, the switch device is a common electronic component, the cost is low, and the circuit structure is simple.
In some embodiments, the control module includes an output unit; the first end of the first switching device is used for being connected with constant voltage, the second end of the first switching device is electrically connected with all input modules, the third end of the first switching device is electrically connected with the output unit, and the first switching device is used for conducting the first end and the third end when the first switching device is started.
Fig. 2 is a schematic block diagram of another signal monitoring circuit according to an embodiment of the present application. As shown in fig. 2, the control module 200 includes an output unit 220; the first terminal 211 of the first switching device 210 is used for connecting the constant voltage V1, the second terminal 212 of the first switching device 210 is electrically connected with all the input modules 100, the third terminal 213 of the first switching device 200 is electrically connected with the output unit 220, and the first switching device 210 is used for conducting the first terminal 211 and the third terminal 213 when being turned on. When the first switching device 210 is turned on under the control of the monitoring electric signal, the first end 211 and the third end 213 are turned on, the monitoring result RS output by the output unit 220 is affected by the constant voltage V1, and when the first switching device 210 is turned off under the control of the monitoring electric signal, the first end 211 and the third end 213 are not turned on, the monitoring result RS output by the output unit 220 is affected only by the internal structure of the output unit 220, so that the on and off of the first switching device 210 can control the output unit 220 to output different monitoring results. The monitoring result may be an electrical signal, such as a voltage or a current, and is not particularly limited in this application.
According to the signal monitoring circuit provided by the embodiment of the application, different monitoring results can be output through the opening and closing control output unit 220 of the first switching device 210 by setting the three-terminal connection mode of the output unit 220 and the first switching device 210, the circuit is easy to realize, the circuit structure is simple, and the cost is low.
In some embodiments, the first switching device includes a first MOS transistor, a gate of the first MOS transistor is electrically connected to all the input modules, a source of the first MOS transistor is used for grounding, and a drain of the first MOS transistor is electrically connected to the output unit. The MOS transistor is a relatively common switching device, and is widely used, and the source of the first MOS transistor may be used for grounding, and then the constant voltage V1 may be a grounding voltage. The first MOS tube can be a metal oxide field effect tube, and has low cost, easy realization and mature device performance.
According to the signal monitoring circuit provided by the embodiment of the application, the MOS tube is used as the first switching device, the MOS tube is a common switching device, whether the source electrode and the drain electrode of the first MOS tube are conducted or not can be controlled by inputting monitoring electric signals to the grid electrode of the first MOS tube, the source electrode of the first MOS tube is grounded, constant potential (0V) can be kept all the time for the source electrode of the first MOS tube, when the first MOS tube is closed, the output of the output unit is controlled by the circuit structure in the output unit, when the first MOS tube is opened, the monitoring result output by the output unit is 0V or a value approximate to 0V, the control of the monitoring electric signals to the first MOS tube is easy to realize, and the synchronous monitoring of the signal monitoring circuit to a plurality of display driving signals to be monitored is further realized.
In some implementations, fig. 3 is a schematic block diagram of still another signal monitoring circuit provided in an embodiment of the present application. As shown in fig. 3, the output unit 220 includes a first voltage division unit, one end of which is used for accessing a constant power voltage, and the other end of which is electrically connected to a third end of the first switching device. The constant power supply voltage may be a main board power supply voltage VDD, one end of the second resistor R2 of the first voltage dividing unit may be electrically connected to the drain d of the first MOS transistor, the other end of the second resistor R2 of the third resistor R3 is used as an Output end Output of the Output unit 220, one end of the third resistor R3 is electrically connected to the drain d of the first MOS transistor, the other end of the third resistor R3 is connected to the main board power supply voltage VDD, the main board power supply voltage VDD is a constant and stable voltage, the second resistor R2 and the third resistor R3 both play a role in voltage division, and when the first MOS transistor is turned off, after the second resistor R2 and the third resistor R3 divide the main board power supply voltage VDD, the divided voltage is not excessively outputted from the Output end Output so as to satisfy the Output monitoring result and be represented by a small voltage value, so as to play a role in voltage protection for a circuit or a device for reading the Output voltage.
In some embodiments, the output unit 220 further includes a voltage stabilizing device D1, where one end of the voltage stabilizing device D1 is electrically connected to one end of the first voltage dividing unit connected to the constant power voltage, and the other end is electrically connected to the first end. It should be noted that the voltage stabilizing device D1 may be a voltage stabilizing diode, and a cathode of the voltage stabilizing diode is used for being connected to the motherboard power supply voltage VDD. The zener diode is a commonly used zener device, and the zener device D1 can play the role of overvoltage protection, can avoid the condition that overvoltage burns out when the voltage received by the grid G of the first MOS tube is too high, can also carry out overvoltage protection to the first MOS tube when the voltage of the main board power supply voltage VDD is too high, and prevents the damage device caused by the too high main board power supply voltage VDD. The output unit 220 may further include a first capacitor C1 and a first resistor R1, where the first capacitor C1 is connected in parallel with the first switching device M1, and the first resistor R1 is connected in parallel with the first switching device M1, and the provision of the first capacitor C1 and the first resistor R1 can prevent erroneous output due to voltage jitter, and the voltage stabilizing device D1, the first capacitor C1, and the first resistor R1 all protect the first switching device M1 from overvoltage and voltage jitter.
According to the signal monitoring circuit provided by the embodiment of the application, the voltage stabilizing device D1 can play a role in overvoltage protection, overvoltage burning-out can be avoided when the voltage received by the grid electrode G of the first MOS tube is too high, and the first capacitor C1 and the first resistor R1 also play a role in protecting the overvoltage and the jitter of the first switching device M1.
For example, with continued reference to fig. 3, when the first MOS transistor is turned on by the monitoring electric signal through the gate G of the first MOS transistor, the source S and the drain d of the first MOS transistor are turned on, the drain d terminal also becomes the ground voltage, the voltage of the drain d is 0V, and the Output of the Output unit 220 is 0V. When the first MOS transistor is turned off by the monitoring electric signal through the gate G of the first MOS transistor, the source S and the drain d of the first MOS transistor are not turned on, the voltage at the drain d end is the divided voltage of the third resistor R3, the divided voltage of the third resistor R3 is the main board power supply voltage VDD, and the voltage Output by the Output end Output of the Output unit 220 is the voltage divided by the second resistor R2, so when the first MOS transistor is turned off, the Output end Output is determined by the main board power supply voltage VDD, the resistance values of the second resistor R2 and the third resistor R3, that is, the voltage Output by the Output end Output is not 0V. It is easy to understand that the resistance values of the second resistor R2 and the third resistor R3 can be reversely deduced according to the main board power supply voltage VDD and the voltage Output range allowed by the Output terminal Output.
According to the signal monitoring circuit, the output voltage value of the output end when the first MOS tube is closed is determined by setting the first voltage dividing unit, so that the output voltage values of the output unit when the first MOS tube is opened and closed are different, and the abnormal monitoring result is output when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state. The control module outputs different monitoring results under the condition of inputting monitoring electric signals in different states by utilizing the switching characteristics of the switching device, so that the cost is low and the circuit structure is simple.
In some embodiments, the number of input modules is three, the display driving signal to be monitored includes a power driving signal and an external system state signal, and the power driving signal includes an anode driving signal and a clock low level signal, where each input module is used for accessing one display driving signal to be monitored.
As shown in fig. 3, the number of input modules is at least three, and the display driving signal to be monitored includes a power driving signal and an external system state signal INF, where the power driving signal includes at least one of an anode driving signal ELVDD, a clock high level signal VGH, and a clock low level signal VGL, and each input module is used for accessing one display driving signal to be monitored. It should be noted that, the external system state signal INF may be a main board state signal for providing the display data driving signal, if the main board state signal of the display data driving signal is in an abnormal state, the external system state signal INF is 3.3V, and if the main board state signal of the display data driving signal is in a normal state, the external system state signal INF is 0. It is easy to understand that, in the display driving signal of the organic display panel, the anode driving signal ELVDD is used to drive the anode of the organic display panel, the clock low level signal VGL is used to provide the low level of the scan clock signal, the high level of the scan clock signal may be represented as the clock high level signal VGH, and the signal monitoring circuit provided in the embodiment of the present application may also monitor the clock high level signal VGH. It is to be readily understood that the clock high signal VGH and the clock low signal VGL are both used for accessing the scan signal lines of the organic display panel, and the INF may be a data signal line for providing a display data driving signal to access the organic display panel.
As illustrated in fig. 3, the input modules include a first input module 101, a second input module 102, and a third input module 103, wherein the first input module 101 is used for accessing the clock low level signal VGL, the second input module 102 is used for accessing the anode driving signal ELVDD, and the third input module 103 is used for accessing the external system state signal INF.
Illustratively, as shown in FIG. 3, at least one input module includes a second switching device M2; the display driving signal to be monitored, which is accessed by the input module, is used for controlling the second switching device M2 to be turned on or turned off. For example, an input module for accessing the clock low signal VGL and the external system state signal INF may include the second switching device M2. The clock low level signal VGL and the external system state signal INF may control the on or off of the corresponding second switching device M2, and the states of the clock low level signal VGL and the external system state signal INF may control the on or off of the corresponding second switching device M2. For example, the clock low level signal VGL in the normal state may control the second switching device M2 to be turned off, the clock low level signal VGL in the abnormal state may control the second switching device M2 to be turned on, the external system state signal INF in the normal state may control the second switching device M2 to be turned off, and the external system state signal INF in the abnormal state may control the second switching device M2 to be turned on, which is not a specific limitation of the embodiments of the present application. The second switching device M2 may be turned on or off to control the input module to form different monitoring electric signals, so as to generate the monitoring electric signal in the corresponding state by controlling the second switching device M2 to be turned on or off, and then the display driving signal to be monitored in the normal state corresponds to the monitoring electric signal in the normal state.
According to the signal monitoring circuit, the second switching device M2 is arranged in any input module, so that the monitoring electric signal in the corresponding state is generated by controlling the second switching device M2 to be turned on and off, and the display driving signal to be monitored in the normal state corresponds to the monitoring electric signal in the normal state. The integrated monitoring electric signals formed by corresponding to the display driving signals to be monitored in different states can be used for synchronously monitoring whether the states of the multipath display driving signals to be monitored are normal or not, the circuit logic is simple, the implementation is easy, the occupied area of the circuit is small, and the cost is low.
In some embodiments, the input module for accessing the clock low level signal includes a second voltage division unit and a second switching device, one end of the second voltage division unit is used for accessing the constant power voltage, and the other end of the second voltage division unit is electrically connected with the second switching device.
In some embodiments, the second switching device M2 may include a second MOS transistor, where a gate of the second MOS transistor is used for accessing a display driving signal to be monitored, a source of the second MOS transistor is used for grounding, and a drain of the second MOS transistor is electrically connected to the control module.
For example, with continued reference to fig. 3, the constant power supply voltage may be a main board power supply voltage VDD, the second voltage dividing unit may include a fifth resistor R5 and a sixth resistor R6, the fifth resistor R5 and the sixth resistor R6 are connected in series, the other end of the fifth resistor R5 is connected to the main board power supply voltage VDD, the other end of the sixth resistor R6 is connected to the clock low level signal VGL, the gate G of the second MOS transistor is connected between the fifth resistor R5 and the sixth resistor R6 through a seventh resistor R7, and the seventh resistor R7 may play a role of current limiting, so as to protect the gate G of the second MOS transistor from being broken down by a large current. The fourth capacitor C4 is disposed between the gate G and the source S of the second MOS transistor of the first input module 101, which can play a role in buffering, and the fourth capacitor C4 can prevent the gate G from being connected to a larger voltage to damage the second MOS transistor due to the grounding of the source S. The second input module 102 for accessing the anode driving signal ELVDD may include a third voltage dividing unit, where the third voltage dividing unit may include a voltage stabilizing device D1 and an eighth resistor R8, where the voltage stabilizing device D1 may play a role in voltage stabilizing and overvoltage protection, and the eighth resistor R8 may play a role in voltage dividing, which is also an overvoltage protection, so as to prevent the anode driving signal ELVDD from damaging a signal circuit due to too high voltage, and the voltage stabilizing device D1 may avoid misjudgment of the voltage jitter of the anode driving signal ELVDD. The third input module 103 may include a second MOS transistor and a ninth resistor R9, where one end of the ninth resistor R9 is connected to the gate G of the second MOS transistor, and the other end of the ninth resistor R9 is grounded, and the ninth resistor R9 is used as a pull-down resistor for protecting the second MOS transistor.
For example, if the second switching device is an NMOS, when the clock low level signal VGL is in an abnormal state, the clock low level signal VGL is typically 0V, the voltage of the gate G of the second MOS transistor is still in a high level through the voltage division voltage of the fifth resistor R5 and the seventh resistor R7 to the motherboard power supply voltage VDD, the corresponding second MOS transistor is turned on, the source S is turned on with the drain d, the drain d is grounded, the drain d of the corresponding second MOS transistor is used as the output end of the corresponding first input module 101, the output voltage is 0V, and the first monitoring electrical signal formed by the first input module 101 is 0V. When the clock low level signal VGL is in a normal state, the clock low level signal VGL is usually-5.5V, and then the voltage of the gate G of the second MOS transistor is pulled down by the clock low level signal VGL and is in a low level by the voltage division of the fifth resistor R5 and the sixth resistor R6, the corresponding second MOS transistor is turned off, the drain d of the corresponding second MOS transistor is used as the output end of the corresponding first input module 101, the output voltage is not 0, and the first monitoring electrical signal is not 0. The voltage division of the fifth resistor R5 and the sixth resistor R6 is used for ensuring that when the clock low level signal VGL is in a normal state, the divided voltage is lower than the opening voltage of the gate G of the second MOS transistor, so that when the clock low level signal VGL is in a normal state, the first MOS transistor is in a closed state. The resistance of the fifth resistor R5 and the seventh resistor R7 are determined by the normal value of the clock low level signal VGL, the main board power supply voltage VDD, and the turn-on voltage of the gate G of the second MOS transistor. The voltage division of the fifth resistor R5 and the sixth resistor R6 is also used for ensuring that the divided voltage is above the turn-on voltage of the gate G of the second MOS transistor when the clock low level signal VGL is in an abnormal state.
For example, the voltage range corresponding to the normal state of the anode driving signal ELVDD is 20-24V, the voltage corresponding to the abnormal state of the anode driving signal ELVDD is less than a voltage range, which may be 12-15V, for example, the voltage of the anode driving signal ELVDD in the abnormal state is less than 12V or less than 15V, etc., the voltage of the anode driving signal ELVDD in the abnormal state cannot turn on the first MOS transistor under the voltage division effect of the voltage stabilizing device D1 and the eighth resistor R8, that is, the voltage of the anode driving signal ELVDD in the abnormal state is less than the turn-on voltage of the first MOS transistor after the voltage division of the voltage stabilizing device D1 and the eighth resistor R8, and the corresponding second input module 102 outputs the voltage (greater than the turn-on voltage of the first MOS transistor) after the voltage division of the voltage stabilizing device D1 and the eighth resistor R8 when the anode driving signal ELVDD in the normal state is connected, and the corresponding second monitoring electric signal is not 0V but is less than the turn-on voltage of the first MOS transistor, and cannot turn on the first MOS transistor. The external system state signal INF in the abnormal state is 3.3V, the external system state signal INF in the normal state is 0V, when the corresponding third input module 103 is connected to the external system state signal INF in the normal state, the corresponding gate G of the second MOS transistor is connected to 0V, the second MOS transistor is closed, the source S and the drain d are not conducted, the drain d of the second MOS transistor serves as the output end of the third input module 103, the third monitoring electric signal output at this time is not 0V, when the corresponding third input module 103 is connected to the external system state signal INF in the abnormal state, the corresponding gate G of the second MOS transistor is connected to 3.3V, the second MOS transistor is opened, the voltage of the drain d is 0V, and the corresponding third monitoring electric signal is 0V. Therefore, when the first input module 101 is connected to the clock low-level signal VGL in the normal state, the first monitoring electric signal formed is not 0V, when the second input module 102 is connected to the anode driving signal ELVDD in the normal state, the second monitoring electric signal formed is the voltage (not 0) divided by the voltage stabilizing device D1 and the eighth resistor R8, when the third input module 103 is connected to the external system state signal INF in the normal state, the third monitoring electric signal formed is not 0V, the voltage corresponding to the first monitoring electric signal not 0V, the second monitoring electric signal is smaller than the starting voltage of the first MOS transistor, and the third monitoring electric signal not 0V is superposed at the common voltage point to form an integrated monitoring electric signal TS, the integrated monitoring electric signal TS at this time is superposition of three voltages, a high level can be formed, the first MOS transistor can be controlled to be turned on, the output voltage of the output unit is 0V at this time, the monitoring result is 0V, the driving signal to be displayed when the monitoring result is 0V represents that all the input modules are connected to the normal state, and the normal monitoring result can be represented by 0V. When any input module is connected with a display driving signal to be monitored in an abnormal state, the corresponding formed monitoring electric signal is 0V or smaller than the starting voltage of the first MOS tube, the electric potential of the common potential point is pulled down to 0V or smaller than the starting voltage of the first MOS tube, the first MOS tube cannot be started by the voltage corresponding to the integrated monitoring electric signal, the first MOS tube is in a closed state, the voltage output by the output unit is not 0V under the action of the first voltage dividing unit, for example, the voltage can be 3.3V, and the abnormal monitoring result can be represented by 3.3V. It should be noted that, when the anode driving signal ELVDD is in a normal state, the voltage of the eighth resistor R8 after dividing the anode driving signal ELVDD needs to be greater than the turn-on voltage of the first MOS transistor, and when the anode driving signal ELVDD is in an abnormal state, the voltage of the eighth resistor R8 after dividing the anode driving signal ELVDD needs to be less than the turn-on voltage of the first MOS transistor, that is, the resistance of the eighth resistor R8 is determined by the normal value range, the abnormal value range, and the turn-on voltage of the first MOS transistor of the anode driving signal ELVDD.
It should be noted that, the zener diode D0 is disposed between the source S and the drain D of the first MOS transistor and the second MOS transistor, the zener diode D0 may play a role in protection against breakdown, and the zener diode D0 has a voltage stabilizing effect, so that the corresponding MOS transistor may be prevented from breakdown due to overvoltage. The first MOS transistor and the second MOS transistor may be NMOS or PMOS, which are not specifically limited in the embodiment of the present application.
In some implementations, with continued reference to fig. 3, the signal monitoring points provided in the embodiments of the present application further include a voltage buffer unit 300, where the voltage buffer unit 300 is disposed between the input module and the control module.
Illustratively, with continued reference to fig. 3, one end of the voltage buffer unit 300 is configured to be grounded, and the other end of the buffer unit 300 is interposed between the input module 100 and the control module 200. The voltage buffer unit 300 may include a third capacitor C3 and a fourth resistor R4 connected in parallel, where one end of the voltage buffer unit 300 is grounded, and the other end is connected to a common potential point of all input modules, and is mainly also under the function of buffer protection, so that voltage division buffering can be performed when the voltage of the anode driving signal ELVDD is too high, so as to prevent the first MOS tube from being damaged by the too high voltage.
The signal monitoring circuit that this application embodiment provided through setting up a plurality of resistance and a plurality of electric capacity, can play the effect of partial pressure and steady voltage, can cushion too big voltage, avoids too big voltage to the damage of device.
Fig. 4 is a schematic block diagram of still another signal monitoring circuit according to an embodiment of the present application. As shown in fig. 4, the signal monitoring circuit provided in the embodiment of the present application may further include a fourth input module 104, where the fourth input module 104 is configured to access the clock high level signal VGH. The fourth input module 104 may include a third switching device M3, where the third switching device may include a third MOS transistor, the clock high level signal VGH is connected to the gate G of the third MOS transistor through a tenth resistor R10, the source S of the third MOS transistor is grounded, and the drain d of the third MOS transistor is connected to the gate G of the first MOS transistor in the control module. It should be noted that the types of the third MOS transistor and the second MOS transistor are opposite, and the types of the second MOS transistor and the first MOS transistor are the same, that is, when the first MOS transistor and the second MOS transistor are NMOS, the third MOS transistor is PMOS, and when the first MOS transistor and the second MOS transistor are PMOS, the third MOS transistor is NMOS. For example, when the third MOS transistor is a PMOS transistor, the PMOS transistor is turned on at a low level and turned off at a high level. When the clock high level signal VGH is in a normal state, the voltage value is a positive value, for example, 10V, and then the third MOS transistor is in a closed state, and the on and off of the first MOS transistor are determined by other input modules. When the voltage value of the clock high-level signal VGH is in an abnormal state is smaller than 10V, the voltage divided by the tenth resistor R10 meets the starting voltage of the third MOS transistor, the third MOS transistor is started, the source electrode S and the drain electrode d of the third MOS transistor are conducted, the grid electrode G of the first MOS transistor is grounded, and then the first MOS transistor cannot be started. It is easy to understand that the tenth resistor R10 plays a role of voltage division, and the resistance value of the tenth resistor R10 is determined by the clock high level signal VGH and the turn-on voltage of the third MOS transistor.
In a second aspect of the embodiments of the present application, a display control circuit is provided, and fig. 5 is a schematic block diagram of a display control circuit provided in the embodiments of the present application. As shown in fig. 5, a display control circuit provided in an embodiment of the present application includes: the signal monitoring circuit 1000 of the first aspect; the drive control circuit 2000, the drive control circuit 2000 is electrically connected to the signal monitoring circuit 1000, and the drive control circuit 2000 is configured to adjust a current display drive signal when the signal monitoring circuit 1000 outputs an abnormality monitoring result. The display control circuit may be integrated on a flexible circuit board, and is not particularly limited in this application. When the signal monitoring circuit 1000 outputs the abnormal monitoring result, the current display driving signal can be adjusted, specifically, the driving of the display panel can be stopped, the cause of the abnormality can be found, and the display panel can be continuously driven to display after the abnormal display driving signal is recovered to be normal.
According to the display control circuit provided by the embodiment of the application, at least two input modules are arranged in the signal monitoring circuit and are electrically connected with the control module together, each input module is used for being connected with one display driving signal to be monitored to form a monitoring electric signal, and the monitoring electric signal is used for indicating the abnormal state of the display driving signal to be monitored; and outputting an abnormal monitoring result when the display driving signal to be monitored corresponding to the at least one monitoring electric signal is in an abnormal state through the setting control module. The control module is electrically connected with at least two input modules, and when at least one monitoring electric signal is in an abnormal state, the control module outputs an abnormal monitoring structure, so that a plurality of display driving signals to be monitored can be monitored simultaneously. The signal monitoring circuit that this embodiment provided adopts integrated circuit's form to replace the current monitoring chip, a signal monitoring circuit's integrated circuit can realize monitoring at least two kinds simultaneously and wait to monitor the drive signal, can monitor two way at least display drive signal simultaneously promptly, on realizing the basis to multichannel drive signal monitoring, can save the use of current monitoring chip, practice thrift the cost, and signal monitoring circuit's simple structure, easy realization, device low cost is great to the scope of the monitoring of display drive signal, the monitoring effect is stronger.
In some implementations, fig. 6 is a schematic block diagram of another display control circuit provided in the embodiment of the present application, as shown in fig. 6, where the display control circuit provided in the embodiment of the present application may further include: the power management chip 3000, the power management chip 3000 is used for accessing a motherboard power supply, the motherboard power supply mainly provides motherboard power supply voltage VDD, and the power management chip 3000 is electrically connected with the drive control circuit 2000 and the signal monitoring circuit 1000 respectively; the signal monitoring circuit 1000 is used for sampling and monitoring the power driving signal through the power management chip 3000. The power driving signals may include a clock low level signal VGL, an anode driving signal ELVDD, a clock high level signal VGH, and the like, the motherboard power supply voltage VDD provided by the motherboard power supply may obtain various display driving signals after passing through the power management chip 3000, for example, the clock low level signal VGL, the anode driving signal ELVDD, the clock high level signal VGH, and the like, where these display driving signals are input into the display panel through the driving control circuit 2000 to drive the display panel display screen, the signal monitoring circuit 1000 may also sample these display driving signals to form a display driving signal to be monitored, the display driving signal to be monitored obtains a monitoring result RS through the monitoring of the signal monitoring circuit 1000, the monitoring result RS is transmitted to the driving control circuit 2000, the driving control circuit 2000 adjusts the display driving signal according to the abnormal monitoring result, and when the driving control circuit 2000 receives the normal monitoring result, the display driving signal is not adjusted, and the display driving is controlled according to the original program.
In a third aspect of the embodiments of the present application, a display device is provided, and fig. 7 is a schematic block diagram of a display device provided in the embodiments of the present application, as shown in fig. 7, where the display device provided in the embodiments of the present application includes: the display control circuit 4000 as described in the second aspect; the display panel 5000, the display panel 5000 and the display control circuit 4000 are electrically connected. The display panel 5000 may be an organic display panel, and embodiments of the present application are not particularly limited.
It should be noted that, the display device provided in the embodiment of the present application may be other fixed display terminals such as a smart phone, a tablet computer, a notebook computer, or a mobile display terminal, which is not specifically limited.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.
Claims (13)
1. A signal monitoring circuit, comprising:
the input modules are used for accessing display driving signals to be monitored to form monitoring electric signals, at least one input module comprises a second switching device, the display driving signals to be monitored accessed by the input modules are used for controlling the second switching device to be turned on or turned off, the second switching device is turned on or turned off and used for controlling the input modules to form different monitoring electric signals, and the monitoring electric signals are used for indicating abnormal states of the display driving signals to be monitored;
the control module is electrically connected with all the input modules and is used for outputting an abnormal monitoring result when the display driving signal to be monitored corresponding to at least one monitoring electric signal is in an abnormal state;
the control module comprises a first switching device;
the monitoring electric signals received by the control module are used for controlling the first switching device to be turned on or turned off, so that the control module outputs the abnormal monitoring result when at least one display driving signal to be monitored corresponding to the monitoring electric signals is in an abnormal state;
The control module comprises an output unit, wherein the output unit comprises a voltage stabilizing device;
the first end of the first switching device is used for accessing constant voltage, the second end of the first switching device is electrically connected with all the input modules, the third end of the first switching device is electrically connected with the output unit, and the first switching device is used for conducting the first end and the third end when being started;
one end of the voltage stabilizing device is used for being connected with a constant power supply voltage, and the other end of the voltage stabilizing device is electrically connected with the first end, wherein the constant power supply voltage is a main board power supply voltage;
the output unit comprises a first voltage dividing unit, a first capacitor and a first resistor, wherein the first voltage dividing unit comprises a second resistor and a third resistor, one end of the second resistor is electrically connected with the first switching device, the other end of the second resistor is used as an output end of the output unit, one end of the third resistor is electrically connected with the first switching device, the other end of the third resistor is used for being connected with the constant power supply voltage, the first capacitor is connected with the first switching device in parallel, and the first resistor is connected with the first switching device in parallel;
the display driving signals to be monitored comprise power driving signals and external system state signals, wherein the power driving signals comprise at least one of anode driving signals, clock high-level signals and clock low-level signals, and each input module is used for being connected with one display driving signal to be monitored.
2. The signal monitoring circuit according to claim 1, wherein the first switching device is configured to be turned on or off when the display driving signals to be monitored corresponding to all the received monitoring electric signals are in a normal state, and the first switching device is configured to be turned off or on when the display driving signals to be monitored corresponding to at least one of the monitoring electric signals are in an abnormal state.
3. The signal monitoring circuit of claim 1, wherein the first switching device comprises a first MOS transistor, a gate of the first MOS transistor is electrically connected to all of the input modules, a source of the first MOS transistor is connected to ground, and a drain of the first MOS transistor is electrically connected to the output unit.
4. The signal monitoring circuit according to claim 1, wherein one end of the voltage stabilizing device is electrically connected to one end of the first voltage dividing unit connected to the constant power supply voltage.
5. The signal monitoring circuit of claim 1, further comprising a voltage buffer unit disposed between the input module and the control module;
the voltage buffer unit comprises a capacitor and a resistor which are connected in parallel.
6. The signal monitoring circuit of claim 1, wherein the number of input modules is three.
7. The signal monitoring circuit according to claim 1, wherein the input module for accessing the clock low level signal includes a second voltage dividing unit and the second switching device, one end of the second voltage dividing unit is used for accessing a constant power supply voltage, and the other end of the second voltage dividing unit is electrically connected with the second switching device.
8. The signal monitoring circuit of claim 7, wherein the second voltage dividing unit comprises two resistors, two resistors being connected in series, one resistor being used for connecting the clock low level signal and the other resistor being used for connecting the constant voltage source voltage;
the second switching device is connected between the two resistors.
9. The signal monitoring circuit of claim 1, wherein the input module for accessing the anode drive signal comprises a third voltage dividing unit having one end for accessing the anode drive signal and the other end for connecting to the control module.
10. The signal monitoring circuit of claim 1, wherein the second switching device comprises a second MOS transistor, a gate of the second MOS transistor is used for accessing the display driving signal to be monitored, a source of the second MOS transistor is used for grounding, and a drain of the second MOS transistor is electrically connected with the control module.
11. A display control circuit, comprising:
the signal monitoring circuit of any one of claims 1-10;
the driving control circuit is electrically connected with the signal monitoring circuit and is used for adjusting the current display driving signal under the condition that the signal monitoring circuit outputs an abnormal monitoring result.
12. The display control circuit of claim 11, further comprising:
the power management chip is used for being connected with a main board power supply, and is electrically connected with the drive control circuit and the signal monitoring circuit respectively;
the signal monitoring circuit is used for sampling and monitoring the power supply driving signal through the power supply management chip.
13. A display device, comprising:
The display control circuit according to claim 11 or 12;
and the display panel is electrically connected with the display control circuit.
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