CN113920926B - Pixel driving circuit - Google Patents

Pixel driving circuit Download PDF

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Publication number
CN113920926B
CN113920926B CN202111221786.6A CN202111221786A CN113920926B CN 113920926 B CN113920926 B CN 113920926B CN 202111221786 A CN202111221786 A CN 202111221786A CN 113920926 B CN113920926 B CN 113920926B
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switch
control signal
period
control
terminal
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CN113920926A (en
Inventor
林容甫
吴佳恩
王贤军
李明贤
张琬珩
张书瀚
苏松宇
戴俊翔
黄文瑜
林嘉彦
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a pixel driving circuit, which is provided with a light-emitting unit, seven or eight switches and a capacitor. A switch and a capacitor are connected in series between the control end and one end of the driving switch, and the threshold voltage and the voltage drop can be compensated through the coupling of the capacitor, so that the light-emitting unit can provide consistent brightness.

Description

Pixel driving circuit
Technical Field
The present disclosure relates to a pixel driving circuit of a light emitting diode.
Background
Light emitting diodes are now widely used in various types of displays. The brightness of the light emitting diode when emitting light is related to the magnitude of its driving current, which is controlled by the driving transistor. However, because the process variation causes different threshold voltages (threshold voltage, vth) of the driving transistors of each pixel in the display, the light emitting diodes in different pixels have different driving currents, so that the brightness of each light emitting diode is different, and the display has a problem of uneven brightness when displaying images. In addition, the driving current is supplied by an operating voltage which is easily dropped (IR drop) due to a line resistance in a transfer path, so that the operating voltage is different for each pixel, causing an error in the driving current.
Therefore, it is an object of the study conducted by those skilled in the art how to compensate for the threshold voltage of the driving transistor of the display pixel and also compensate for the operation voltage.
Disclosure of Invention
Embodiments of the present disclosure propose a pixel driving circuit including the following elements. The light emitting unit has a first end and a second end, and the first end of the light emitting unit is connected to a first operation voltage. The first switch has a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light emitting unit, and the control end of the first switch is connected to the first control signal. The second switch has a first end, a second end and a control end, the first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to the second operating voltage. The third switch has a first end, a second end and a control end, the first end of the third switch is connected to the control end of the second switch, the second end of the third switch is connected to the first operating voltage, and the control end of the third switch is connected to the second control signal. The fourth switch has a first end, a second end and a control end, the first end of the fourth switch is connected to the second end of the first switch and the first end of the second switch, the second end of the fourth switch is connected to the first operating voltage, and the control end of the fourth switch is connected to the second control signal. The capacitor has a first end and a second end, and the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch and the first end of the fourth switch. The fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second end of the capacitor, the second end of the fifth switch is connected to the control end of the second switch and the first end of the third switch, and the control end of the fifth switch is connected to the first control signal. The sixth switch has a first end, a second end and a control end, the first end of the sixth switch is connected to the second end of the capacitor and the first end of the fifth switch, the second end of the sixth switch is connected to the first diode signal, and the control end of the sixth switch is connected to the third control signal. The seventh switch has a first end, a second end and a control end, the first end of the seventh switch is connected to the control end of the second switch, the first end of the third switch and the second end of the fifth switch, the second end of the seventh switch is connected to the second diode signal, and the control end of the seventh switch is connected to the third control signal. The eighth switch has a first end, a second end and a control end, the first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch and the first end of the sixth switch, the second end of the eighth switch is connected to the second operation voltage, and the control end of the eighth switch is connected to the second control signal.
In some embodiments, the pixel driving circuit operates sequentially in a first period, a second period, and a third period. In the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, and the third switch, the fourth switch and the eighth switch are in an on state. In the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in an off state, and the second switch, the sixth switch and the seventh switch are in an on state. In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch and the eighth switch are in an off state, and the first switch, the second switch and the fifth switch are in an on state.
Embodiments of the present disclosure propose a pixel driving circuit including the following elements. The light emitting unit has a first end and a second end, and the first end of the light emitting unit is connected to a first operation voltage. The first switch is provided with a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light-emitting unit, and the control end of the first switch is connected to a first control signal. The second switch has a first end, a second end and a control end, the first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to the second operating voltage. The third switch has a first end, a second end and a control end, the first end of the third switch is connected to the control end of the second switch, the second end of the third switch is connected to the second end of the first switch and the first end of the second switch, and the control end of the third switch is connected to the second control signal. The fourth switch has a first end, a second end and a control end, the first end of the fourth switch is connected to the second end of the first switch, the second end of the second switch and the second end of the third switch, the second end of the fourth switch is connected to the first operation voltage, and the control end of the fourth switch is connected to the second control signal. The capacitor has a first end and a second end, and the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch, the second end of the third switch and the first end of the fourth switch. The fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second end of the capacitor, the second end of the fifth switch is connected to the control end of the second switch and the first end of the third switch, and the control end of the fifth switch is connected to the first control signal. The sixth switch has a first end, a second end and a control end, the first end of the sixth switch is connected to the second end of the capacitor and the first end of the fifth switch, the second end of the sixth switch is connected to the first diode signal, and the control end of the sixth switch is connected to the third control signal. The seventh switch has a first end, a second end and a control end, the first end of the seventh switch is connected to the control end of the second switch, the first end of the third switch and the second end of the fifth switch, the second end of the seventh switch is connected to the second diode signal, and the control end of the seventh switch is connected to the fourth control signal.
In some embodiments, the pixel driving circuit operates in sequence in a first period, a second period, a third period, and a fourth period. In the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, and the third switch and the fourth switch are in an on state. In the second period, the first switch, the second switch, the fifth switch and the seventh switch are in an off state, and the third switch, the fourth switch and the sixth switch are in an on state. In the third period, the first switch, the third switch, the fourth switch and the fifth switch are in an off state, and the second switch, the sixth switch and the seventh switch are in an on state. In the fourth period, the third switch, the fourth switch, the sixth switch and the seventh switch are in an off state, and the second switch and the fifth switch are in an on state.
In some embodiments, the first through seventh switches are N-type transistors, and the first operating voltage is lower than the second operating voltage. In the first period, the first control signal, the third control signal and the fourth control signal are at a low level, and the second control signal is at a high level. In the second period, the first control signal and the fourth control signal are at low level, and the second control signal and the third control signal are at high level. In the third period, the first control signal and the second control signal are at low level, and the third control signal and the fourth control signal are at high level. In the fourth period, the first control signal is at a high level, and the second control signal, the third control signal and the fourth control signal are at a low level.
In some embodiments, the first through seventh switches are P-type transistors, and the first operating voltage is greater than the second operating voltage. In the first period, the first control signal, the third control signal and the fourth control signal are at a high level, and the second control signal is at a low level. In the second period, the first control signal and the fourth control signal are at high level, and the second control signal and the third control signal are at low level. In the third period, the first control signal and the second control signal are at high level, and the third control signal and the fourth control signal are at low level. In the fourth period, the first control signal is at a low level, and the second control signal, the third control signal and the fourth control signal are at a high level.
In some embodiments, the pixel driving circuit further includes an eighth switch having a first terminal, a second terminal, and a control terminal. The first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch and the first end of the sixth switch, the second end of the eighth switch is connected to the first diode signal, and the control end of the eighth switch is connected to the second control signal.
In some embodiments, the pixel driving circuit operates sequentially in a first period, a second period, and a third period, and the third control signal is identical to the fourth control signal. In the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, and the third switch, the fourth switch and the eighth switch are in an on state. In the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in an off state, and the second switch, the sixth switch and the seventh switch are in an on state. In the third period, the third switch, the fourth switch, the sixth switch, the seventh switch and the eighth switch are in an off state, and the first switch, the second switch and the fifth switch are in an on state.
In some embodiments, the first through eighth switches are N-type transistors, and the first operating voltage is lower than the second operating voltage. In the first period, the first control signal and the third control signal are at low level, and the second control signal is at high level. In the second period, the first control signal and the second control signal are at low level, and the third control signal is at high level. In the third period, the first control signal is at a high level, and the second control signal and the third control signal are at a low level.
In some embodiments, the first through eighth switches are P-type transistors, and the first operating voltage is higher than the second operating voltage. In the first period, the first control signal and the third control signal are at a high level, and the second control signal is at a low level. In the second period, the first control signal and the second control signal are at high level, and the third control signal is at low level. In the third period, the first control signal is at a low level, and the second control signal and the third control signal are at a high level.
In the pixel driving circuit, the light emitting unit provides uniform brightness due to the compensation of the threshold voltage and the operation voltage.
Drawings
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a circuit configuration diagram showing a pixel driving circuit according to a first embodiment.
Fig. 2 is a timing chart showing respective signals and node voltages in the pixel driving circuit according to the first embodiment.
Fig. 3 is a schematic diagram showing switching of the pixel driving circuit during a first period according to the first embodiment.
Fig. 4 is a schematic diagram showing switching of the pixel driving circuit during the second period according to the first embodiment.
Fig. 5 is a schematic diagram showing switching of the pixel driving circuit during the third period according to the first embodiment.
Fig. 6 is a schematic diagram showing switching of the pixel driving circuit in the fourth period according to the first embodiment.
Fig. 7 is a circuit configuration diagram showing a pixel driving circuit according to the second embodiment.
Fig. 8 is a timing chart showing respective signals and node voltages in the pixel driving circuit according to the second embodiment.
Fig. 9 is a schematic diagram showing switching of the pixel driving circuit during the first period according to the second embodiment.
Fig. 10 is a schematic diagram showing switching of the pixel driving circuit during a second period according to the second embodiment.
Fig. 11 is a schematic diagram showing switching of the pixel driving circuit during the third period according to the second embodiment.
Fig. 12 is a circuit configuration diagram showing a pixel driving circuit according to the third embodiment.
Fig. 13 is a timing diagram showing various signals and node voltages according to a third embodiment.
Fig. 14 is a circuit configuration diagram showing a pixel driving circuit according to the fourth embodiment.
Fig. 15 is a timing diagram showing various signals and node voltages according to a fourth embodiment.
Fig. 16 is a circuit configuration diagram showing a pixel driving circuit according to the fifth embodiment.
Fig. 17 is a circuit configuration diagram showing a pixel driving circuit according to the sixth embodiment.
Fig. 18 is a timing chart showing respective signals in the pixel driving circuit according to the sixth embodiment.
Fig. 19 is a schematic diagram showing switching of the pixel driving circuit during the first period according to the sixth embodiment.
Fig. 20 is a schematic diagram showing switching of the pixel driving circuit during the second period according to the sixth embodiment.
Fig. 21 is a schematic diagram showing switching of the pixel driving circuit in the third period according to the sixth embodiment.
Fig. 22 is a circuit configuration diagram showing a pixel driving circuit according to the seventh embodiment.
Reference numerals illustrate:
100: pixel driving circuit
110: light-emitting unit
T1 to T8: switch
C1: capacitance device
110-1, C1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1, T8-1: first end
110-2, C1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2, T8-2: second end
T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3: control terminal
VDD, VSS: operating voltage
Sn1, sn2, sn3, EM: control signal
SL, ref: diode signal
A, B, C: node
I d : electric current
210,810,1610: during a first period
220,820,1620: second period
230,830,1630: third period of time
240,1640: fourth period
Detailed Description
The terms "first," "second," and the like, as used herein, do not denote a particular order or sequence, but rather are merely used to distinguish one element or operation from another in the same technical term. The connection referred to herein may be a direct connection.
The pixel driving circuit can compensate the critical voltage and the operation voltage so that the light emitting unit can provide consistent brightness, and a plurality of embodiments are described below.
First embodiment
Fig. 1 is a circuit configuration diagram showing a pixel driving circuit according to a first embodiment. The pixel driving circuit 100 may be disposed in the display panel as a pixel, which is not limited in this disclosure. The pixel driving circuit 100 includes a light emitting unit 110, switches T1 to T17, and a capacitor C1. The light emitting unit 110 is, for example, a light emitting diode, and the size of the light emitting diode may be in a micrometer scale or other suitable size, which is not limited in this disclosure. In the embodiment of fig. 1, the switches T1 to T7 are, for example, thin film transistors (thin film transistor) and are N-type transistors.
The light emitting unit 110 has a first terminal 110-1 and a second terminal 110-2, and the first terminal 110-1 of the light emitting unit 110 is connected to the operating voltage VSS. The switch T1 has a first terminal T1-1, a second terminal T1-2 and a control terminal T1-3, wherein the first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light emitting unit 110, and the control terminal T1-3 of the switch T1 is connected to the control signal EM. The switch T2 has a first terminal T2-1, a second terminal T2-2 and a control terminal T2-3, the first terminal T2-1 of the switch T2 is connected to the second terminal T1-2 of the switch T1, and the second terminal T2-2 of the switch T2 is connected to an operating voltage VDD, wherein the operating voltage VDD is greater than the operating voltage VSS. The switch T3 has a first terminal T3-1, a second terminal T3-2 and a control terminal T3-3, the first terminal T3-1 of the switch T3 is connected to the control terminal T2-3 of the switch T2, the second terminal T3-2 of the switch T3 is connected to the second terminal T1-2 of the switch T1 and the first terminal T2-1 of the switch T2, and the control terminal T3-3 of the switch T3 is connected to the control signal Sn1. The switch T4 has a first terminal T4-1, a second terminal T4-2 and a control terminal T4-3, the first terminal T4-1 of the switch T4 is connected to the second terminal T1-2 of the switch T1, the second terminal T2-2 of the switch T2 and the second terminal T3-2 of the switch T3, the second terminal T4-2 of the switch T4 is connected to the operating voltage VSS, and the control terminal T4-3 of the switch T4 is connected to the control signal Sn1.
The capacitor C1 has a first end C1-1 and a second end C1-2, and the first end C1-1 of the capacitor C1 is connected to the second end T1-2 of the switch T1, the first end T2-1 of the switch T2, the second end T3-2 of the switch T3 and the first end T4-1 of the switch T4. The switch T5 has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, the first terminal T5-1 of the switch T5 is connected to the second terminal C1-2 of the capacitor C1, the second terminal T5-2 of the switch T5 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3-1 of the switch T3, and the control terminal T5-3 of the switch T5 is connected to the control signal EM. The switch T6 has a first terminal T6-1, a second terminal T6-2 and a control terminal T6-3, the first terminal T6-1 of the switch T6 is connected to the second terminal C1-2 of the capacitor C1 and the first terminal T5-1 of the switch T5, the second terminal T6-2 of the switch T6 is connected to the diode signal SL, and the control terminal T6-3 of the switch T6 is connected to the control signal Sn2. The switch T7 has a first terminal T7-1, a second terminal T7-2 and a control terminal T7-3, the first terminal T7-1 of the switch T7 is connected to the control terminal T2-3 of the switch T2, the first terminal T3-1 of the switch T3 and the second terminal T5-2 of the switch T5, the second terminal T7-2 of the switch T7 is connected to the diode signal Ref, and the control terminal T7-3 of the switch T7 is connected to the control signal Sn3. For illustration, node A, B, C is also shown in fig. 1.
Fig. 2 is a timing chart showing respective signals and node voltages in the pixel driving circuit according to the first embodiment. Referring to fig. 2, the pixel driving circuit sequentially operates in a first period 210, a second period 220, a third period 230 and a fourth period 240.
Fig. 3 is a schematic diagram showing switching of the pixel driving circuit during a first period according to the first embodiment. Referring to fig. 2 and 3, during the first period 210, the control signal Sn1 is at a high level, and the control signals Sn2, sn3 and EM are at low levels. Therefore, in the first period 210, the switches T1, T2, T5, T6, and T7 are turned off, and the switches T3 and T4 are turned on. At this time, the potential of the node a and the node C are the same as the operation voltage VSS.
Fig. 4 is a schematic diagram showing switching of the pixel driving circuit during the second period according to the first embodiment. Referring to fig. 2 and 4, in the second period 220, the control signals Sn1 and Sn2 are at a high level, and the control signals Sn3 and EM are at a low level. Therefore, in the second period 220, the switches T1, T2, T5 and T7 are in the off state, and the switches T3, T4 and T6 are in the on state. At this time, the potential of the node a is the same as the operation voltage VSS. The diode signal SL provides the data voltage V data The potential of node B is the same as the data voltage V data . The potential of the node C is the same as the operating voltage VSS.
Fig. 5 shows the pixel driving electric during the third period according to the first embodimentSchematic of the switching of the circuit. Referring to fig. 2 and 5, in the third period 230, the control signal Sn1 and the control signal EM are at low level, and the control signal Sn2 and the control signal Sn3 are at high level. Therefore, in the third period 230, the switches T1, T3, T4, and T5 are turned off, and the switches T2, T6, and T7 are turned on. At this time, the diode signal Ref provides the reference voltage V ref The potential of the node A is the same as the reference voltage V ref . The potential of the node B is the same as the data voltage Vdata. The switch T2 is turned on at the beginning of the third period 230, and then the potential of the node C is continuously increased until the potential V is reached ref -V th_T2 The switch T2 is switched to the off state, wherein vth_t2 is the threshold voltage of the switch T2.
Fig. 6 is a schematic diagram showing switching of the pixel driving circuit in the fourth period according to the first embodiment. Referring to fig. 2 and 6, in the fourth period 240, the control signal Sn1, the control signal Sn2 and the control signal Sn3 are at low level, and the control signal EM is at high level. Therefore, in the fourth period 240, the switches T3, T4, T6, and T7 are turned off, and the switches T2 and T5 are turned on. At this time, the potential of the node C is the same as VSS+V LED Wherein V is LED Is the voltage across the two ends of the light emitting unit 110 when it is turned on. Vref-V due to potential at node C from third period 230 th_T2 VSS+V changed to fourth period 240 LED The variation is VSS+V LED -V ref +V th_T2 Thus the potential of node B will be from V data Change to V data +VSS+V LED -V ref +V th_T2 . The potential of node A is the same as that of node B, and the potential turns on switch T2 to generate current I d This current I d The size of (2) is shown in the following equation 1.
[ mathematics 1]
I d ＝K(V A -V C -V th_T2 ) 2
＝K(V data +VSS+V LED -V ref +V th_T2 -VSS-V LED -V th_T2 ) 2
＝K(V data -V ref ) 2
Wherein K is a constant, V A For the potential of node A, V C The potential of node C. It is noted that in equation 1, the threshold voltage V th_T2 And the reference voltages VSS cancel each other out due to compensation, thus the current I d Has been free from critical voltage V th_T2 And the reference voltage VSS.
Second embodiment
Fig. 7 is a circuit configuration diagram showing a pixel driving circuit according to the second embodiment. Referring to fig. 7, the difference between fig. 7 and fig. 1 is that there are more switches T8, the switch T8 has a first terminal T8-1, a second terminal T8-2 and a third terminal T8-3, the first terminal T8-1 of the switch T8 is connected to the second terminal C1-2 of the capacitor C1, the first terminal T5-1 of the switch T5 and the first terminal T6-1 of the switch T6, the second terminal T8-2 of the switch T8 is connected to the diode signal SL, and the control terminal T8-3 of the switch T8 is connected to the control signal Sn1.
Fig. 8 is a timing chart showing respective signals and node voltages in the pixel driving circuit according to the second embodiment. Referring to fig. 8, in the second embodiment, the control signal Sn3 is identical to the control signal Sn2, and the control signal Sn3 is not shown below for simplicity. The pixel driving circuit sequentially operates in a first period 810, a second period 820, and a third period 830.
Fig. 9 is a schematic diagram showing switching of the pixel driving circuit during the first period according to the second embodiment. Referring to fig. 8 and 9, in the first period 810, the control signal Sn1 is at a high level, and the control signals Sn2 and EM are at a low level. Accordingly, in the first period 810, the switches T1, T2, T5, T6, and T7 are turned off, and the switches T3, T4, and T8 are turned on. At this time, the potential of the node a is the same as the operation voltage VSS. The diode signal SL provides the data voltage V data The potential of node B is the same as the data voltage V data . The potential of the node C is the same as the operating voltage VSS.
Fig. 10 is a schematic diagram showing switching of the pixel driving circuit during a second period according to the second embodiment. Referring to fig. 8 and 10, in the second phaseIn the interval 820, the control signal Sn1 and the control signal EM are at low level, and the control signal Sn2 is at high level. Therefore, in the second period 820, the switches T1, T3, T4, T5, and T8 are in the off state, and the switches T2, T6, and T7 are in the on state. The diode signal Ref provides a reference voltage V ref The potential of the node A is the same as the reference voltage V ref . The potential of node B is the same as the data voltage V data . At the beginning of the second period 820, the switch T2 is turned on, and then the potential of the node C is continuously increased until the potential V is reached ref -V th_T2 The switch T2 is switched to the off state, wherein vth_t2 is the threshold voltage of the switch T2.
Fig. 11 is a schematic diagram showing switching of the pixel driving circuit during the third period according to the second embodiment. Referring to fig. 8 and 11, in the third period 830, the control signals Sn1 and Sn2 are at low level, and the control signal EM is at high level. Therefore, in the third period 830, the switches T3, T4, T6, T7, and T8 are turned off, and the switches T1, T2, and T5 are turned on. The potential of node C is the same as VSS+V LED . Since the potential of the node C is from V in the second period 820 ref -V th_T2 Change to VSS+V LED The variation is VSS+V LED -V ref +V th_T2 Thus the potential of node B is from V data Change to V data +VSS+V LED -V ref +V th_T2 . The potential of node A is the same as that of node B, which turns on switch T2 to generate current I d This current I d The size of (2) is as shown in the above equation 1.
Thus, in the second embodiment, the threshold voltage V th_T2 And the reference voltages VSS cancel each other out due to compensation, current I d Has been free from critical voltage V th_T2 And the reference voltage VSS.
Third embodiment
The third embodiment is to change the N-type transistor to the P-type transistor as compared with the first embodiment. Fig. 12 is a circuit configuration diagram showing a pixel driving circuit according to a third embodiment, and fig. 13 is a timing chart showing respective signals and node voltages according to the third embodiment. In the first period 210, the control signal Sn1 is at a low level, and the control signals Sn2, sn3 and EM are at a high level. In the second period 220, the control signals Sn1 and Sn2 are at low level, and the control signals Sn3 and EM are at high level. In the third period 230, the control signal Sn1 and the control signal EM are at a high level, and the control signal Sn2 and the control signal Sn3 are at a low level. In the fourth period 240, the control signal Sn1, the control signal Sn2, and the control signal Sn3 are at the high level, and the control signal EM is at the low level. Those skilled in the art will understand the circuit and operation of the third embodiment according to the above description of the first embodiment, and the detailed description is omitted here.
Fourth embodiment
The fourth embodiment is to change the N-type transistor to the P-type transistor as compared with the second embodiment. Fig. 14 is a circuit configuration diagram showing a pixel driving circuit according to a fourth embodiment, and fig. 15 is a timing chart showing respective signals and node voltages according to the fourth embodiment. In the first period 810, the control signal Sn1 is at a low level, and the control signal Sn2 and the control signal EM are at a high level. In the second period 820, the control signal Sn1 and the control signal EM are at a high level, and the control signal Sn2 is at a low level. In the third period 830, the control signals Sn1 and Sn2 are at the high level, and the control signal EM is at the low level. Those skilled in the art will understand the circuit and operation of the fourth embodiment according to the above description of the second embodiment, and the detailed description is omitted here.
Fifth embodiment
Fig. 16 is a circuit configuration diagram showing a pixel driving circuit according to the fifth embodiment. The fifth embodiment is to exchange the diode control signal SL with the diode control signal Ref in comparison with the first embodiment, although this will change the potential of the node a and the node B for the current I d The calculation formula of (2) changes only the data voltage V data With reference voltage V ref In the order of (I), i.e. I d ＝K(V ref -V data ) 2 But current I d Is not of the same size asThere are variations. It should be noted that the diode control signal SL and the diode control signal Ref may also be interchanged in the second embodiment, the third embodiment and the fourth embodiment.
Sixth embodiment
Fig. 17 is a circuit configuration diagram showing a pixel driving circuit according to the sixth embodiment. Referring to fig. 17, the light emitting unit 110 has a first end 110-1 and a second end 110-2, and the first end 110-1 of the light emitting unit 110 is connected to an operating voltage VSS. The switch T1 has a first terminal T1-1, a second terminal T1-2 and a control terminal T1-3, wherein the first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light emitting unit 110, and the control terminal T1-3 of the switch T1 is connected to the control signal EM. The switch T2 has a first terminal T2-1, a second terminal T2-2 and a control terminal T2-3, the first terminal T2-1 of the switch T2 is connected to the second terminal T1-2 of the switch T1, and the second terminal T2-2 of the switch T2 is connected to an operating voltage VDD, wherein the operating voltage VDD is greater than the operating voltage VSS. The switch T3 has a first terminal T3-1, a second terminal T3-2 and a control terminal T3-3, the first terminal T3-1 of the switch T3 is connected to the control terminal T2-3 of the switch T2, the second terminal T3-2 of the switch T3 is connected to the operating voltage VSS, and the control terminal T3-3 of the switch T3 is connected to the control signal Sn1. The switch T4 has a first terminal T4-1, a second terminal T4-2 and a control terminal T4-3, the first terminal T4-1 of the switch T4 is connected to the second terminal T1-2 of the switch T1 and the first terminal T2-1 of the switch T2, the second terminal T4-2 of the switch T4 is connected to the operating voltage VSS, and the control terminal T4-3 of the switch T4 is connected to the control signal Sn1.
The capacitor C1 has a first end C1-1 and a second end C1-2, and the first end C1-1 of the capacitor C1 is connected to the second end T1-2 of the switch T1, the first end T2-1 of the switch T2 and the first end T4-1 of the switch T4. The switch T5 has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, the first terminal T5-1 of the switch T5 is connected to the second terminal C1-2 of the capacitor C1, the second terminal T5-2 of the switch T5 is connected to the control terminal T2-3 of the switch T2 and the first terminal T3-1 of the switch T3, and the control terminal T5-3 of the switch T5 is connected to the control signal EM. The switch T6 has a first terminal T6-1, a second terminal T6-2 and a control terminal T6-3, the first terminal T6-1 of the switch T6 is connected to the second terminal C1-2 of the capacitor C1 and the first terminal T5-1 of the switch T5, the second terminal T6-2 of the switch T6 is connected to the diode signal SL, and the control terminal T6-3 of the switch T6 is connected to the control signal Sn2. The switch T7 has a first terminal T7-1, a second terminal T7-2 and a control terminal T7-3, the first terminal T7-1 of the switch T7 is connected to the control terminal T2-3 of the switch T2, the first terminal T3-1 of the switch T3 and the second terminal T5-2 of the switch T5, the second terminal T7-2 of the switch T7 is connected to the diode signal Ref, and the control terminal T7-3 of the switch T7 is connected to the control signal Sn3. The switch T8 has a first terminal T8-1, a second terminal T8-2 and a third terminal T8-3, the first terminal T8-1 of the switch T8 is connected to the second terminal C1-2 of the capacitor C1, the first terminal T5-1 of the switch T5 and the first terminal T6-1 of the switch T6, the second terminal T8-2 of the switch T8 is connected to the operating voltage VDD, and the control terminal T8-3 of the switch T8 is connected to the control signal Sn1. For illustration, node A, B, C is also shown in fig. 17.
Fig. 18 is a timing chart showing respective signals in the pixel driving circuit according to the sixth embodiment. Referring to fig. 18, in this embodiment, the diode signal SL provides the data voltage V data The diode signal Ref provides a reference voltage V ref . The pixel driving circuit sequentially operates in a first period 1610, a second period 1620, a third period 1630, and a fourth period 1640, which do not overlap with each other.
Fig. 19 is a schematic diagram showing switching of the pixel driving circuit during the first period according to the sixth embodiment. Referring to fig. 18 and 19, in the first period 1610, the control signal Sn1 is at a high level, and the control signals Sn2 and EM are at a low level. Accordingly, during the first period 1610, the switches T1, T2, T5, T6, and T7 are turned off, and the switches T3, T4, and T8 are turned on. At this time, the potential of the node a is the same as the operation voltage VSS. The potential of the node B is the same as the operating voltage VDD. The potential of the node C is the same as the operating voltage VSS.
Fig. 20 is a schematic diagram showing switching of the pixel driving circuit during the second period according to the sixth embodiment. Referring to fig. 18 and 20, in the second period 1620, the control signal Sn1 and the control signal EM are at low level, and the control signal Sn2 is at high level. Therefore, in the second period 1620, the switches T1, T3, T4, T5, and T8 are in the off state, and the switches T2, T6, and T7 are in the on state. The potential of the node A is the same as the reference voltage V ref . The potential of node B is the same as the data voltage V data . In the second period 1620, the switch T2 is turned on, and the potential of the node C is continuously increased until the potential V is reached ref -V th_T2 The switch T2 is switched to the off state, wherein V th_T2 Is the threshold voltage of switch T2.
Fig. 21 is a schematic diagram showing switching of the pixel driving circuit in the third period according to the sixth embodiment. Referring to fig. 18 and 21, in the third period 1630, the control signals Sn1 and Sn2 are at low level, and the control signal EM is at high level. Accordingly, in the third period 1630, the switches T3, T4, T6, T7, and T8 are in the off state, and the switches T1, T2, and T5 are in the on state. The potential of node C is the same as VSS+V LED . Due to the potential at node C being from V of second period 1620 ref -V th_T2 Change to VSS+V LED The variation is VSS+V LED -V ref +V th_T2 Thus the potential of node B is from V data Change to V data +VSS+V LED -V ref +V th_T2 . The potential of node A is the same as that of node B, which turns on switch T2 to generate current I d This current I d The size of (2) is as shown in the above equation 1. Therefore, in the sixth embodiment, the threshold voltage V th_T2 And the reference voltages VSS cancel each other out due to compensation, current I d Has been free from critical voltage V th_T2 And the reference voltage VSS.
In the fourth period 1640, the control signal Sn1, the control signal Sn2 and the control signal EM are at low level, so the switches T1 to T8 are in the off state to turn off the light emitting unit 110.
Seventh embodiment
Fig. 22 is a circuit configuration diagram showing a pixel driving circuit according to the seventh embodiment. Referring to fig. 22, the seventh embodiment is to change the N-type transistor to the P-type transistor compared with the sixth embodiment. Those skilled in the art will understand the circuit and operation of the seventh embodiment according to the above description of the sixth embodiment, and the detailed description is omitted here.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A pixel driving circuit comprising:
a light-emitting unit having a first end and a second end, wherein the first end of the light-emitting unit is connected to a first operating voltage;
the first switch is provided with a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light-emitting unit, and the control end of the first switch is connected to a first control signal;
the second switch is provided with a first end, a second end and a control end, wherein the first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to a second operation voltage;
the third switch is provided with a first end, a second end and a control end, wherein the first end of the third switch is connected to the control end of the second switch, the second end of the third switch is connected to the first operation voltage, and the control end of the third switch is connected to a second control signal;
a fourth switch having a first end, a second end and a control end, wherein the first end of the fourth switch is connected to the second end of the first switch and the first end of the second switch, the second end of the fourth switch is connected to the first operating voltage, and the control end of the fourth switch is connected to the second control signal;
a capacitor having a first end and a second end, wherein the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch and the first end of the fourth switch;
a fifth switch having a first end, a second end and a control end, wherein the first end of the fifth switch is connected to the second end of the capacitor, the second end of the fifth switch is connected to the control end of the second switch and the first end of the third switch, and the control end of the fifth switch is connected to the first control signal;
a sixth switch having a first end, a second end and a control end, wherein the first end of the sixth switch is connected to the second end of the capacitor and the first end of the fifth switch, the second end of the sixth switch is connected to a first diode signal, and the control end of the sixth switch is connected to a third control signal;
a seventh switch having a first end, a second end and a control end, wherein the first end of the seventh switch is connected to the control end of the second switch, the first end of the third switch and the second end of the fifth switch, the second end of the seventh switch is connected to a second diode signal, and the control end of the seventh switch is connected to the third control signal; and
an eighth switch having a first end, a second end and a control end, wherein the first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch and the first end of the sixth switch, the second end of the eighth switch is connected to the second operating voltage, and the control end of the eighth switch is connected to the second control signal.
2. The pixel driving circuit according to claim 1, wherein the pixel driving circuit operates sequentially in a first period, a second period and a third period,
wherein in the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, the third switch, the fourth switch and the eighth switch are in an on state,
wherein in the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the off state, the second switch, the sixth switch and the seventh switch are in the on state,
in the third period, the third switch, the fourth switch, the sixth switch, the seventh switch and the eighth switch are in the off state, and the first switch, the second switch and the fifth switch are in the on state.
3. A pixel driving circuit comprising:
a light-emitting unit having a first end and a second end, wherein the first end of the light-emitting unit is connected to a first operating voltage;
the first switch is provided with a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light-emitting unit, and the control end of the first switch is connected to a first control signal;
the second switch is provided with a first end, a second end and a control end, wherein the first end of the second switch is connected to the second end of the first switch, and the second end of the second switch is connected to a second operation voltage;
the first end of the third switch is connected to the control end of the second switch, the second end of the third switch is connected to the second end of the first switch and the first end of the second switch, and the control end of the third switch is connected to a second control signal;
a fourth switch having a first end, a second end and a control end, wherein the first end of the fourth switch is connected to the second end of the first switch, the second end of the second switch and the second end of the third switch, the second end of the fourth switch is connected to the first operating voltage, and the control end of the fourth switch is connected to the second control signal;
a capacitor having a first end and a second end, wherein the first end of the capacitor is connected to the second end of the first switch, the first end of the second switch, the second end of the third switch and the first end of the fourth switch;
a fifth switch having a first end, a second end and a control end, wherein the first end of the fifth switch is connected to the second end of the capacitor, the second end of the fifth switch is connected to the control end of the second switch and the first end of the third switch, and the control end of the fifth switch is connected to the first control signal;
a sixth switch having a first end, a second end and a control end, wherein the first end of the sixth switch is connected to the second end of the capacitor and the first end of the fifth switch, the second end of the sixth switch is connected to a first diode signal, and the control end of the sixth switch is connected to a third control signal; and
the seventh switch is provided with a first end, a second end and a control end, wherein the first end of the seventh switch is connected to the control end of the second switch, the first end of the third switch and the second end of the fifth switch, the second end of the seventh switch is connected to a second diode signal, and the control end of the seventh switch is connected to a fourth control signal.
4. The pixel driving circuit according to claim 3, wherein the pixel driving circuit operates sequentially in a first period, a second period, a third period and a fourth period,
wherein in the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, the third switch and the fourth switch are in an on state,
wherein in the second period, the first switch, the second switch, the fifth switch and the seventh switch are in the off state, the third switch, the fourth switch and the sixth switch are in the on state,
wherein in the third period, the first switch, the third switch, the fourth switch and the fifth switch are in the off state, the second switch, the sixth switch and the seventh switch are in the on state,
in the fourth period, the third switch, the fourth switch, the sixth switch and the seventh switch are in the off state, and the second switch and the fifth switch are in the on state.
5. The pixel driving circuit according to claim 4, wherein the first to seventh switches are N-type transistors, the first operating voltage is lower than the second operating voltage,
wherein in the first period, the first control signal, the third control signal and the fourth control signal are at a low level, the second control signal is at a high level,
wherein in the second period, the first control signal and the fourth control signal are at the low level, the second control signal and the third control signal are at the high level,
wherein in the third period, the first control signal and the second control signal are at the low level, the third control signal and the fourth control signal are at the high level,
in the fourth period, the first control signal is at the high level, and the second control signal, the third control signal and the fourth control signal are at the low level.
6. The pixel driving circuit according to claim 4, wherein the first through seventh switches are P-type transistors, the first operating voltage is greater than the second operating voltage,
wherein in the first period, the first control signal, the third control signal and the fourth control signal are at a high level, the second control signal is at a low level,
wherein in the second period, the first control signal and the fourth control signal are at the high level, the second control signal and the third control signal are at the low level,
wherein in the third period, the first control signal and the second control signal are at the high level, the third control signal and the fourth control signal are at the low level,
in the fourth period, the first control signal is at the low level, and the second control signal, the third control signal and the fourth control signal are at the high level.
7. A pixel drive circuit according to claim 3, further comprising:
an eighth switch having a first end, a second end and a control end, wherein the first end of the eighth switch is connected to the second end of the capacitor, the first end of the fifth switch and the first end of the sixth switch, the second end of the eighth switch is connected to the first diode signal, and the control end of the eighth switch is connected to the second control signal.
8. The pixel driving circuit according to claim 7, wherein the pixel driving circuit sequentially operates in a first period, a second period, and a third period, the third control signal being identical to the fourth control signal,
wherein in the first period, the first switch, the second switch, the fifth switch, the sixth switch and the seventh switch are in an off state, the third switch, the fourth switch and the eighth switch are in an on state,
wherein in the second period, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the off state, the second switch, the sixth switch and the seventh switch are in the on state,
in the third period, the third switch, the fourth switch, the sixth switch, the seventh switch and the eighth switch are in the off state, and the first switch, the second switch and the fifth switch are in the on state.
9. The pixel driving circuit according to claim 8, wherein the first to eighth switches are N-type transistors, the first operating voltage is lower than the second operating voltage,
wherein during the first period, the first control signal and the third control signal are at a low level, the second control signal is at a high level,
wherein during the second period, the first control signal and the second control signal are at the low level, the third control signal is at the high level,
in the third period, the first control signal is at the high level, and the second control signal and the third control signal are at the low level.
10. The pixel driving circuit according to claim 8, wherein the first switch to the eighth switch are P-type transistors, the first operation voltage is higher than the second operation voltage,
wherein in the first period, the first control signal and the third control signal are at a high level, the second control signal is at a low level,
wherein during the second period, the first control signal and the second control signal are at the high level, the third control signal is at the low level,
in the third period, the first control signal is at the low level, and the second control signal and the third control signal are at the high level.
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