CN111583870A - Pixel driving circuit - Google Patents

Pixel driving circuit Download PDF

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Publication number
CN111583870A
CN111583870A CN202010416594.XA CN202010416594A CN111583870A CN 111583870 A CN111583870 A CN 111583870A CN 202010416594 A CN202010416594 A CN 202010416594A CN 111583870 A CN111583870 A CN 111583870A
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terminal
switch
signal
voltage
electrically connected
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郑园
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a pixel driving circuit. The pixel driving circuit comprises seven switches, two storage capacitors, an organic light emitting diode and a plurality of signal sources. The time sequence of the signal sources can be divided into a reset stage, a compensation stage, a writing stage and a light-emitting stage in sequence, and the compensation stage and the writing stage of the threshold voltage are separated, so that the compensation stage is not affected by the compression of compensation time due to high-frequency driving display, and the compensation effect is further kept.

Description

Pixel driving circuit
Technical Field
The invention relates to the technical field of display, in particular to a pixel driving circuit.
Background
With the development of display panels, display panels with high frequency driving display have gradually become the development trend of display panels because they can bring smoother use experience. However, the difficulties of high-frequency driving display are different for the currently mainstream liquid crystal display panel and the oled display panel, wherein the high-frequency driving display of the oled display panel has higher difficulty, and in order to ensure the display quality of the current oled display panel, a compensation circuit is usually adopted to solve the problem of unstable current between pixels due to threshold voltage.
Referring to fig. 1 and fig. 2, a schematic diagram and a timing diagram of a pixel driving circuit in the prior art are shown, respectively. The pixel driving circuit is composed of seven switches and a storage capacitor (7T1C), and has a DATA voltage V of the DATA signal DATA when the scan signal Scan (n) is at a low leveldataAre written to the node through the first to third switches T1 to T3 which are turned onS, the voltage of the node S is made to be a relation related to the threshold voltage, i.e. the compensation phase of the threshold voltage and the writing of the DATA signal DATA are performed simultaneously in the prior art. When the organic light emitting diode display panel performs light emitting display, the current of the organic light emitting diode is a relational expression irrelevant to the threshold voltage, so that the problem of unstable current caused by the threshold voltage is solved, but high-frequency driving display can be compressed to the time when each row of scanning lines perform scanning, and meanwhile, the time for performing compensation can be compressed, so that the problem of poor compensation effect is caused.
Therefore, it is necessary to provide a pixel driving circuit to solve the problems of the prior art.
Disclosure of Invention
It is an object of the present invention to provide a pixel driving circuit to solve the above-mentioned problems of the prior art.
To achieve the above object, the present invention provides a pixel driving circuit comprising:
a first switch;
a second switch, a first end of which is electrically connected to the first input voltage, a second end of which is controlled by the first enable signal, and a third end of which is electrically connected to the first end of the first switch through a first node;
a third switch having a first terminal electrically connected to a data voltage having a data signal, a second terminal controlled by a scan signal, and a third terminal electrically connected to the second terminal of the first switch through a second node;
a fourth switch, a first terminal of which is electrically connected to the reference voltage, a second terminal of which is controlled by the compensation signal, and a third terminal of which is electrically connected to the second terminal of the first switch and the third terminal of the third switch through the second node;
a fifth switch, the first end of which is electrically connected to the initial voltage and the second end of which is controlled by the compensation voltage;
a sixth switch, a first terminal of which is electrically connected to the third terminal of the first switch, a second terminal of which is controlled by the second enable signal, and a third terminal of which is electrically connected to the third terminal of the fifth switch;
a seventh switch, a first terminal of which is electrically connected to the second input voltage, a second terminal of which is controlled by the reset signal, and a third terminal of which is connected to the first terminal of the first switch and the third terminal of the second switch through the first node;
an organic light emitting diode having an anode terminal electrically connected to the third terminal of the fifth switch and the third terminal of the sixth switch, and a cathode terminal electrically connected to a common voltage;
a first storage capacitor having a first terminal electrically connected to the second terminal of the first switch, the third terminal of the third switch, and the third terminal of the fourth switch via the second node, and a second terminal electrically connected to the first terminal of the first switch, the third terminal of the second switch, and the third terminal of the seventh switch via the first node; and
a second storage capacitor having a first terminal electrically connected to the first input voltage, a second terminal electrically connected to the third terminal of the seventh switch, and a first terminal of the first switch, a third terminal of the second switch, and a second terminal of the first storage capacitor through the first node.
Further, the timings of the first enable signal, the second enable signal, the compensation signal, the reset signal, and the scan signal may be sequentially divided into a reset phase, a compensation phase, a write phase, and a light emitting phase.
Further, in the reset phase, the compensation signal and the reset signal are at a first level, and the first enable signal, the second enable signal, and the scan signal are at a second level.
Further, in the compensation phase, the second enable signal and the compensation signal are at a first level, and the first enable signal, the reset signal, and the scan signal source are at a second level.
Further, in the write phase, the scan signal is at a first level, and the first enable signal, the second enable signal, the compensation signal, and the reset signal are at a second level.
Further, in the light emitting phase, the first enable signal and the second enable signal are at a first level, and the compensation signal, the reset signal, and the scan signal are at a second level.
Further, in the reset phase, the voltage V of the first nodeASatisfy the relation: vA＝VDD2Voltage V of the second nodeQSatisfy the relation: vQ＝VrefIn which V isDD2Is the second input voltage, VrefIs the reference voltage.
Further, in the compensation phase, the voltage V of the first nodeASatisfy the relation: vA＝Vref+|VthVoltage V of the second nodeQSatisfy the relation: vQ＝VrefIn which V isthIs the threshold voltage.
Further, in the write phase, the voltage V of the first nodeASatisfy the relation:
Figure BDA0002494267390000041
voltage V of the second nodeQSatisfy the relation: vQ＝VdataIn which V isdataFor the data voltage, C1 is the capacitance value of the first storage capacitor, and C2 is the capacitance value of the second storage capacitor.
Further, a current I flowing through the organic light emitting diodeOLEDSatisfy the relation:
Figure BDA0002494267390000042
where μ is the carrier mobility, CoxW is the gate width of the TFT, and L is the gate length of the TFT.
The invention can solve the problem of current instability caused by threshold voltage, and further, the compensation stage of the threshold voltage is separated from the writing stage, so that the compensation stage can not be influenced by the compression compensation time caused by high-frequency driving display, and the compensation effect is further kept. Therefore, the method has foresight property, and has obvious advantages compared with the prior art.
Drawings
Fig. 1 is a schematic diagram of a pixel driving circuit in the prior art.
Fig. 2 is a timing diagram of a pixel driving circuit in the prior art.
Fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention.
FIG. 4 is a timing diagram of a pixel driving circuit according to an embodiment of the invention.
FIG. 5 is a timing diagram of a pixel driving circuit for scanning a plurality of rows of scan lines according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the particular embodiments described herein are illustrative only, and that the word "embodiment" as used in the description of the invention is intended to serve as an example, instance, or illustration, and is not intended to limit the invention.
Referring to fig. 3, fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention. The pixel driving circuit of the present invention includes seven switches (i.e., T1-T7) and two storage capacitors (i.e., C1 and C2), wherein each switch includes a first terminal, a second terminal, and a third terminal. In the present embodiment, the seven switches are illustratively P-type thin film transistors, each of the switches has a source terminal, a gate terminal, and a drain terminal respectively corresponding to the first terminal, the second terminal, and the third terminal, and the P-type thin film transistor is turned on when the gate terminal of the P-type thin film transistor is controlled by a low level signal, and is turned off when the gate terminal of the P-type thin film transistor is controlled by a high level signal. In an embodiment, the seven switches may also be N-type tfts, which operate in a similar manner but with opposite polarities to the P-type tfts, and are not described herein again.
In the present embodiment, the first terminal of the first switch T1 is electrically connected to the third terminal of the second switch T2, the third terminal of the seventh switch T7, the second terminal of the first storage capacitor C1, and the second terminal of the second storage capacitor C2 through a first node electrical connection a, the second terminal is electrically connected to the third terminal of the third switch T3, the third terminal of the fourth switch T4, and the first terminal of the first storage capacitor C1 through a second node Q, and the third terminal is electrically connected to the third terminal of the sixth switch T6.
In this embodiment, the first terminal of the second switch T2 is electrically connected to the first input voltage VDDA second terminal controlled by a first enable signal EM1, and a third terminal electrically connected to the first terminal of the first switch T1, the third terminal of the seventh switch T7, the second terminal of the first storage capacitor C1, and the second terminal of the second storage capacitor C2 through the first node a, wherein the first enable signal EM1 is used to control the on and off of the second switch T2.
In this embodiment, a first end of the third switch T3 is electrically connected to the DATA voltage V having the DATA signal DATAdataA second terminal controlled by a SCAN signal SCAN, and a third terminal electrically connected to the second terminal of the first switch T1, the third terminal of the fourth switch T4, and the first terminal of the first storage capacitor C1 through the second node Q, wherein the SCAN signal SCAN is a level signal from a SCAN line (not shown) for controlling the on and off of the third switch T3.
In the present embodiment, a first terminal of the fourth switch T4 is electrically connected to the reference voltage VrefAnd a third terminal electrically connected to the second terminal of the first switch T1, the third terminal of the third switch T3, and the first terminal of the first storage capacitor C1 through the second node Q, wherein the compensation signal Comp is used to control the on and off of the fourth switch T4.
In the present embodiment, a first terminal of the fifth switch T5 is electrically connected to the initial voltage VinitA second terminal controlled by the compensation signal Comp, and a third terminal electrically connected to the third terminal of the sixth switch T6 and the anode terminal of the organic light emitting diode OLED, wherein the compensation signal Comp is also used for controlling the on/off of the fifth switch T5And off.
In this embodiment, a first terminal of the sixth switch T6 is electrically connected to a third terminal of the first switch T1, a second terminal of the sixth switch T6 is controlled by a second enable signal EM2, and a third terminal of the sixth switch T5 is electrically connected to the third terminal of the fifth switch T5 and an anode terminal of the organic light emitting diode OLED, wherein the second enable signal EM2 is used to control the sixth switch T6 to be turned on and off.
In this embodiment, a first terminal of the seventh switch T7 is electrically connected to the second input voltage VDD2A second terminal controlled by a reset signal Rst, a third terminal electrically connected to the second terminal of the second storage capacitor C2, and electrically connected to the first terminal of the first switch T1, the third terminal of the second switch T2, and the second terminal of the first storage capacitor C1 through the first node a, wherein the reset signal Rst is used to control the on and off of the seventh switch T7.
In this embodiment, the first terminal of the first storage capacitor C1 is electrically connected to the second terminal of the first switch T1, the third terminal of the third switch T3, and the third terminal of the fourth switch T4 through the second node Q, and the second terminal is electrically connected to the first terminal of the first switch T1, the third terminal of the second switch T2, the third terminal of the seventh switch T7, and the second terminal of the second storage capacitor C2 through the first node a.
In this embodiment, the first end of the second storage capacitor C2 is electrically connected to the first input voltage VDDA second terminal is electrically connected to the third terminal of the seventh switch T7, and is electrically connected to the first terminal of the first switch T1, the third terminal of the second switch T2, and the second terminal of the first storage capacitor C1 through the first node a.
In this embodiment, the organic light emitting diode OLED has an anode terminal and a cathode terminal, the anode terminal is electrically connected to the third terminal of the fifth switch T5 and the third terminal of the sixth switch T6, and the cathode terminal is electrically connected to a common voltage VSS。
Referring to fig. 4, fig. 4 is a timing diagram of a pixel driving circuit according to an embodiment of the invention. The present invention is achieved by the above7T2C (i.e., seven switches and two storage capacitors) will be applied to the threshold voltage VthThe compensation phase of (2) is separated from the writing phase, so that the compensation phase can not be influenced by the compression compensation time of the high-frequency driving display, and the compensation effect is further kept.
In the present embodiment, the level signal of each signal source goes through four stages, which are a reset stage, a compensation stage, a write stage, and a light-emitting stage. It is understood that the operation of the pixel driving circuit of the present invention can be performed for a plurality of cycles, and each cycle sequentially performs the reset phase, the compensation phase, the write phase, and the emission phase, which is described as a cycle.
In the reset phase, the compensation signal Comp and the reset signal Rst are at a low level (first level), the first enable signal EM1, the second enable signal EM2, and the SCAN signal SCAN are at a high level (second level), which means that the fourth switch T4 and the fifth switch T5 connected to the compensation signal Comp and the seventh switch T7 connected to the reset signal Rst are in an on state, and the first switch T1 to the third switch T3 and the sixth switch T6 are in an off state. At this time, the second input voltage VDD2A voltage value, reference voltage V, is initialized to the first node a through the seventh switch T7refA voltage value, an initial voltage V, is initialized to the second node Q through the fourth switch T4initA voltage value is initialized to the anode terminal of the organic light emitting diode through the fifth switch T5, that is, the voltage V of the first node a during the reset phaseA＝VDD2Voltage V of second node QQ＝VrefThe voltage at the anode terminal of the organic light emitting diode OLED is Vinit. It can be understood that since the first switch T1 is in an open state, it represents the threshold voltage | V of the first switch T1th|>|Vref-VDD2|。
In the compensation phase, the second enable signal EM2 and the compensation signal Comp are at a low level, the first enable signal EM1, the reset signal Rst and the SCAN signal SCAN are at a high level, and the sixth switch T6 connected to the second enable signal EM2 and the compensation signal are indicatedThe fourth switch T4 and the fifth switch T5 of the Comp connection are in an on state, and the second switch T2, the third switch T3, and the seventh switch T7 are in an off state. Based on the fourth switch T4 being in the ON state, the second node Q is initialized to the reference voltage V via the fourth switch T4ref(i.e. V)Q＝Vref). Since the seventh switch T7 is in the off state (the second input voltage V)DD2Unable to write to the first node a) such that the first switch T1 satisfies | Vref-VA|≥|VthI.e. the first switch T1 is turned on, and the first node a is discharged continuously until the voltage difference with the second node Q is the threshold voltage V due to the bootstrap of the first storage capacitor C1thAt this time, the voltage V of the first node AA＝Vref+|VthL. It is understood that, since the present embodiment is described with reference to a P-type thin film transistor, the threshold voltage V isthIs a negative number, therefore | Vth|＝-VthI.e. the voltage V of the first node AAPressure can also be expressed as VA＝Vref-Vth. In addition, the second input voltage V can be changedDD2To adjust the voltage V of the first node a in the compensation phaseAThe range of variation of (a).
In the write phase, the SCAN signal SCAN is low, the first enable signal EM1, the second enable signal EM2, the compensation signal Comp, and the reset signal Rst are high, indicating that the third switch T3 connected to the SCAN signal SCAN is turned on, and the second switch T2 and the fourth to seventh switches T4 to T7 are turned off. Based on the third switch T3 being in the ON state, the second node Q is initialized to the data voltage V through the third switch T3data(i.e. V)Q＝Vdata). Since the first storage capacitor C1 charges the first switch T1, the first switch T1 is also in an on state. At this time, the voltage of the first node a is the sum of the original voltage value (i.e. the voltage of the first node a in the compensation phase) and the voltage variation value of the first node a, i.e. the voltage V of the first node aA＝Vref+|Vth|+△VAWherein the voltage variation value of the first node A is △ VACan be based on "each storage capacitorThe electric quantity of the capacitor is equal to the electric quantity of the equivalent capacitor after series connection, and the total voltage is equal to the sum of the voltages across the two ends of each storage capacitor
Figure BDA0002494267390000101
That is, the voltage of the first node A during the write phase
Figure BDA0002494267390000102
Due to the reference voltage VrefGreater than the data voltage VdataThus the voltage V of the first node A at this stageALess than its voltage value during the compensation phase (i.e. less than V)ref+|Vth|)。
In the light-emitting stage, the first input voltage V is appliedDDThe input current must pass through the first switch T1, the second switch T2, and the sixth switch T6 to make the organic light emitting diode OLED emit light, so at this stage, the first enable signal EM1 and the second enable signal EM2 are set to a low level, the compensation signal Comp, the reset signal Rst, and the SCAN signal SCAN are set to a high level, indicating that the second switch T2 connected to the first enable signal EM1 and the sixth switch T6 connected to the second enable signal EM2 are in an on state, and the third switch T3 to the fifth switch T5 and the seventh switch T7 are in an off state. The first switch T1 is continuously charged based on the first storage capacitor C1, and thus the first switch T1 is also in an open state.
In summary, when the first input voltage V isDDAfter inputting a threshold voltage and a start-up current, the pixel driving circuit in the embodiment of the invention makes the mathematical relation of the current flowing through the organic light emitting diode OLED in the light emitting stage be as follows according to the structure of 7T2C and the high-low level of the matched signal source:
Figure BDA0002494267390000103
Figure BDA0002494267390000104
Figure BDA0002494267390000105
where μ is the carrier mobility, CoxW is the gate width of the TFT, and L is the gate length of the TFT. Therefore, the light emitting current and the threshold voltage V of the pixel driving circuit provided by the invention can be knownthIrrelevant, therefore, the problem of unstable current between pixels is solved.
Further, referring to fig. 5, fig. 5 is a timing diagram of a pixel driving circuit when scanning is performed on a plurality of rows of scanning lines according to an embodiment of the present invention. Since the compensation phase and the write phase are independent processes, the compensation phase and the write phase (as shown by the dotted line in fig. 5) can be performed separately and simultaneously between different scan lines, and the threshold voltage V can be completely correctedthThe compensation is performed without the problem of poor compensation effect caused by the compressed scanning time for performing the high frequency driving display. In addition, only the first storage capacitor is charged in the writing stage, so that the charging time is short, and the invention can be applied to a display panel for high-frequency driving display.
The invention can solve the problem of current instability caused by threshold voltage, and further, the compensation stage of the threshold voltage is separated from the writing stage, so that the compensation stage can not be influenced by the compression compensation time caused by high-frequency driving display, and the compensation effect is further kept.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope of the present invention.

Claims (10)

1. A pixel driving circuit, comprising:
a first switch;
a second switch, a first end of which is electrically connected to the first input voltage, a second end of which is controlled by the first enable signal, and a third end of which is electrically connected to the first end of the first switch through a first node;
a third switch having a first terminal electrically connected to a data voltage having a data signal, a second terminal controlled by a scan signal, and a third terminal electrically connected to the second terminal of the first switch through a second node;
a fourth switch, a first terminal of which is electrically connected to the reference voltage, a second terminal of which is controlled by the compensation signal, and a third terminal of which is electrically connected to the second terminal of the first switch and the third terminal of the third switch through the second node;
a fifth switch, the first end of which is electrically connected to the initial voltage and the second end of which is controlled by the compensation voltage;
a sixth switch, a first terminal of which is electrically connected to the third terminal of the first switch, a second terminal of which is controlled by the second enable signal, and a third terminal of which is electrically connected to the third terminal of the fifth switch;
a seventh switch, a first terminal of which is electrically connected to the second input voltage, a second terminal of which is controlled by the reset signal, and a third terminal of which is connected to the first terminal of the first switch and the third terminal of the second switch through the first node;
an organic light emitting diode having an anode terminal electrically connected to the third terminal of the fifth switch and the third terminal of the sixth switch, and a cathode terminal electrically connected to a common voltage;
a first storage capacitor having a first terminal electrically connected to the second terminal of the first switch, the third terminal of the third switch, and the third terminal of the fourth switch via the second node, and a second terminal electrically connected to the first terminal of the first switch, the third terminal of the second switch, and the third terminal of the seventh switch via the first node; and
a second storage capacitor having a first terminal electrically connected to the first input voltage, a second terminal electrically connected to the third terminal of the seventh switch, and a first terminal of the first switch, a third terminal of the second switch, and a second terminal of the first storage capacitor through the first node.
2. The pixel driving circuit according to claim 1, wherein the timings of the first enable signal, the second enable signal, the compensation signal, the reset signal, and the scan signal are sequentially divided into a reset phase, a compensation phase, a write phase, and a light-emitting phase.
3. The pixel driving circuit according to claim 2, wherein the compensation signal and the reset signal are at a first level, and the first enable signal, the second enable signal, and the scan signal are at a second level during the reset phase.
4. The pixel driving circuit according to claim 3, wherein during the compensation phase, the second enable signal and the compensation signal are at a first level, and the first enable signal, the reset signal, and the scan signal source are at a second level.
5. The pixel driving circuit according to claim 4, wherein during the writing phase, the scan signal is at a first level, and the first enable signal, the second enable signal, the compensation signal, and the reset signal are at a second level.
6. The pixel driving circuit according to claim 5, wherein the first enable signal and the second enable signal are at a first level, and the compensation signal, the reset signal, and the scan signal are at a second level during the light-emitting period.
7. The pixel driving circuit according to claim 3, wherein the voltage V of the first node is in the reset phaseASatisfy the relation: vA＝VDD2Voltage V of the second nodeQSatisfy the relation: vQ＝VrefIn which V isDD2Is the second input voltage, VrefIs the reference voltage.
8. The pixel driving circuit according to claim 7, wherein during the compensation phase, the voltage V at the first node isASatisfy the relation: vA＝Vref+|VthVoltage V of the second nodeQSatisfy the relation: vQ＝VrefIn which V isthIs the threshold voltage.
9. The pixel driving circuit according to claim 8, wherein the voltage V of the first node is at the writing stageASatisfy the relation:
Figure FDA0002494267380000031
Figure FDA0002494267380000032
voltage V of the second nodeQSatisfy the relation: vQ＝VdataIn which V isdataFor the data voltage, C1 is the capacitance value of the first storage capacitor, and C2 is the capacitance value of the second storage capacitor.
10. The pixel driving circuit according to claim 9, wherein the current I flowing through the organic light emitting diodeOLEDSatisfy the relation:
Figure FDA0002494267380000041
where μ is the carrier mobility, CoxW is the gate width of the TFT, and L is the gate length of the TFT.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112071275A (en) * 2020-09-28 2020-12-11 成都中电熊猫显示科技有限公司 Pixel driving circuit and method and display panel
CN112071269A (en) * 2020-09-24 2020-12-11 京东方科技集团股份有限公司 Pixel unit driving circuit, driving method, display panel and display device
CN112992055A (en) * 2021-04-27 2021-06-18 武汉华星光电半导体显示技术有限公司 Pixel circuit and display panel
CN113920926A (en) * 2021-02-26 2022-01-11 友达光电股份有限公司 Pixel driving circuit
CN114120886A (en) * 2021-08-25 2022-03-01 友达光电股份有限公司 Pixel circuit
CN114582288A (en) * 2020-12-01 2022-06-03 乐金显示有限公司 Organic light emitting display device

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