CN113918393B - Memory detection method for functional safety system - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The invention discloses a memory detection method of a functional safety system, which comprises the steps of determining the total bit number of SDRAM one-time burst mode access data in the applied functional safety system; determining the detected data background according to the total bit number of the SDRAM access data in a one-time burst mode; closing a processor cache, judging whether the memory capacity required by the actual operation of the security system is consistent with the actual capacity of SDRAM hardware, performing memory detection according to the actual capacity range of the hardware, otherwise, performing SDRAM access according to the designated capacity, and detecting SDRAM address lines, data lines and data shielding control lines; opening a cache, and performing cache detection; the memory is subjected to periodic segment detection, wherein the detection period and segment size of the SDRAM are determined, a buffer memory is closed, and at least one address line detection, at least one data shielding control line detection and at least one data line detection are performed on the SDRAM; and the cache is opened, and the cache detection is performed at least once, so that the memory detection speed and the system safety are improved.
Description
Technical Field
The invention belongs to the technical field of testing, and particularly relates to a memory detection method of a functional safety system.
Background
The functional safety system requires to detect the memory to prevent the dangerous consequences of the system caused by the memory faults, the memory used by the safety system with high requirement on the computing power is larger at present, and usually an SDRAM memory is adopted, the basic capacity of the SDRAM memory is hundreds of megabytes or even gigabytes, and the full detection usually takes a long time during starting, thus extremely affecting the practical experience of the system and even being unacceptable.
In addition, a high-performance processor generally uses a cache to accelerate the data access performance, if the system does not use the cache, the performance of the processor is seriously reduced, and complex application needs are difficult to meet, when the cache is used, a similar fault mode exists between the cache and a memory, if the cache is not detected, security accidents can be caused by unexpected change of data, and how to comprehensively detect the cache is a technical problem currently.
Disclosure of Invention
In order to solve the technical problems, the invention provides a memory detection method of a functional safety system.
The specific scheme is as follows:
The method comprises the steps of detecting all memories when a security system is started, and detecting the memories in a periodic and sectional mode when the security system is running;
Wherein,
The detection of the entire memory includes the following steps,
S1): determining the total bit number of SDRAM one-time burst mode access data in an applied functional security system;
S2): selecting a RAM detection method, and determining a detected data background according to the total bit number of the SDRAM access data in a one-time burst mode;
S3): closing a processor cache, judging whether the memory capacity required by the actual operation of the security system is consistent with the actual capacity of SDRAM hardware, if so, turning to S4), otherwise, detecting SDRAM by the security system according to the designated capacity by using a selected RAM detection method, turning to S5), wherein the designated capacity is smaller than the actual capacity of SDRAM hardware;
S4): performing memory detection on the SDRAM according to the actual capacity range of hardware according to the selected RAM detection method, and switching to S6 after the detection is completed;
S5): the safety system detects address lines, data lines and data shielding control lines on the SDRAM;
S6): opening a processor cache to perform cache detection;
the periodic segment detection of the memory comprises the following steps:
p1): determining a detection period of SDRAM and a segment size of SDRAM
P2): closing a processor cache, performing memory detection according to the determined SDRAM detection period and the segmentation size of the SDRAM, and performing address line detection, data shielding control line detection and data line detection at least once on the SDRAM at the same time;
p3): and opening the processor cache, and performing cache detection at least once.
The cache detection comprises the following steps:
M1): selecting an address range of the SDRAM according to the capacity of the to-be-detected cache, wherein the address range of the selected SDRAM is consistent with the capacity of the to-be-detected cache;
M2): enabling the cache, reading all data in the address range, and performing memory detection on the address range according to the selected RAM detection method.
During cache detection, in step M2), during memory detection, the data background is selected according to the number of bits of the processor bus width.
Step S2), determining the detection number of the data background according to the maximum bit width B of one access of the memory, wherein the detection number N of the data background and the bit width B accord with a formulaWherein, N is the data background detection number, and B is the data length of each read/write, i.e. bit width.
The data shielding control line detection comprises the following steps:
t1): closing a processor cache, and initializing a memory address of a machine word in SDRAM by taking the width of the machine word as a boundary according to the bus width of the processor, wherein the width of the machine word is equal to the bus width of the processor;
t2): according to the number of bytes contained in the machine word, orderly rewriting byte data, reading the word for checking, and opening a processor cache; the writing of the byte data is performed once in ascending order and descending order, the ascending order writing includes ascending order writing of single byte data and ascending order writing of half word data, and the descending order writing includes descending order writing of single byte data and descending order writing of half word data.
The SDRAM detection period is determined according to the time for completing the detection of the whole memory range once when the system is required to run, and the segmentation size of the SDRAM is determined according to the total capacity of the SDRAM to be detected, the detection interval period and the time for completing the detection of the whole memory range once when the system is required to run.
The invention discloses a memory detection method of a functional safety system, which selects detection capacity according to the requirement of an actual system on memory capacity, improves the use experience of the system, combines the SDRAM characteristics in the memory detection process, carries out rapid and effective comprehensive detection on SDRAM, and provides a detection method for cache, thereby improving the safety of the system and improving the memory detection speed compared with the prior art; the detection capacity can be limited according to the actual system requirement, the hardware adaptability is strong, and the system availability is improved on the premise of meeting the safety. Under the condition of not sacrificing performance, the detection of the cache is increased, and the system safety is improved.
Drawings
Fig. 1 is a schematic flow chart of the present invention.
FIG. 2 is a schematic diagram of a single byte ascending overwrite process.
Fig. 3 is a schematic diagram of a single byte down-sequence rewrite process.
Fig. 4 is a schematic diagram of a half word ascending rewrite process.
Fig. 5 is a schematic diagram of a half word down-order rewrite process.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. It will be apparent to those skilled in the art that the described embodiments are only a part, but not all, of the implementations of the invention, and that all other embodiments, based on which those skilled in the art will come to lie within the scope of the invention without making any inventive effort.
As shown in fig. 1, SDRAM is a dynamic random access memory having a synchronous interface which waits for a clock signal before responding to a control input so that SDRAM can be synchronized with a system bus of a computer, and SDRAM is widely used in the computer.
The method comprises the steps of detecting all memories when a security system is started, and detecting the memories in a periodic and sectional mode when the security system is running;
Wherein,
The detection of the entire memory includes the following steps,
S1): determining the total bit number of SDRAM one-time burst mode access data in an applied functional security system; the burst mode refers to that after addressing and operating one address of the SDRAM is completed, the next address is not required to be addressed again, and the read-write operation of the memory is directly performed, so that the read-write and detection time of the memory is saved;
S2): selecting a RAM detection method, and determining a detected data background according to the total bit number of the SDRAM access data in a one-time burst mode; for those skilled in the art, there are many RAM detection methods, and in this embodiment, the RAM detection is preferably performed by march algorithm;
S3): closing a processor cache, judging whether the memory capacity required by the actual operation of the security system is consistent with the actual capacity of SDRAM hardware, if so, turning to S4), otherwise, detecting SDRAM by the security system according to the designated capacity by using a selected RAM detection method, turning to S5), wherein the designated capacity is smaller than the actual capacity of SDRAM hardware; at this time, the processor cache is closed, so that the real operation of the memory can be realized, and the memory is not affected by the cache when the memory is read or written;
S4): performing memory detection on the SDRAM according to the hardware actual capacity range according to the selected RAM detection method, and switching to S6 after the detection is completed;
S5): the safety system detects address lines, data lines and data shielding control lines on the SDRAM;
S6): opening a processor cache to perform cache detection;
the periodic segment detection of the memory comprises the following steps:
p1): determining a detection period of SDRAM and a segment size of SDRAM
P2): closing a processor cache, performing memory detection according to the determined SDRAM detection period and the segmentation size of the SDRAM, and performing address line detection, data shielding control line detection and data line detection at least once on the SDRAM at the same time; at this time, the periodic segment detection is always performed on the memory in the running process, and the required operation should be applied to the SDRAM memory, so that the cache is closed to ensure the actual operation on the SDRAM memory;
p3): and opening the processor cache, and performing cache detection at least once.
The SDRAM detection period is determined according to the time for completing the detection of the whole memory range once when the system is required to run, and the segmentation size of the SDRAM is determined according to the total capacity of the SDRAM to be detected, the detection interval period and the time for completing the detection of the whole memory range once when the system is required to run.
The cache detection comprises the following steps:
M1): selecting an address range of the SDRAM according to the capacity of the to-be-detected cache, wherein the address range of the selected SDRAM is consistent with the capacity of the to-be-detected cache;
m2): and reading all data in the address range, and performing memory detection on the address range according to the selected RAM detection method.
During cache detection, in step M2), during memory detection, the data background is selected according to the number of bits of the processor bus width.
Step S2), determining the maximum bit width B of one-time access of the data background detection memory, wherein the data background detection number N and the bit width B accord with a formulaWherein, N is the data background detection number, and B is the data length of each read/write, i.e. bit width.
The data shielding control line detection comprises the following steps:
t1): closing a processor cache, and initializing a memory address of a machine word in SDRAM by taking the width of the machine word as a boundary according to the bus width of the processor, wherein the width of the machine word is equal to the bus width of the processor;
t2): according to the number of bytes contained in the machine word, orderly rewriting byte data, reading the word for checking, and opening a processor cache; the writing of the byte data is performed once in ascending order and descending order, the ascending order writing includes ascending order writing of single byte data and ascending order writing of half word data, and the descending order writing includes descending order writing of single byte data and descending order writing of half word data.
In this embodiment, the system processor bus is preferably 32 bits,
The machine word is 32 bits, and the machine word is the number of bits of binary data that can be processed by the computer through one integer operation, and in this embodiment, the number of bits of binary data that can be processed by the security system through one integer operation is 32 bits.
The data format is a small end format. The small end format refers to that high bytes of data are stored in a high address of a memory, and low bytes of data are stored in a low address of the memory;
for a 32-bit processor, one word is equal to four bytes and half is equal to two bytes.
The test SDRAM address is selected to be a 4 integer multiple address, in this embodiment, it is preferable that the address in SDRAM starts from byte a to address a+3 is one word, and since the small-end format is adopted, the high byte of one word is stored in the high address of the memory, that is, in a+3 of this embodiment, the low byte of one word is stored in the low address of the memory, that is, in a+0 of this embodiment.
Fig. 2 (a 0) to (a 4) show a single byte ascending writing process in the memory, specifically:
First, in the stage (a 0) of fig. 2, the processor cache is closed, and the data in the selected address is cleared, that is, all the data in the address range of the word a are written with zeros, and after the writing is completed, the readback check is successful.
Then, in the stage (a 1) of fig. 1, the content of the byte address a+0 is written into 0x55, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x00000055 is detected;
In the stage (a 2) of fig. 2, the content of the byte address a+1 is written into 0xAA, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x0000AA55 is detected;
in the stage (a 3) of fig. 2, the content of the byte address a+2 is written into 0x33, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x0033AA55 is detected;
Finally, in the stage (a 4) of fig. 2, the content of byte address a+2 is written into 0xCC, and at this time, the data content of word a is read out, and whether or not the content of word a is 0xCC AA55 is detected.
Fig. 3 (b 0) to (b 4) show a one-byte writing process in the memory, specifically:
firstly, in the stage (b 0) of fig. 3, setting 1 to the data in the selected address, that is, writing 1 to all the data in the address range of the word a, wherein the hexadecimal content of the word a is 0xFFFFFFFF, after writing, reading back the content of the word a, and detecting whether the content of the word a is 0xFFFFFFFF;
Then, in the stage (b 1) of fig. 3, the content of the byte address a+3 is written into 0x55, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x55FFFFFF is detected;
in the stage (b 2) of fig. 3, the content of the byte address a+2 is written into 0xAA, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x55AAFFFF is detected;
In the stage (b 3) of fig. 3, the content of the byte address a+1 is written into 0x33, and at this time, the data content of the word a is read out, and whether the content of the word a is 0x55AA33FF is detected;
Finally, in the stage (b 4) of fig. 3, the content of byte address a+0 is written into 0xCC, and at this time, the data content of word a is read out, and whether the content of word a is 0x55AA33CC is detected;
in the process of single byte ascending rewrite or single byte descending rewrite, whether the single byte ascending rewrite is consistent with the expected or not is checked after each rewrite, if the single byte ascending rewrite is inconsistent with the expected or not, the detection is ended, the detection error mark is arranged, the system carries out safety processing, and if the single byte ascending rewrite is consistent with the expected, the memory data shielding function is good.
The ascending or descending order refers to the ascending or descending order of the memory addresses in the SDRAM.
Fig. 4 (c 0) to (c 2) illustrate a half word ascending writing process in the memory, in which, in the present embodiment, half words are equal to two bytes, namely, double-byte ascending writing, specifically:
firstly, in the stage (c 0) in fig. 4, performing a zero clearing operation on the content of the memory address word a, and performing a read-back check to determine whether zero clearing is successful;
Then, in the stage (c 1) in fig. 4, the half word write a+0 content is 0x5555, and at this time, the data content of the word a is read out, and whether the word a content is 0x00005555 is detected;
Finally, in the stage (c 2) in fig. 4, the content of the half word write a+2 is 0xAAAA, at this time, the data content of the word a is read out, and whether the content of the word a is 0xAAAA5555 is detected;
Fig. 5 (d 0) to (d 2) show a half word writing process in memory, in which half words are written in a descending order of two bytes, that is, two bytes, specifically:
First, in the stage (d 0) in fig. 5, 0xFFFFFFFF is written to the content of the memory address word a, and the read-back check is performed to determine whether the content is correct;
then, in the stage (d 1) in fig. 5, the half word write a+2 content is 0x3333, and at this time, the data content of the word a is read out, and whether the word a content is 0x3333FFFF is detected;
finally, in the stage (d 2) in fig. 5, the half-word write a+0 content is 0xccc, and at this time, the data content of the word a is read, and whether the word a content is 0x3333CCCC is detected;
In the process of half word ascending-order rewriting or half word descending-order rewriting, whether the half word ascending-order rewriting is consistent with the expected or not is checked after each rewriting, if the half word ascending-order rewriting is inconsistent with the expected or not, detection is finished, an error detection mark is arranged, the system carries out safety processing, and if the half word descending-order rewriting is consistent with the expected, the memory data shielding function is good.
The invention discloses a memory detection method of a functional safety system, which selects detection capacity according to the requirement of an actual system on memory capacity, improves the use experience of the system, combines the SDRAM characteristics in the memory detection process, carries out rapid and effective comprehensive detection on SDRAM, and provides a detection method for cache, thereby improving the safety of the system and improving the memory detection speed compared with the prior art; the detection capacity can be limited according to the actual system requirement, the hardware adaptability is strong, and the system availability is improved on the premise of meeting the safety. Under the condition of not sacrificing performance, the detection of the cache is increased, and the system safety is improved.
The technical means disclosed by the scheme of the invention is not limited to the technical means disclosed by the embodiment, and also comprises the technical scheme formed by any combination of the technical features. It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (2)
1. A memory detection method of a functional safety system is characterized in that:
Detecting all memories when the security system is started, and detecting the memories in a periodical and sectional mode when the security system is running;
Wherein,
The detection of the entire memory includes the following steps,
S1): determining the total bit number of SDRAM one-time burst mode access data in an application function security system;
S2): selecting a RAM detection method, and determining a detected data background according to the total bit number of the SDRAM access data in a one-time burst mode; step S2), determining a data background detection number according to a memory access maximum bit width B, wherein the data background detection number N and the bit width B accord with a formula N=log 2 B +1, N is the data background detection number, and B is the data length of each reading and writing, namely the bit width;
S3): closing a processor cache, judging whether the memory capacity required by the actual operation of the security system is consistent with the actual capacity of SDRAM hardware, if so, turning to S4), otherwise, detecting SDRAM by the security system according to the designated capacity by using a selected RAM detection method, turning to S5), wherein the designated capacity is smaller than the actual capacity of SDRAM hardware;
S4): performing memory detection on the SDRAM according to the actual capacity range of hardware according to the selected RAM detection method, and switching to S6 after the detection is completed;
S5): the safety system detects address lines, data lines and data shielding control lines on the SDRAM; the data shielding control line detection comprises the following steps:
t1): closing a processor cache, and initializing a memory address of a machine word in SDRAM by taking the width of the machine word as a boundary according to the bus width of the processor, wherein the width of the machine word is equal to the bus width of the processor;
t2): according to the number of bytes contained in the machine word, orderly rewriting byte data, reading the word for checking, and opening a processor cache; the writing of the byte data is carried out once according to an ascending order and a descending order, wherein the ascending order writing comprises ascending order writing of single byte data and ascending order writing of half word data, and the descending order writing comprises descending order writing of single byte data and descending order writing of half word data;
S6): opening a processor cache to perform cache detection;
the periodic segment detection of the memory comprises the following steps:
P1): determining the detection period of the SDRAM and the segmentation size of the SDRAM, wherein the detection period of the SDRAM is determined according to the time for completing the detection of the whole memory range once when the system is required to run, and the segmentation size of the SDRAM is determined according to the total capacity of the SDRAM to be detected, the detection interval period of each time and the time for completing the detection of the whole memory range once when the system is required to run;
p2): closing a processor cache, performing memory detection according to the determined SDRAM detection period and the segmentation size of the SDRAM, and performing address line detection, data shielding control line detection and data line detection at least once on the SDRAM at the same time;
P3): opening a processor cache to perform cache detection at least once;
the cache detection comprises the following steps:
M1): selecting an address range of the SDRAM according to the capacity of the to-be-detected cache, wherein the address range of the selected SDRAM is consistent with the capacity of the to-be-detected cache;
M2): enabling the cache, reading all data in the address range, and performing memory detection on the address range according to the selected RAM detection method.
2. The method for detecting the memory of the functional safety system according to claim 1, wherein: during cache detection, in step M2), during memory detection, the data background is selected according to the number of bits of the processor bus width.
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