CN115981569A - Data path scanning method, system, equipment and storage medium - Google Patents
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Abstract
The embodiment of the application provides a data path scanning method, a system, equipment and a storage medium, wherein the method comprises the following steps: determining a first traversal range of the data gating delay value, and determining the size of a first traversal step of the data gating delay value based on the first traversal range; executing a write data strobe training command on the logic unit number in each data strobe channel with each increase of the first traversal step size; writing sample data into the Nand flash memory through the DDR, and reading the sample data into the double-rate synchronous dynamic random access memory; and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment. The data gating delay writing training function finds that a proper data gating delay value cannot be found in a certain logic unit number in a certain channel of the Nand flash memory, which indicates that a data channel has problems, and channel scanning is not needed.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, a system, a device, and a storage medium for data path scanning.
Background
The SSD produced in the same batch may affect the signal quality of a data path between a Nand flash memory and a double-rate synchronous dynamic random access memory due to different PCB qualities, and the read-write function of the SSD is abnormal in severe cases, so that the scanning of the data path and the checking of the abnormal data path are very important.
At present, a method of traversing data strobe delay values is usually adopted for scanning a data path, data written in a Nand flash memory is read, and a proper data strobe delay value is determined through the correctness of data comparison, so that the quality of the data path signal of the Nand flash memory is judged, but the method needs to write a page, namely 16K of data, while traversing each data strobe delay value, and then read the data, and even if the signal quality of the data path is not good and the proper data strobe delay value cannot be found, all the data strobe delay values need to be traversed, which wastes excessive time during data path scanning.
Disclosure of Invention
The embodiment of the application provides a data path scanning method, a data path scanning system, a data path scanning device and a storage medium, which are used for solving the technical problem that excessive time is wasted in scanning in the conventional data path scanning method.
In one aspect, an embodiment of the present application provides a data path scanning method, where the method includes:
setting a first traversal range of the data gating delay value among the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range;
under the condition that the first traversal step length of the data gating delay value is increased once, a write-in data gating training command is executed on the logic unit number in each data gating channel;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
The embodiment of the application provides a method for scanning a Nand flash data path based on write _ dq _ training assistance, which can provide prior information for the Nand flash data path, and the method includes firstly setting a traversal range of a data strobe delay value, executing a write data strobe training command on a logic unit number in each channel every time a traversal step of the data strobe delay value is increased, writing a data sample of a specific Byte into the Nand flash, comparing read data with sample data, recording the data strobe delay value at the moment if data comparison on all logic unit numbers of each channel is successful, and recording all data strobe delay values when data comparison is successful as a data strobe delay value scanning window of the data path until data comparison is unsuccessful.
In one implementation of the present application, the sample data has a size range of 32 bytes to 128 bytes.
In an implementation manner of the present application, the comparing the sample data with the data written based on the written data strobe training command, and if the comparison is successful, after recording a data strobe delay value at this time, the method further includes:
taking the data gating delay value window obtained after the comparison is successful as a second traversal range;
re-traversing the data gating delay value based on the second traversal range, and determining the size of a second traversal step;
and based on the second traversal step, reading the data in the Nand flash memory back to the double-rate synchronous dynamic random access memory.
In an implementation manner of the present application, the reading data in the Nand flash memory back to the double-rate sdram based on the second traversal step length specifically includes:
setting a pattern with a preset size on the double-rate synchronous dynamic random access memory, and writing the pattern into the Nand flash memory through a register write command under the condition that the second traversal step length of the data strobe delay value is increased once;
and reading the data containing the pattern in the Nand flash memory onto the double-rate synchronous dynamic random access memory through a register read command.
In one implementation of the present application, when the pattern is written into the Nand flash memory by the register write command, the size of the write is one Page.
In one implementation of the present application, the method further comprises:
traversing the data gating delay value, and judging whether the read data and the write data are the same;
and if the read data is the same as the write data, the signal quality of a data path of the Nand flash memory is good.
In an implementation manner of the present application, after comparing the sample data with the data written based on the write data strobe training command, the method further includes:
judging whether all channels have data comparison failure on a certain logic unit number;
if the channel data path exists, the channel data path is indicated to have a fault, the scanning of other data paths is stopped, and the fault is reported.
An embodiment of the present application further provides a data path scanning system, where the system includes:
a traversal determination unit for setting a first traversal range of data strobe delay values between the character strings 0x00-0xFF,
and determining a size of a first traversal step size of the data strobe delay value based on the first traversal range;
a command writing unit for executing a write data strobe training command on a logic unit number in each data strobe channel under the condition that the first traversal step length of the data strobe delay value is increased once;
the reading unit is used for writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory and reading the sample data into the double-rate synchronous dynamic random access memory;
a data comparison unit for comparing the sample data with data written based on the write data strobe training command,
if the comparison is successful, the data strobe delay value at the moment is recorded.
An embodiment of the present application further provides a data path scanning device, where the device includes:
at least one processor; and (c) a second step of,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
setting a first traversal range of the data gating delay value between the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
An embodiment of the present application further provides a non-volatile computer storage medium for data path scanning, where a computer-executable instruction is stored, and the computer-executable instruction is set as:
setting a first traversal range of the data gating delay value between the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
According to the data path scanning method, the data path scanning system, the data path scanning equipment and the storage medium, the defect that the time consumption is too long in the existing Nand flash memory data path scanning method is improved, the strategy that priori information can be provided for the Nand flash memory data path scanning according to the data gating delay writing training function is used, data samples are written into a Nand flash memory from a double-rate synchronous dynamic random access memory, then data are read from the Nand flash memory to the double-rate synchronous dynamic random access memory to determine the size of a data gating delay window in advance, then the data gating delay window is used in a traditional data scanning method, if the data gating delay writing training function finds that a certain logic unit number in a certain channel of the Nand flash memory cannot find a proper data gating delay value, the data path is indicated to have problems, the path scanning is not needed, and a large amount of time can be saved in the Nand flash memory data path scanning by using the method, and the working efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flowchart of a data path scanning method according to an embodiment of the present disclosure;
FIG. 2 is a block diagram of a data path scanning system according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a data path scanning apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The SSD produced in the same batch may affect the signal quality of a data path between a Nand flash memory and a double-rate synchronous dynamic random access memory due to different PCB qualities, and the read-write function of the SSD is abnormal in severe cases, so that the scanning of the data path and the checking of the abnormal data path are very important. The latency incurred by Nand flash operations (especially page writes and page erases) is typically hundreds of microseconds or even milliseconds, which is intolerable to many enterprise storage systems. Therefore, how to solve the problem of data response time is very important.
When the host sends a write operation to the solid-state storage device, the device typically returns to the host using a built-in cache, and the write operation is completed when the host writes the write data to the cache. The valid write data in the cache is then written to the NAND flash media using a cache management and erasure mechanism. The mechanism can effectively reduce the write-in delay of the SSD equipment back to the host and solve the problem of write-in data response time.
However, there is never a very effective solution to the data response time of read operations. The read latency of Nand flash memory itself is tens to hundreds of microseconds, which is only the read latency of the medium and acceptable to the host of the storage system. In addition, a complex environment may be encountered where the controller CPU of a solid-state memory device is busy and needs to wait, where Nand flash media is writing pages or erasing pages, or is preceded by a queue of commands that need to wait. Particularly in certain extreme cases, combinations of potentially complex situations are likely to occur. Thus, in these extreme cases, the read latency can be as long as tens or even hundreds of milliseconds, which is a fatal and unacceptable result for the memory system.
Nand flash is a type of non-volatile flash that can provide higher capacity within a given chip size. The Nand flash memory stores by taking pages as basic units and erases by taking blocks as basic units, has high writing and erasing speeds, and is a better storage device than a hard disk drive.
At present, a method of traversing data strobe delay values is usually adopted for scanning a data path, data written into a Nand flash memory are read, and a proper data strobe delay value is determined through the correctness of data comparison, so that the quality of the data path signal of the Nand flash memory is judged, but the method needs to write a page, namely 16K data, while traversing each data strobe delay value, and then read the data, and needs to traverse all the data strobe delay values even if the data path signal quality is not good and the proper data strobe delay value cannot be found, so that excessive time is wasted during data path scanning.
The embodiment of the application provides a data path scanning method, a data path scanning system, a data path scanning device and a storage medium, which are used for solving the technical problem that excessive time is wasted in scanning in the conventional data path scanning method.
The embodiment of the application provides a method for scanning a Nand flash data path based on write _ dq _ training assistance, which can provide prior information for the Nand flash data path, and the method includes firstly setting a traversal range of a data strobe delay value, executing a write data strobe training command on a logic unit number in each channel every time a traversal step of the data strobe delay value is increased, writing a data sample of a specific Byte into the Nand flash, comparing read data with sample data, recording the data strobe delay value at the moment if data comparison on all logic unit numbers of each channel is successful, and recording all data strobe delay values when data comparison is successful as a data strobe delay value scanning window of the data path until data comparison is unsuccessful.
The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 is a flowchart of a data path scanning method according to an embodiment of the present disclosure. As shown in fig. 1, the method mainly comprises the following steps:
step 101, setting a first traversal range of the data gating delay value among the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range.
In the embodiment of the application, a traversal range is needed when the data strobe delay value is traversed, so before this, the traversal range of the data strobe delay value is set, and a first traversal range of the data strobe delay value is set between the character strings 0x00-0 xFF. The size of the first traversal step is then determined.
And 102, under the condition that the first traversal step size of the data strobe delay value is increased once, executing a write data strobe training command on a logic unit number in each data strobe channel.
In the embodiment of the present application, the data strobe value is traversed by the first traversal range and the first traversal step determined in step 101. And monitoring the increase of the first traversal step in real time, and executing a write data strobe training command on the logic unit number in each data strobe channel under the condition that the first traversal step of the data strobe delay value is increased once.
It should be noted that the frequency of the I/O portion of the memory is higher and higher, and the higher frequency allows a small error to be amplified. The clock constraint of high-speed signal wiring is very strict, a group of high-speed signals bends on a mainboard, the lengths of routing of an inner ring and an outer ring can generate a difference, although the routing lengths are very small and low-speed signals do not have a relation, the clock constraint of the high-speed signals cannot be achieved, and the high-speed signals must be bent back in the opposite direction to compensate. The reason for training the memory is that the frequency of G on the memory I/O frequency, so that any small errors must be compensated for, is aligned and compensated for over the entire data link.
In the embodiment of the application, a data strobe training command is written on the logic unit number in each data strobe channel, sample data is written into the Nand flash memory through the double-rate synchronous dynamic random access memory, the data is read into the double-rate synchronous dynamic random access memory, and then the data is compared with the written data.
The sample data has a size range of 32 bytes to 128 bytes.
And step 104, comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
In the embodiment of the application, the data gating delay value window obtained after the comparison is successful is used as a second traversal range; re-traversing the data gating delay value based on the second traversal range, and determining the size of a second traversal step; and based on the second traversal step, reading the data in the Nand flash memory back to the double-rate synchronous dynamic random access memory.
In the embodiment of the application, whether data comparison failure on a certain logic unit number exists in all channels is judged; if the channel data path exists, the channel data path is indicated to have a fault, the scanning of other data paths is stopped, and the fault is reported. If the data gating delay writing training function finds that a proper data gating delay value cannot be found in a certain logic unit number in a certain channel of the Nand flash memory, the problem of a data path is solved, path scanning is not needed, a large amount of time can be saved in the Nand flash memory data path scanning by using the method, and the working efficiency is improved.
The reading the data in the Nand flash memory to the double-rate synchronous dynamic random access memory again based on the second traversal step length specifically comprises: setting a pattern with a preset size on the double-rate synchronous dynamic random access memory, and writing the pattern into the Nand flash memory through a register write command under the condition that the second traversal step length of the data strobe delay value is increased once; and reading the data containing the pattern in the Nand flash memory onto the double-rate synchronous dynamic random access memory through a register read command.
It should be noted that, when the pattern is written into the Nand flash memory by the register write command, the size of the write is one Page, i.e., 16KB.
In the embodiment of the application, the process of verifying the signal quality of the data path of the Nand flash memory comprises the following steps: traversing the data gating delay value, and judging whether the read data and the write data are the same; and if the read data is the same as the write data, the signal quality of a data path of the Nand flash memory is good.
According to the data gating delay writing training method, the defect that the time consumption is too long in the existing Nand flash memory data path scanning method is overcome, the data sample is written into a Nand flash memory from a double-rate synchronous dynamic random access memory according to a strategy that a data gating delay writing training function can provide prior information for Nand flash memory data path scanning, then data are read from the Nand flash memory to the double-rate synchronous dynamic random access memory to determine the size of a data gating delay window in advance, then the data gating delay window is used in a traditional data scanning method, if the data gating delay writing training function finds that a logic unit number in a certain channel of the Nand flash memory cannot find a proper data gating delay value, the data path is problematic, path scanning is not needed, and a large amount of time can be saved in Nand flash memory data path scanning by using the method, and the working efficiency is improved.
Based on the same inventive concept, the embodiment of the present application further provides a data path scanning system, as shown in fig. 2, fig. 2 is a composition diagram of the data path scanning system provided in the embodiment of the present application, and in fig. 2, the system mainly includes:
the traversal determining unit 201 is configured to set a first traversal range of the data strobe delay value between the character strings 0x00-0xFF, and determine a size of a first traversal step of the data strobe delay value based on the first traversal range;
a command writing unit 202 for executing a write data strobe training command on a logic unit number in each data strobe channel in a case where the first traversal step size of the data strobe delay value is increased once;
the reading unit 203 is configured to write sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and read the sample data into the double-rate synchronous dynamic random access memory;
and the data comparison unit 204 is configured to compare the sample data with the data written based on the write data strobe training command, and record a data strobe delay value at this time if the comparison is successful.
In the embodiment of the application, the data comparison unit is further configured to determine whether all channels have data comparison failure on a certain logical unit number; if the channel data path exists, the channel data path is indicated to have a fault, the scanning of other data paths is stopped, and the fault is reported. If the data gating delay writing training function finds that a proper data gating delay value cannot be found in a certain logic unit number in a certain channel of the Nand flash memory, the problem of a data channel is solved, channel scanning is not needed, a large amount of time can be saved in the process of scanning the data channel of the Nand flash memory by using the method, and the working efficiency is improved.
According to the data channel scanning system provided by the embodiment of the application, the defect that the time consumption is too long in the existing Nand flash memory data channel scanning method is improved, according to the strategy that the data gating delay writing training function can provide prior information for the Nand flash memory data channel scanning, data samples are written into a Nand flash memory from a double-rate synchronous dynamic random access memory, then data are read from the Nand flash memory to the double-rate synchronous dynamic random access memory, the size of a data gating delay window is determined in advance, then the data gating delay window is used in the traditional data scanning method, if the data gating delay writing training function finds that a logic unit number in a certain channel of the Nand flash memory cannot find a proper data gating delay value, the data channel has a problem, channel scanning is not needed, and by using the method, a large amount of time can be saved in the Nand flash memory data channel scanning, and the working efficiency is improved.
The above is a data path scanning system provided in an embodiment of the present application, and based on the same inventive concept, an embodiment of the present application further provides a data path scanning device, and fig. 3 is a schematic diagram of the data path scanning device provided in the embodiment of the present application, and as shown in fig. 3, the device mainly includes: at least one processor 301; and a memory 302 communicatively coupled to the at least one processor; wherein the memory 302 stores instructions executable by the at least one processor 301, the instructions being executable by the at least one processor 301 to enable the at least one processor 301 to:
setting a first traversal range of the data gating delay value between the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
According to the data channel scanning device provided by the embodiment of the application, the defect that the time consumption is too long in the existing Nand flash memory data channel scanning method is improved, according to the strategy that the data gating delay writing training function can provide prior information for the Nand flash memory data channel scanning, data samples are written into a Nand flash memory from a double-rate synchronous dynamic random access memory, then data are read from the Nand flash memory to the double-rate synchronous dynamic random access memory, the size of a data gating delay window is determined in advance, then the data gating delay window is used in the traditional data scanning method, if the data gating delay writing training function finds that a logic unit number in a certain channel of the Nand flash memory cannot find a proper data gating delay value, the data channel has a problem, channel scanning is not needed, and by using the method, a large amount of time can be saved in the Nand flash memory data channel scanning, and the working efficiency is improved.
In addition, an embodiment of the present application further provides a non-volatile computer storage medium for data path scanning, which stores computer-executable instructions configured to:
setting a first traversal range of the data gating delay value between the character strings 0x00-0xFF, and determining the size of a first traversal step size of the data gating delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on differences from other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "...," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A method for datapath scanning, the method comprising:
determining a first traversal range of a data strobe delay, and determining a size of a first traversal step of the data strobe delay based on the first traversal range;
under the condition that the first traversal step size is gradually increased, writing the data gating training command on the logic unit number in each data gating channel;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written in by the training command, and if the comparison is successful, recording a numerical value corresponding to the data gating delay at the moment.
2. The method of claim 1, wherein the sample data has a size range of 32 bytes to 128 bytes.
3. A data path scanning method as claimed in claim 1, further comprising:
taking the corresponding numerical value as a second traversal range;
re-traversing the data gating delay based on the second traversal range, and determining the size of a second traversal step;
and based on the second traversal step, reading the data in the Nand flash memory back to the double-rate synchronous dynamic random access memory.
4. The method according to claim 3, wherein the reading data in the Nand flash memory back to the ddr sdram based on the second traversal step size comprises:
setting a pattern with a preset size on the double-rate synchronous dynamic random access memory, and writing the pattern into the Nand flash memory through a register write command under the condition that the second traversal step length of data strobe delay is increased once;
and reading the data containing the pattern in the Nand flash memory onto the double-rate synchronous dynamic random access memory through a register read command.
5. The datapath scanning method of claim 4, wherein the writing of the pattern to the Nand flash memory by the register write command is one page in size.
6. A method for datapath scanning according to claim 1, further comprising:
traversing the data gating delay, and judging whether the read data and the write data are the same;
and if the read data is the same as the write data, the signal quality of a data path of the Nand flash memory is good.
7. A method for datapath scanning according to claim 1, further comprising:
judging whether all channels have data comparison failure on a certain logic unit number;
if the channel data path exists, the channel data path is indicated to have a fault, the scanning of other data paths is stopped, and the fault is reported.
8. A data path scanning system, the system comprising:
the traversal determination unit is used for determining a first traversal range of the data gating delay and determining the size of a first traversal step of the data gating delay based on the first traversal range;
a command writing unit for executing a writing data strobe training command on a logic unit number in each data strobe channel in a case where a first traversal step of the data strobe delay is increased once;
the reading unit is used for writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory and reading the sample data into the double-rate synchronous dynamic random access memory;
and the data comparison unit is used for comparing the sample data with the data written based on the written data gating training command, and recording the data gating delay value at the moment if the comparison is successful.
9. A data path scanning device, characterized in that the device comprises:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to cause the at least one processor to:
determining a first traversal range of a data strobe delay, and determining a size of a first traversal step size of the data strobe delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
10. A non-transitory computer storage medium having stored thereon computer-executable instructions configured to:
determining a first traversal range of a data strobe delay, and determining a size of a first traversal step size of the data strobe delay value based on the first traversal range;
executing a write data strobe training command on a logic cell number in each data strobe channel with each increase in the first traversal step size of the data strobe delay value;
writing sample data into the Nand flash memory through the double-rate synchronous dynamic random access memory, and reading the sample data onto the double-rate synchronous dynamic random access memory;
and comparing the sample data with the data written based on the written data gating training command, and if the comparison is successful, recording the data gating delay value at the moment.
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| CN202310018741.1A CN115981569A (en) | 2023-01-06 | 2023-01-06 | Data path scanning method, system, equipment and storage medium |
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