CN113904748A - Clock synchronization method, system, device and medium - Google Patents
Clock synchronization method, system, device and medium Download PDFInfo
- Publication number
- CN113904748A CN113904748A CN202111118806.7A CN202111118806A CN113904748A CN 113904748 A CN113904748 A CN 113904748A CN 202111118806 A CN202111118806 A CN 202111118806A CN 113904748 A CN113904748 A CN 113904748A
- Authority
- CN
- China
- Prior art keywords
- clock
- clock source
- source
- effective
- data packets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000001360 synchronised effect Effects 0.000 claims abstract description 19
- 230000004044 response Effects 0.000 claims description 20
- 230000008859 change Effects 0.000 claims description 11
- 238000001514 detection method Methods 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 8
- 238000004458 analytical method Methods 0.000 abstract description 6
- 238000004364 calculation method Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004422 calculation algorithm Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a clock synchronization method, which comprises the following steps: acquiring a plurality of clock signals and detecting whether each clock signal is effective or not; responding to the validity of the clock source signal, and sequentially adding the clock sources corresponding to the valid clock signals into an effective clock source table according to a preset priority order; and sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal. The invention also discloses a system, a computer device and a readable storage medium. According to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
Description
Technical Field
The present invention relates to the field of clock synchronization, and in particular, to a clock synchronization method, system, device, and storage medium.
Background
With the development of technologies such as 5G, Internet of things and the like, the data volume is exponentially increased, the data cannot be analyzed and processed immediately only by cloud computing, more and more data need to be stored, analyzed and processed at the network edge, a large amount of edge computing depends on a clock, and the clock precision is higher. The problem of clock synchronization of edge servers is therefore becoming an increasingly important issue.
At present, most clock synchronization researches are mainly applied to base stations, internet of things equipment and the like, the researches on the clock synchronization of servers, particularly edge servers are lacked, and in the aspect of clock synchronization mode selection, the clock synchronization researches can only be manually configured, and an automatic selection optimization method is lacked.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a clock synchronization method, including:
acquiring a plurality of clock signals and detecting whether each clock signal is effective or not;
responding to the validity of the clock source signal, and sequentially adding the clock sources corresponding to the valid clock signals into an effective clock source table according to a preset priority order;
and sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a clock synchronization system, including:
a detection module configured to acquire a plurality of clock signals and detect whether each clock signal is valid;
the adding module is configured to respond to the validity of the clock source signals and sequentially add the clock sources corresponding to the valid clock signals to the valid clock source table according to a preset priority order;
and the synchronization module is configured to send the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronization clock signal.
In some embodiments, the detection module is further configured to:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, the detection module is further configured to:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising a phase-locked loop module configured to:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:
acquiring a plurality of clock signals and detecting whether each clock signal is effective or not;
responding to the validity of the clock source signal, and sequentially adding the clock sources corresponding to the valid clock signals into an effective clock source table according to a preset priority order;
and sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of:
acquiring a plurality of clock signals and detecting whether each clock signal is effective or not;
responding to the validity of the clock source signal, and sequentially adding the clock sources corresponding to the valid clock signals into an effective clock source table according to a preset priority order;
and sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
The invention has one of the following beneficial technical effects: according to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a clock synchronization method according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a clock synchronization system according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a clock synchronization method, as shown in fig. 1, which may include the steps of:
s1, acquiring a plurality of clock signals and detecting whether each clock signal is effective;
s2, responding to the validity of the clock source signal, sequentially adding the clock source corresponding to the valid clock signal into the valid clock source table according to the preset priority order;
and S3, sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
According to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
In some embodiments, in step S1, a plurality of clock signals are obtained, specifically, the plurality of clock signals may be NTP network clocks, 1588 clocks, GPS clocks, and synchronous clock signals sent by other edge servers, where the NTP network clocks perform time information transmission through a network, the 1588 clocks perform clock synchronization through an ethernet card, and the GPS clocks perform clock synchronization by generating pulse-per-second signals and time information. The synchronization clock signals sent by other edge servers may be GPS clock signals or 1588 clock signals, when other edge servers select a clock signal generated by a GPS clock source as a synchronization signal, the clock signal sent by the other edge servers is a GPS clock signal, and if the clock signal generated by the 1588 clock source is selected as the synchronization signal, the clock signal sent by the other edge servers is a 1588 clock signal.
Firstly, initializing a clock source, setting an NTP network server, and accessing the NTP network server to an edge server network; a 1588 clock source generating device is arranged, so that a server or a corresponding instrument can be accessed to an edge server network in the same way; the GPS clock source device is connected to one of the edge servers.
It should be noted that initially different edge servers may detect different clock signals initially, for example, some edge servers may not be able to detect the GPS clock signal.
In some embodiments, in step S2, a priority order is preset for each clock source, specifically, the highest precision clock source GPS always exists in the first position of the table, the 1588 clock source GPS always exists in the second position of the table, the NTP network clock is the third position, and the first effective clock source is always selected as the synchronization source for clock synchronization.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
Specifically, whether the level change of a 1PPS signal (pulse signal) accords with a preset rule or not is detected, whether the GPS is effective or not is judged, and if the GPS is effective, a GPS clock source is placed at the head of an effective clock source;
determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether the time intervals in a plurality of data packets are stable, and if so, adding the 1588 clock source to a second position of an effective clock source table;
detecting whether the NTP server is unobstructed, and if the NTP server is unobstructed, adding the NTP network clock source to the third position of the effective clock source table;
therefore, whether the effective clock source table is empty or not is judged, if the effective clock source table is empty, waiting is carried out, if the effective clock source table is not empty, a first clock source is selected, the clock is synchronized to the local, circulation is carried out, and the first effective clock source is always selected for clock synchronization.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
Specifically, as a large number of 1588 clock synchronization information packets exist in the network, the automatic screening function is added, and effective and most accurate clock signals can be automatically screened out.
In some embodiments, the automated screening step may be as follows:
adding hash table and initializing the hash table
Monitoring a clock synchronization information packet of a network, and filtering out non-clock information packets;
detecting the integrity of the packets aiming at the clock synchronization information packets, grouping the packets with the integrity according to sources, distributing the packets into a hash table according to the sources, and recording timestamps in the packets;
when a synchronous packet from the same source is received next time, clock differences are recorded, and the operation is repeated, so that a group of time differences from the same source can be collected;
judging the time difference, if the interval is not stable, it indicates that the source is in synchronization and the clock signal is not accurate, otherwise, it is more stable
A stable set of clock signals is selected, and other non-stable signals are filtered out, and a loop is entered to select the stable set of clock signals all the time.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
In particular, a phase locked loop is a feedback circuit that functions to synchronize the phase of a clock on the circuit with some external clock. The PLL realizes synchronization by comparing the phase of the external signal with the phase of the voltage-controlled crystal oscillator, and in the comparison process, the phase-locked loop circuit can continuously adjust the clock phase of the local crystal oscillator according to the phase of the external signal until the phases of the two signals are synchronized. And introducing a phase-locked loop chip, and transmitting the signal to the phase-locked loop chip after the clock source selection module selects the optimal clock signal, so that the clock of the phase-locked loop is synchronous with the external optimal clock. In the whole module, an external clock source is continuously detected, and when no effective clock source exists, a clock source output signal in a phase-locked loop is temporarily used as a new clock source to eliminate system clock errors, so that the clock progress is kept for a long time. And an alarm is set, and the information of the clock source lack is fed back to the maintenance personnel, so that the maintenance personnel can process the information in time.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a clock synchronization system 400, as shown in fig. 2, including:
a detection module 401 configured to acquire a plurality of clock signals and detect whether each clock signal is valid;
an adding module 402 configured to respond to the validity of the clock source signal, and sequentially add the clock source corresponding to the valid clock signal to the valid clock source table according to a preset priority order;
and a synchronization module 403 configured to send a clock signal corresponding to a first clock source in the valid clock source table to another server as a synchronization clock signal.
In some embodiments, the detection module 401 is further configured to:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, the detection module 401 is further configured to:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising a phase-locked loop module configured to:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
According to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
a memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform the steps of:
s1, acquiring a plurality of clock signals and detecting whether each clock signal is effective;
s2, responding to the validity of the clock source signal, sequentially adding the clock source corresponding to the valid clock signal into the valid clock source table according to the preset priority order;
and S3, sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
According to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the following steps:
s1, acquiring a plurality of clock signals and detecting whether each clock signal is effective;
s2, responding to the validity of the clock source signal, sequentially adding the clock source corresponding to the valid clock signal into the valid clock source table according to the preset priority order;
and S3, sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
In some embodiments, detecting whether each clock signal is valid further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
In some embodiments, determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
In some embodiments, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
According to the scheme provided by the invention, the clock effectiveness and precision analysis is carried out on the multi-channel clock synchronization source of the edge server, the high-precision clock is automatically selected and synchronized into the current system, and the high-precision clock is kept and adjusted and output, so that each edge server in the area can keep high-precision clock synchronization at the same time, and the time reliability is provided for the edge calculation accuracy.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of clock synchronization, comprising the steps of:
acquiring a plurality of clock signals and detecting whether each clock signal is effective or not;
responding to the validity of the clock source signal, and sequentially adding the clock sources corresponding to the valid clock signals into an effective clock source table according to a preset priority order;
and sending the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronous clock signal.
2. The clock synchronization method of claim 1, wherein detecting whether each clock signal is valid, further comprises:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
3. The method of claim 2, wherein determining whether the 1588 multicast packet generated by the 1588 clock source is valid by detecting whether a time interval size in a plurality of packets is stable, further comprises:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
4. The method of claim 1, further comprising:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
5. A clock synchronization system, comprising:
a detection module configured to acquire a plurality of clock signals and detect whether each clock signal is valid;
the adding module is configured to respond to the validity of the clock source signals and sequentially add the clock sources corresponding to the valid clock signals to the valid clock source table according to a preset priority order;
and the synchronization module is configured to send the clock signal corresponding to the first clock source in the effective clock source table to other servers as a synchronization clock signal.
6. The clock synchronization system of claim 5, wherein the detection module is further configured to:
responding to that a clock source corresponding to a clock signal is a GPS clock source, and determining whether a pulse signal generated by the GPS clock source is effective or not by detecting whether the level change of the pulse signal accords with a preset rule or not;
responding to a clock source corresponding to a clock signal as a 1588 clock source, and determining whether a 1588 multicast data packet generated by the 1588 clock source is valid by detecting whether time intervals in a plurality of data packets are stable;
responding to the fact that a clock source corresponding to the clock signal is an NTP clock source, and determining whether the clock signal generated by the NTP clock source is effective or not by detecting whether the clock source can be connected with an NTP server or not.
7. The system of claim 6, wherein the detection module is further configured to:
in response to receiving data packets corresponding to a plurality of 1588 clock sources, grouping the data packets according to different 1588 clock sources and recording timestamps in the data packets;
responding to the data packets sent by the same 1588 clock source received again, calculating the time interval between the data packets and the last time of receiving the data packets, and repeating the time interval for multiple times to obtain a group of time differences corresponding to each 1588 clock source;
and determining whether the 1588 multicast data packet generated by the 1588 clock source is valid according to whether the time interval size in a group of time differences corresponding to each 1588 clock source is stable.
8. The system of claim 5, further comprising a phase-locked loop module configured to:
transmitting a clock signal corresponding to a first clock source to a phase-locked loop so as to synchronize a clock source in the phase-locked loop by using the clock signal corresponding to the first clock source;
and in response to the effective clock source table not having an effective clock source, taking the clock source in the phase-locked loop as a new clock source.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, characterized in that the processor executes the program to perform the steps of the method according to any of claims 1-4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111118806.7A CN113904748A (en) | 2021-09-24 | 2021-09-24 | Clock synchronization method, system, device and medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111118806.7A CN113904748A (en) | 2021-09-24 | 2021-09-24 | Clock synchronization method, system, device and medium |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113904748A true CN113904748A (en) | 2022-01-07 |
Family
ID=79029068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111118806.7A Pending CN113904748A (en) | 2021-09-24 | 2021-09-24 | Clock synchronization method, system, device and medium |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113904748A (en) |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006099312A (en) * | 2004-09-29 | 2006-04-13 | Hitachi Kokusai Electric Inc | Clock generator |
CN101719837A (en) * | 2009-11-25 | 2010-06-02 | 华为技术有限公司 | Clock board, network system suitable for server and clock switching method |
JP2010161708A (en) * | 2009-01-09 | 2010-07-22 | Nec Corp | Apparatus, method and program for clock selection |
CN101902321A (en) * | 2010-08-13 | 2010-12-01 | 中兴通讯股份有限公司 | Clock management method and system |
US20120087453A1 (en) * | 2009-06-25 | 2012-04-12 | Zte Corporation | Method for selecting clock source in synchronization digital hierarchy network |
CN103248445A (en) * | 2012-02-09 | 2013-08-14 | 中兴通讯股份有限公司 | Clock synchronization method and device |
US20160301416A1 (en) * | 2015-04-08 | 2016-10-13 | Microsemi Semiconductor Ulc | Digital Phase Locked Loop Arrangement with Master Clock Redundancy |
CN106685566A (en) * | 2016-12-31 | 2017-05-17 | 上海远景数字信息技术有限公司 | Clock source selection method and clock server |
CN106707736A (en) * | 2015-11-17 | 2017-05-24 | 惠州市德赛西威汽车电子股份有限公司 | Automobile instrument clock precision measuring method and automobile instrument clock precision measuring device |
CN107528654A (en) * | 2016-06-21 | 2017-12-29 | 中兴通讯股份有限公司 | It is a kind of based on 1588 method for synchronizing time and device |
CN108064080A (en) * | 2018-01-02 | 2018-05-22 | 京信通信***(中国)有限公司 | The clock synchronizing method and device of base station equipment |
CN110830141A (en) * | 2019-11-26 | 2020-02-21 | 北京小马智行科技有限公司 | Time synchronization method, system, storage medium and processor |
CN111148211A (en) * | 2019-12-31 | 2020-05-12 | 京信通信***(中国)有限公司 | Clock synchronization method and device, computer equipment and storage medium |
CN112020133A (en) * | 2020-07-29 | 2020-12-01 | 苏州浪潮智能科技有限公司 | Edge calculation server design method for multi-strategy high-precision clock synchronization |
CN112398568A (en) * | 2020-11-24 | 2021-02-23 | 广东省新一代通信与网络创新研究院 | System and method for synchronizing clocks in multiple cells |
CN112713952A (en) * | 2020-11-28 | 2021-04-27 | 苏州浪潮智能科技有限公司 | Clock synchronization card and server |
CN112929122A (en) * | 2021-04-26 | 2021-06-08 | 新石器慧通(北京)科技有限公司 | Time synchronization method and device, terminal equipment and computer readable storage medium |
-
2021
- 2021-09-24 CN CN202111118806.7A patent/CN113904748A/en active Pending
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006099312A (en) * | 2004-09-29 | 2006-04-13 | Hitachi Kokusai Electric Inc | Clock generator |
JP2010161708A (en) * | 2009-01-09 | 2010-07-22 | Nec Corp | Apparatus, method and program for clock selection |
US20120087453A1 (en) * | 2009-06-25 | 2012-04-12 | Zte Corporation | Method for selecting clock source in synchronization digital hierarchy network |
CN101719837A (en) * | 2009-11-25 | 2010-06-02 | 华为技术有限公司 | Clock board, network system suitable for server and clock switching method |
CN101902321A (en) * | 2010-08-13 | 2010-12-01 | 中兴通讯股份有限公司 | Clock management method and system |
CN103248445A (en) * | 2012-02-09 | 2013-08-14 | 中兴通讯股份有限公司 | Clock synchronization method and device |
US20160301416A1 (en) * | 2015-04-08 | 2016-10-13 | Microsemi Semiconductor Ulc | Digital Phase Locked Loop Arrangement with Master Clock Redundancy |
CN106707736A (en) * | 2015-11-17 | 2017-05-24 | 惠州市德赛西威汽车电子股份有限公司 | Automobile instrument clock precision measuring method and automobile instrument clock precision measuring device |
CN107528654A (en) * | 2016-06-21 | 2017-12-29 | 中兴通讯股份有限公司 | It is a kind of based on 1588 method for synchronizing time and device |
CN106685566A (en) * | 2016-12-31 | 2017-05-17 | 上海远景数字信息技术有限公司 | Clock source selection method and clock server |
CN108064080A (en) * | 2018-01-02 | 2018-05-22 | 京信通信***(中国)有限公司 | The clock synchronizing method and device of base station equipment |
CN110830141A (en) * | 2019-11-26 | 2020-02-21 | 北京小马智行科技有限公司 | Time synchronization method, system, storage medium and processor |
CN111148211A (en) * | 2019-12-31 | 2020-05-12 | 京信通信***(中国)有限公司 | Clock synchronization method and device, computer equipment and storage medium |
CN112020133A (en) * | 2020-07-29 | 2020-12-01 | 苏州浪潮智能科技有限公司 | Edge calculation server design method for multi-strategy high-precision clock synchronization |
CN112398568A (en) * | 2020-11-24 | 2021-02-23 | 广东省新一代通信与网络创新研究院 | System and method for synchronizing clocks in multiple cells |
CN112713952A (en) * | 2020-11-28 | 2021-04-27 | 苏州浪潮智能科技有限公司 | Clock synchronization card and server |
CN112929122A (en) * | 2021-04-26 | 2021-06-08 | 新石器慧通(北京)科技有限公司 | Time synchronization method and device, terminal equipment and computer readable storage medium |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN113711510B (en) | Phase predictor and associated method of use | |
WO2018137548A1 (en) | Clock synchronization device and method | |
CN103563287B (en) | Synchronization device and synchronization method | |
WO2021047313A1 (en) | Clock delay detection method and apparatus, clock delay compensation method and apparatus, terminal, and readable storage medium | |
EP2871494B1 (en) | Phase-alignment between clock signals | |
CN111385050B (en) | Clock synchronization method, device and storage medium | |
CN111385051B (en) | Clock synchronization method, device and storage medium | |
CN109600186A (en) | Clock synchronizing method and device | |
CN115987477A (en) | Multi-reference source time synchronization method, system, module and medium | |
CN110089120B (en) | System and method for synchronized playback of media items on multiple remote devices | |
JPH087947B2 (en) | Device for recovering channel-clock information and data recovery circuit comprising this device | |
US8294501B1 (en) | Multiphase clock generation and calibration | |
CN113904748A (en) | Clock synchronization method, system, device and medium | |
CN111464254B (en) | Clock synchronization method and device and electronic equipment | |
CN112838860B (en) | Data output method, device and system | |
CN107154800B (en) | Detection system and detection method for phase-locked loop losing lock | |
WO2017008677A1 (en) | Data detection method and device | |
CA2389969A1 (en) | Digital signal processing of multi-sampled phase | |
CN116131984A (en) | Reference time determining method and device, electronic equipment and storage medium | |
CN112019288B (en) | Time synchronization method, service single board and network equipment | |
CN110515907B (en) | Data synchronization method and related device for distributed storage nodes | |
JP6312772B1 (en) | Phase difference estimation device and communication device including the phase difference estimation device | |
CN106209032B (en) | Straddle clock source frequency deviation detection device and method based on single High Precision Crystal Oscillator | |
CN110572233B (en) | Time keeping method and device using NTP (network time protocol) as auxiliary source | |
CN114070762B (en) | Network monitoring probe assembly, synchronization method and data acquisition and analysis device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |