CN113903794A - 包含沟槽栅的半导体器件的制备方法及半导体器件 - Google Patents
包含沟槽栅的半导体器件的制备方法及半导体器件 Download PDFInfo
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Abstract
本发明公开了提供一种包含沟槽栅的半导体器件的制备方法,包含以下步骤:1)在半导体衬底上形成外延层,在外延层中形成沟槽;2)对外延层的上表面和沟槽的内壁进行蚀刻,使沟槽的顶部的直径大于沟槽的底部的直径;3)在外延层的上表面和沟槽的内壁与底部形成屏蔽氧化层;以及4)在沟槽内填充多晶硅以形成沟槽栅。该方法有效消除沟槽栅中的缝隙。本发明同时提供一种使用上述方法制备的半导体器件。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种包含沟槽栅的半导体器件的制备方法及使用该方法制备的半导体器件。
背景技术
基于沟槽技术的功率场效应晶体管(Power MOSFET)的制备过程通常包含如图1所示的以下步骤:基于掩模层以蚀刻的方式在衬底001上方的外延层002上形成沟槽003(参见图2a)——去除掩模层并在沟槽003的表面及外延层002的顶面形成屏蔽氧化层004(参见图2b)——向沟槽003内填充多晶硅002以形成沟槽栅(参见图2c)。然而,对于深宽比较大的沟槽而言,常常会由于多晶硅005填充能力不足等原因在沟槽栅的中间部位形成缝隙006,严重者会贯穿整个沟槽003,导致后续工艺无法顺利进行并影响器件性能。
因此,如何消除沟槽栅中的缝隙成为半导体器件制备领域亟待解决的技术问题。
发明内容
为了解决现有的技术问题,本发明提出了一种有效消除沟槽栅中的缝隙半导体器件的制备方法及使用该方法制备的半导体器件。
依据本发明,提供一种包含沟槽栅的半导体器件的制备方法,包含以下步骤:
1)在半导体衬底上形成外延层,在外延层中形成沟槽;
2)对外延层的上表面和沟槽的内壁进行蚀刻,使沟槽的顶部的直径大于沟槽的底部的直径;
3)在外延层的上表面和沟槽的内壁与底部形成屏蔽氧化层;以及
4)在沟槽内填充多晶硅以形成沟槽栅。
依据本发明的一个实施例,步骤1)包含基于外延层上方的掩模层在外延层上形成沟槽,以及去除掩模层。
依据本发明的一个实施例,步骤2)包含:2.1)对外延层的上表面进行干蚀刻,使邻近外延层的上表面的沟槽的内壁形成第一倾斜面,第一倾斜面环绕的区域构成直径大于沟槽的底部直径的开口。
依据本发明的一个实施例,步骤2)包含:
2.2)在外延层的上表面和沟槽的内壁与底部形成牺牲氧化层;
2.3)去除牺牲氧化层,以使开口扩大并使开口以外的内壁形成第二倾斜面,第二倾斜面环绕的区域的直径自沟槽的底部至沟槽的顶部逐渐增大。
依据本发明的一个实施例,第一倾斜面与竖直方向构成第一夹角,第一夹角为30-60°。
依据本发明的一个实施例,第二倾斜面与竖直方向构成第二夹角,第二夹角的斜率为1:30~1:20。
依据本发明的一个实施例,制备方法包含:步骤5)对半导体器件进行退火处理。
依据本发明的一个实施例,退火处理包含将沟槽栅加热至800-1000℃。
依据本发明,提供一种使用上述方法制备的半导体器件。
由于采用以上技术方案,本发明与现有技术相比具有如下优点:
1.本发明通过增加干蚀刻在沟槽顶部形成直径大于沟槽底部的开口,并通过牺牲氧化层使沟槽直径沿着远离底部的方向逐渐增大,改善了沟槽的总体轮廓,降低多晶硅在填充过程中于沟槽顶部过早闭合的可能性,减小了在沟槽栅中部形成缝隙的几率;
2.即使形成缝隙,还可通过后期退火工艺使多晶硅内部材料均匀化,将缝隙消除。
附图说明
图1示出了现有技术中功率场效应晶体管的制备过程的流程图;
图2a-2c示出了现有技术中功率场效应晶体管的制备过程的示意图;
图3示出了依据本发明的包含沟槽栅的半导体器件的制备方法的流程图;
图4a-4g示出了图3所示方法制备半导体器件的示意图。
图中,
001衬底,002外延层,003沟槽,004屏蔽氧化层,005多晶硅,006缝隙,100衬底,200外延层,210第一倾斜面,220第二倾斜面,300沟槽,400牺牲氧化层,500屏蔽氧化层,600多晶硅,700一次缝隙,700’二次缝隙,a第一夹角,b第二夹角。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
本领域技术人员应当领会的是,本发明实施例中所有使用“第一”、“第二”、“一次”、“二次”的表述均是为了区分两个相同名称但非相同的实体,可见“第一”、“第二”、“一次”、“二次”仅为了表述的方便,不应理解为对本发明实施例的限定,后续实施例对此不再一一说明。并且,本发明实施例中的方位名词均以正常制备过程中水平放置的半导体器件为参考。例如,“外延层的上表面”即指外延层远离衬底的表面;“竖直方向”即为垂直于水平放置的衬底层的方向。
如图3和4a-4g所示,依据本发明的包含沟槽栅的半导体器件的制备方法总体包含如下步骤:
1)在半导体衬底100上形成外延层200,在外延层200中形成沟槽300(图4a)。具体地,可先在外延层200上方覆盖掩模层并以蚀刻的方式在外延层200上形成沟槽300,再将掩模层去除。
2)对外延层200的表面和沟槽300的内壁进行蚀刻,使沟槽300的顶部的直径大于沟槽的底部的直径。在本发明的实施例中,可通过干蚀刻与湿蚀刻结合的方式形成具有上述形状的沟槽300,具体地,
2.1)对外延层200的表面进行干蚀刻,使得外延层200上表面与沟槽300内壁接合处的部分材料被去除,从而在邻近外延层200上表面的沟槽300的内壁处形成第一倾斜面210(图4b),使得第一倾斜面210环绕的区域可构成直径大于沟槽300底部直径的开口。该第一倾斜面210与竖直方向构成第一夹角a,该第一夹角a的大小可以是30-60°,优选为45°。
2.3)以湿蚀刻的方式去除牺牲氧化层400,一方面可进一步扩大开口,另一方面可使开口以外的沟槽300内壁形成第二倾斜面220(图4d),使得第二倾斜面220环绕的区域的直径自沟槽300底部至顶部逐渐增大。该第二倾斜面220与竖直方向构成第二夹角b,该第二夹角b的斜率可以是1:30~1:20,优选1:35。
3)在外延层200上表面和沟槽300的内壁与底部形成屏蔽氧化层500(图4e)。
4)在沟槽300内填充多晶硅600以形成沟槽栅(图4f)。
经干蚀刻与湿蚀刻后的沟槽300总体具有上宽窄的轮廓,尤其在顶部具有直径相对较大的开口,降低了多晶硅600在填充过程中于沟槽300顶部过早闭合的可能性,避免了沟槽栅中形成缝隙,或者仅形成尺寸较小的缝隙700。
优选地,依据本发明的包含沟槽栅的半导体器件的制备方法还可进一步包含步骤5)对半导体器件进行退火处理——例如将沟槽栅加热至800-1000℃——以使多晶硅内部材料均匀化,从而使第一缝隙700转变为尺寸更小的第二缝隙700’(图4g),或者彻底消除第一缝隙700。
通过上述方法制备半导体器件可有效避免在沟槽栅中形成足以影响后续工艺或器件性能的缝隙,进而提高半导体器件的成品率。
以上实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (10)
1.一种包含沟槽栅的半导体器件的制备方法,其特征在于,包含以下步骤:
1)在半导体衬底上形成外延层,在所述外延层中形成沟槽;
2)对所述外延层的上表面和所述沟槽的内壁进行蚀刻,使所述沟槽的顶部的直径大于所述沟槽的底部的直径;
3)在所述外延层的上表面和所述沟槽的内壁与底部形成屏蔽氧化层;以及
4)在所述沟槽内填充多晶硅以形成沟槽栅。
2.根据权利要求1所述的制备方法,其特征在于,步骤1)包含基于所述外延层上方的掩模层在所述外延层上形成沟槽,以及去除所述掩模层。
3.根据权利要求1所述的制备方法,其特征在于,步骤2)包含:
2.1)对所述外延层的上表面进行干蚀刻,使邻近所述外延层的上表面的所述沟槽的内壁形成第一倾斜面,所述第一倾斜面环绕的区域构成直径大于所述沟槽的底部直径的开口。
4.根据权利要求3所述的制备方法,其特征在于,步骤2)包含:
2.2)在所述外延层的上表面和所述沟槽的内壁与底部形成牺牲氧化层;
2.3)去除所述牺牲氧化层,以使所述开口扩大并使所述开口以外的所述内壁形成第二倾斜面,所述第二倾斜面环绕的区域的直径自所述沟槽的底部至所述沟槽的顶部逐渐增大。
6.根据权利要求4所述的制备方法,其特征在于,所述第一倾斜面与竖直方向构成第一夹角,所述第一夹角为30-60°。
7.根据权利要求4所述的制备方法,其特征在于,所述第二倾斜面与竖直方向构成第二夹角,所述第二夹角的斜率为1:30~1:20。
8.根据权利要求1-7任一项所述的制备方法,其特征在于,所述制备方法包含:步骤5)对所述半导体器件进行退火处理。
9.根据权利要求8所述的制备方法,其特征在于,所述退火处理包含将所述沟槽栅加热至800-1000℃。
10.一种使用权利要求1-9任一项所述的方法制备的半导体器件。
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US20010006836A1 (en) * | 1994-02-04 | 2001-07-05 | Katsumi Nakamura | Method of forming a trench mos gate on a power semiconductor device |
US6495294B1 (en) * | 1999-10-28 | 2002-12-17 | Denso Corporation | Method for manufacturing semiconductor substrate having an epitaxial film in the trench |
TW457567B (en) * | 2000-07-17 | 2001-10-01 | Mosel Vitelic Inc | Manufacturing method for gate oxide layer |
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