CN113886318A

CN113886318A - Single-chip microcomputer UART interface device supporting multiple baud rates

Info

Publication number: CN113886318A
Application number: CN202111148331.6A
Authority: CN
Inventors: 杨智华; 罗盛裕; 周黄
Original assignee: Shenzhen Zhixiang Technology Co ltd
Current assignee: Shenzhen Zhixiang Technology Co ltd
Priority date: 2021-09-29
Filing date: 2021-09-29
Publication date: 2022-01-04

Abstract

The invention discloses a single chip microcomputer UART interface device supporting multiple baud rates, and relates to the technical field of single chip microcomputers. The device comprises: the UART module and the first register are connected with the UART module; wherein: the UART module internally comprises a first counter and a second counter; the second counter is used for dividing the transmitting/receiving bit width of the UART module into 2^NEqual parts, wherein N is an integer; the first counter is used for counting in the value range of each equal bit width to realize rough adjustment of the bit width of the baud rate, wherein the value range is set by the first register. The UART interface device can give consideration to the transmission speeds of various baud rates through the embodiment of the invention, so that the UART interface device can give consideration to the requirements of both low-speed baud rates and high-speed baud rates, and can meet various standard baud rates as much as possible.

Description

Single-chip microcomputer UART interface device supporting multiple baud rates

Technical Field

The invention relates to the technical field of single-chip microcomputers, in particular to a single-chip microcomputer UART interface device supporting multiple baud rates.

Background

A UART (Universal Asynchronous Receiver/Transmitter) is a common peripheral in a single chip microcomputer, and a CPU of the single chip microcomputer communicates with other external devices through the UART.

As shown in fig. 1, the UART specifies data transmission by first sending a Start Bit Start (low), then sending a 0-th Bit0 of 8-Bit data, then sending a 1-th Bit1 … …, a 7-th Bit7 or an 8-th Bit8 (the 8-th Bit is optional, for example, in a band check mode, the 8-th Bit is a parity Bit), and finally sending a Stop Bit Stop (high), so that one byte transmission is completed. Between the bytes, there may be Idle bits Idle of variable length (the Idle bits Idle are kept at high level by the pull-up resistor, and the time length may be 0). Because the data is serial, both the transceiver and the transmitter must agree on the speed of each bit to ensure that the transmission will not be corrupted. This speed is expressed in baud rate, i.e. how many bits are sent in 1 second time. The UART transmission allows the baud rates of the transmitting side and the receiving side to have certain errors, and the data can be correctly received as long as the receiving offset of the data is within half bit time.

Commonly used baud rates are 4800, 9600, 14400, 19200, 38400, 56000, 57600, 115200, 128000, 256000, and the like. The baud rate speeds are very different, and the traditional UART cannot meet the transmission speeds of the various baud rates in the UART equipment, namely, the requirement of both low speed and high speed can be met.

Therefore, a new UART design is needed to meet both low speed and high speed requirements, and meet various standard baud rates as much as possible.

Disclosure of Invention

The embodiment of the invention aims to provide a single chip microcomputer UART interface device supporting multiple baud rates, which can enable the UART interface device to give consideration to the transmission speeds of various baud rates, so that the UART interface device can give consideration to the requirements of both low-speed baud rates and high-speed baud rates, and can meet various standard baud rates as much as possible.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions: a single chip UART interface apparatus supporting multiple baud rates, the apparatus comprising: the UART module and the first register are connected with the UART module; wherein:

the UART module internally comprises a first counter and a second counter;

the second counter is used for dividing the transmitting/receiving bit width of the UART module into 2^NEqual parts, wherein N is an integer;

the first counter is used for counting in the value range of each equal bit width to realize rough adjustment of the bit width of the baud rate, wherein the value range is set by the first register.

Optionally, a value range M of the first counter is [ 0-255 ], and the value range M is set by a first register; the first counter counts clock cycles within each equal bit width, the count value of the first counter is automatically added with 1 in one clock cycle, and when the count value reaches M, the counting is restarted from 0.

Optionally, the apparatus further includes a second register, where the second register is configured to set a bit width position of a specified equal portion, into which a clock needs to be inserted, of the second counter.

Optionally, the bit width position of the designated equal part includes bit width positions of equal parts at the head and tail ends.

Optionally, the specified bit width position of the equal part includes bit width positions of equal parts according to the second counter sequence.

Optionally, the second counter performs clock insertion operation at the bit width position of the equal part specified by the second register, so that the bit width is accurately equal to the width required by transmitting/receiving 1 bit of the baud rate, and fine adjustment of the baud rate bit width is realized.

Optionally, the second counter is further configured to enable a receiving end of the UART module to read data at a middle position of a transmitting/receiving bit width.

Optionally, the apparatus further includes a transceiving buffer module, where the transceiving buffer module is connected to the UART module and is configured to buffer baud rate data to be sent from the CPU to the UART module and baud rate data to be received from the UART module to the CPU.

Optionally, when the device sends baud rate data, the CPU determines that the storage of the transceiving buffer module is not full, writes the baud rate data into the transceiving buffer module, and then sends a PUSH signal until the transceiving buffer module is full or the baud rate data to be sent is finished;

the receiving and transmitting buffer module receives the baud rate data and then is in a non-empty state, and the baud rate data is sent to the UART module;

the UART module automatically sends out baud rate data through a TX pin, and the baud rate data sending by the UART module can be automatically carried out as long as the transceiving buffer module is in a non-empty state;

as long as the storage of the transceiving buffer module is not full, the baud rate data sent by the CPU can be received all the time until the baud rate data to be sent are finished.

Optionally, when the single-chip UART interface device receives baud rate data, the UART module automatically receives the baud rate data through an RX pin and writes the received baud rate data into the transceiving buffer module, and an output of the transceiving buffer module is in a non-empty state;

the CPU reads baud rate data from the transceiving buffer module and sends a POP signal; as long as the receiving and sending buffer module is in a non-empty state, the CPU reads data from the receiving and sending buffer module all the time; as long as the receiving and sending buffer module is not full of memory, the UART module can automatically receive baud rate data sent by an RX pin; if the receiving and sending buffer module is full, and the UART module receives a baud rate data from the RX pin again at the moment, an error is reported.

Compared with the prior art, the single chip microcomputer UART interface device supporting multiple baud rates provided by the embodiment of the invention comprises the following components: a UART module and a first register REG1, the first register REG1 being connected with the UART module; wherein: the UART module internally comprises a first counter cnt1 and a second counter cnt 2; the second counter cnt2 is configured to divide a transmission/reception bit width of the UART module into 2N equal parts; the first counter cnt1 is configured to count within a value range of the first counter cnt1 within each equal bit width, so as to implement coarse adjustment of the bit width of the baud rate, where the value range of the first counter cnt1 is set by the first register REG 1. Therefore, the UART interface device can give consideration to the transmission speeds of various baud rates, not only can give consideration to the requirements of low-speed baud rates, but also can give consideration to the requirements of high-speed baud rates, and can meet various standard baud rates as much as possible.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a schematic diagram of a data structure of data transmission specified by UART.

Fig. 2 is a schematic structural diagram of a single-chip UART interface apparatus supporting multiple baud rates according to the present invention.

Fig. 3 is a schematic timing diagram of a single-chip UART interface device supporting multiple baud rates in transmitting baud rate data according to the present invention.

Fig. 4 is a schematic timing diagram of a single-chip UART interface device supporting multiple baud rates in transmitting baud rate data according to the present invention.

Fig. 5 is a schematic timing diagram of a single-chip UART interface device supporting multiple baud rates according to the present invention when receiving baud rate data.

Fig. 6 is a schematic structural diagram of a single-chip UART interface apparatus supporting multiple baud rates according to the present invention.

Detailed Description

In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. As used in this specification, the terms "upper," "lower," "inner," "outer," "bottom," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the invention and simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

In one embodiment, as shown in fig. 2 and 3, the present invention provides a single-chip UART interface apparatus supporting multiple baud rates, the single-chip UART interface apparatus including: a UART module and a first register REG1, the first register REG1 being connected with the UART module; wherein:

the UART module internally comprises a first counter cnt1 and a second counter cnt 2;

the second counter cnt2 is used for dividing the transmission/reception bit width of the UART module into 2^NEqual parts, wherein N is an integer;

the first counter cnt1 is configured to count within a value range of the first counter cnt1 within each equal bit width, so as to implement coarse adjustment of the bit width of the baud rate, where the value range of the first counter cnt1 is set by the first register REG 1.

In this embodiment, a single chip UART interface apparatus supporting multiple baud rates is provided, where the apparatus includes: a UART module and a first register REG1, the first register REG1 being connected with the UART module; wherein: the UART module internally comprises a first counter cnt1 and a second counter cnt 2; the second counter cnt2 is configured to divide a transmission/reception bit width of the UART module into 2N equal parts; the first counter cnt1 is configured to count within a value range of the first counter cnt1 within each equal bit width, so as to implement coarse adjustment of the bit width of the baud rate, where the value range of the first counter cnt1 is set by the first register REG 1. Therefore, the UART interface device can give consideration to the transmission speeds of various baud rates, not only can give consideration to the requirements of low-speed baud rates, but also can give consideration to the requirements of high-speed baud rates, and can meet various standard baud rates as much as possible.

In one embodiment, as shown in fig. 3, a value range M of the first counter cnt1 is [ 0-255 ], and the value range M is set by the first register REG 1; the first counter cnt1 counts clock cycles within each equal bit width, and for one clock cycle, the count value of the first counter cnt1 is automatically increased by 1, and when the count value reaches M, the counting is restarted from 0, and the cycle is repeated.

Preferably, the first register REG1 is an 8-bit frequency division register, one 8-bit frequency division register REG1 is used within each equal bit width, a corresponding value is set for the first counter cnt1, the clock cycle is counted, the bit width required by the baud rate can be roughly obtained, and rough adjustment of the baud rate bit width is realized.

In this embodiment, the second counter cnt2 divides a transmission/reception bit width of the UART module into 2 bits by providing a first counter cnt1 and a second counter cnt2 inside the UART module^NThe first counter cnt1 is used for counting clock cycles within the value range M of the first counter cnt1 within the bit width of each equal part, and can roughly approach values of some baud rates, obtain an indication range in which the value of the baud rate is wider, roughly obtain the bit width required by the baud rate, and realize rough adjustment of the bit width of the baud rate.

In an embodiment, as shown in fig. 2 and fig. 4, the single chip UART interface apparatus further includes a second register REG2, where the second register REG2 is used to set a bit width position of a specified equal portion of the clock to be inserted into the second counter cnt 2.

Preferably, the bit width position of the designated equal part includes bit width positions of equal parts at the head and the tail ends, and the second counter cnt2 may insert a clock at the bit width positions of equal parts at the head and the tail ends. Alternatively, the specified bit-width bits of the equal part include the bit-width bits of the equal part in the order of the second counter cnt2, and the clock may be inserted into the second counter cnt2 in the bit-width bits of the equal part in the order of the second counter cnt 2.

Preferably, the second register REG2 is a divide-by-3 adjustment register.

The second counter cnt2 performs clock insertion operation at the bit width position of the equal part specified by the second register REG2, so that the bit width is exactly equal to the width required by 1 bit of baud rate transmission/reception, and fine adjustment of the baud rate bit width is realized.

In this embodiment, the transmitting/receiving bit width of the UART module is divided into 2^NEqually dividing, using an 8-bit frequency division register (first register) REG1 in each equal bit width, setting a corresponding value for the first counter cnt1, counting clock cycles, roughly obtaining the bit width required by the baud rate, and implementing rough adjustment of the baud rate bit width. Meanwhile, a 3-bit frequency division adjustment register (second register) REG2 is used to enable the second counter cnt2 to perform clock insertion operation at the bit width position of the equal part specified by the second register REG2, so that the bit time is prolonged, the bit width is accurately equal to the width required by the baud rate transmitting/receiving 1 bit, and fine adjustment of the baud rate bit width is realized.

In one embodiment, as shown in fig. 4, the second counter cnt2 is further used for enabling the receiving end of the UART module to read data at a middle position of a transmitting/receiving bit width.

The count range of the second counter cnt2 is [0 to (2 ]^N-1)]. The second counter cnt2 divides the transmission/reception bit width of the UART module into 2^NAfter the equal parts, the UART moduleThe receiving end of the block reads data at the very middle of the bit width, which is the least error prone.

For example, as shown in fig. 4, when N is 3, 2^N-1＝2³-1 ═ 7, and the count range of the second counter cnt2 is [0, 1, 2, 3, 4, 5, 6, 7]The middle position of the transmitting/receiving bit width is at the transition positions of 3 and 4, and when the count value of the second counter cnt2 changes from 3 to 4, the receiving end of the UART module reads data at this time, which is the least error-prone.

In this embodiment, in order to obtain a more accurate baud rate, some clocks are appropriately inserted into the bit width of the designated equal part of the second counter, so that the bit width (time length) of this bit can be made to be exactly equal to the bit width required by the baud rate to transmit/receive 1 bit, and it is preferable that the receiving end of the UART module reads data in the middle of the data bit. Which equal bit widths require an insertion clock may be set by the second register REG2, i.e. said second register REG2 sets the specified equal bit width position of the second counter cnt2 that requires an insertion clock.

In one embodiment, the bit width calculation formula for baud rate transmit/receive 1 bit is as follows:

bit width is Period x (2)^N)×REG1[7:0]+Period×REG2(1)

In the above equation (1), Period is a clock cycle, and the number of significant bits of the second register REG2 is determined by N (N is an integer).

Selecting a suitable parameter N, e.g. in this embodiment N is selected to be 6, 2^N＝2⁶In case of a clock frequency of 48MHz, 64, the above equation (1) is:

bit width of 20.83 × 64 × REG1[7:0] +20.83 × REG2[5:0]

In the above equation (1), the second register REG2 requires only 6 bits enough.

From the above equation (1), bit widths covering the following baud rates can be obtained as shown in table 1 below.

TABLE 1 Baud Rate and bit Width thereof

In table 1 above, the first behavior is the common baud rate that this embodiment can support; the second behavior is that theoretical bit width 1 is obtained through calculation according to the baud rate; the third row is the actual bit width 2 that can be achieved with this embodiment.

As can be obtained from table 1 above, the actual bit width 2 that can be achieved in this embodiment is very close to the theoretical bit width 1 calculated according to the baud rate.

In one embodiment, as shown in fig. 4, when the UART module transmits baud rate data, the operation of the UART module is as follows: when the UART module transmits baud rate data, the low level on the TX pin goes low, i.e. the Start bit starts, the first counter cnt1 and the second counter cnt2 Start to work at once, and the second counter cnt2 divides the transmission/reception bit width into 2^NAnd the receiving end of the UART reads data at the middle position of the transmitting/receiving bit width. The second counter cnt2 also performs an insert clock operation according to the bit width position of the equal part specified by the second register REG2, so that the bit width is exactly equal to the width required by the baud rate to transmit/receive 1 bit. The UART module transmits baud rate data to the TX pin according to the values of the first counter cnt1 and the second counter cnt2, completing transmission of one data bit.

Fig. 4 is a schematic diagram illustrating data transmission by the UART interface apparatus for a single chip microcomputer supporting multiple baud rates according to the present invention.

In fig. 4, N is selected to be 3, a value range M of the first counter cnt1 is [ 0-255 ], a count range of the second counter cnt2 is [0, 1, 2, 3, 4, 5, 6, 7], the second counter cnt2 divides a transmission/reception bit width into 8 equal parts, the second register REG2 sets the second counter cnt2 to insert 2 clocks (as shown in a gray part in fig. 4) at bit width positions of the equal parts at the head and tail ends, so that the bit width is exactly equal to a width required by 1 bit transmission/reception of a baud rate; the middle position of the transmitting/receiving bit width is at the jump position of 3 and 4, and when the count value of the second counter cnt2 changes from 3 to 4, the receiving end of the UART module reads data at this time until the data to be transmitted is finished.

In one embodiment, as shown in fig. 5, the UART module operates in a similar manner when receiving baud rate data as when transmitting the baud rate data.

When the UART module receives baud rate data, the low level on the RX pin goes low, i.e. the Start bit starts, the first counter cnt1 and the second counter cnt2 Start to work at once, and the second counter cnt2 divides the transmission/reception bit width into 2^NAnd the receiving end of the UART reads data at the middle position of the transmitting/receiving bit width. The second counter cnt2 also performs an insert clock operation according to the bit width position of the equal part specified by the second register REG2, so that the bit width is exactly equal to the width required by the baud rate to transmit/receive 1 bit. The UART module receives baud rate data to the RX pin according to the values of the first counter cnt1 and the second counter cnt2, completing the reception of one data bit.

Fig. 5 is a schematic diagram illustrating the data received by the UART interface apparatus for a single chip microcomputer supporting multiple baud rates according to the present invention.

In fig. 5, N is selected to be 3, a value range M of the first counter cnt1 is [ 0-255 ], a count range of the second counter cnt2 is [0, 1, 2, 3, 4, 5, 6, 7], the second counter cnt2 divides a transmission/reception bit width into 8 equal parts, the second register REG2 sets the second counter cnt2 to insert 2 clocks (as shown in a gray part in fig. 5) at bit width positions of the equal parts at the head and tail ends, so that the bit width is exactly equal to a width required by 1 bit transmission/reception of a baud rate; the middle position of the transmitting/receiving bit width is at the jump position of 3 and 4, and when the count value of the second counter cnt2 changes from 3 to 4, the receiving end of the UART module reads data at this time until the end of the data to be received.

In general, in the case of a high-speed transmission rate, especially in the case of a data end without idle bits, in order to avoid wasting bandwidth, data transmission is performed one after another, a CPU executes several instructions, several clocks are needed at the fastest speed, and when the CPU reads data, the start bit of the next byte starts to be transmitted, so that the CPU does not have enough time to read data, which may cause data errors or loss.

For this reason, in an embodiment, as shown in fig. 6, the single-chip UART interface apparatus further includes a transceiving buffer module, connected to the UART module, for buffering the baud rate data to be transmitted from the CPU to the UART module and the baud rate data to be received from the UART module to the CPU, so as to convert the data operation of the UART module by the CPU into the data operation of the transceiving buffer module, so that the UART module itself can uninterruptedly transmit and receive the baud rate data at full speed, thereby better supporting high-speed transmission, and making it difficult for the CPU to lose data or cause data errors when transmitting and receiving data.

Preferably, the transceiving buffer module is implemented in a FIFO (First Input First Output) manner.

The following further describes the data transmitted and received by the UART interface apparatus of the single chip microcomputer by taking the FIFO manner as an example of the transmission and reception buffer module.

When the UART interface device of the single chip microcomputer sends baud rate data, the working process is as follows:

when the CPU judges that the FIFO is not full, the Baud rate data is written into the FIFO, and then a PUSH signal is sent until the FIFO is full or the Baud rate data to be sent are finished. After the FIFO receives the baud rate data, the FIFO is in a non-empty state at the moment, the FIFO sends the baud rate data to the UART module, the UART module can automatically send the baud rate data out through the TX pin according to the working process of sending the baud rate data, and the UART module can automatically send the baud rate data as long as the FIFO is in the non-empty state. As long as the FIFO memory is not full, the baud rate data sent by the CPU can be received all the time until the baud rate data to be sent are finished.

When the UART interface device of the single chip microcomputer receives baud rate data, the working process is as follows:

after the UART module automatically receives the baud rate data through the RX pin according to the working process of receiving the baud rate data, the UART module writes the received baud rate data into the FIFO, the output of the FIFO is in a non-empty state at the moment, and then the CPU can read the baud rate data from the FIFO and send a POP signal; the CPU can always read data from the FIFO as long as the FIFO is in a non-empty state. As long as the FIFO memory is not full (full is 0), the UART module may automatically receive the baud rate data from the RX pin. If the FIFO is full (full 1), and the UART module receives a baud rate data from the RX pin again, an error is reported.

In this embodiment, the UART interface apparatus of the single chip microcomputer is provided with the transceiving buffer module, and the data operation of the CPU on the UART module is converted into the data operation on the transceiving buffer module, so that the UART module itself can uninterruptedly transmit and receive baud rate data at full speed, thereby better supporting high-speed transmission, and making the CPU less prone to data loss or data error when transmitting and receiving data.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single chip microcomputer UART interface device supporting multi-baud rate is characterized in that the device comprises: the UART module and the first register are connected with the UART module; wherein:

the UART module internally comprises a first counter and a second counter;

2. The apparatus of claim 1, wherein a value range M of the first counter is [ 0-255 ], the value range M being set by the first register; the first counter counts clock cycles within each equal bit width, the count value of the first counter is automatically added with 1 in one clock cycle, and when the count value reaches M, the counting is restarted from 0.

3. The apparatus of claim 1, further comprising a second register for setting a bit width position of the second counter that requires an insertion clock of a specified equal portion.

4. The apparatus of claim 3, wherein the specified slot width locations comprise slot width locations at a beginning and end of the slot.

5. The apparatus of claim 3, wherein the specified bit-wide locations of the aliquot comprise bit-wide locations of the aliquot in a second counter order.

6. The apparatus according to claim 3, wherein the second counter performs an insert clock operation at the bit width position of the equal portion specified by the second register, so that the bit width is exactly equal to the width required by the baud rate for transmitting/receiving 1 bit, thereby achieving fine tuning of the baud rate bit width.

7. The apparatus of claim 3, wherein the second counter is further configured to enable a receiving end of the UART module to read data at a middle position of a transmitting/receiving bit width.

8. The apparatus according to claim 1, further comprising a transceiving buffer module, connected to the UART module, for buffering the baud rate data to be transmitted from the CPU to the UART module and the baud rate data to be received from the UART module to the CPU.

9. The device of claim 8, wherein when the device sends baud rate data, the CPU determines that the storage of the transceiving buffer module is not full, writes the baud rate data into the transceiving buffer module, and then sends a PUSH signal until the transceiving buffer module is full or the baud rate data to be sent is finished;

10. The apparatus of claim 8, wherein when the single-chip UART interface apparatus receives baud rate data, the UART module automatically receives the baud rate data through an RX pin and writes the received baud rate data into the transceiving buffer module, and an output of the transceiving buffer module is in a non-empty state;