CN113871469A - Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss - Google Patents
Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss Download PDFInfo
- Publication number
- CN113871469A CN113871469A CN202111088801.4A CN202111088801A CN113871469A CN 113871469 A CN113871469 A CN 113871469A CN 202111088801 A CN202111088801 A CN 202111088801A CN 113871469 A CN113871469 A CN 113871469A
- Authority
- CN
- China
- Prior art keywords
- trench gate
- trench
- turn
- optimizing
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000903 blocking effect Effects 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims description 12
- 238000009826 distribution Methods 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 13
- 238000004886 process control Methods 0.000 abstract 1
- 238000009825 accumulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application discloses an insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, including the trench gate, have mesa area adjacent setting between the trench gate, be equipped with a plurality of at mesa area and block the trench gate, block the trench gate and pass through emitter contact and emitter metallic interconnect, the trench gate still with emitter metallic interconnect. Under the condition that the processing difficulty is not increased, the effective width of the mesa region can be further reduced by introducing the blocking trench gate in the mesa region between the trench gates, so that the carrier concentration of the IGBT device is changed from A-type distribution to B-type distribution in the opening state, and the loss in the turn-off process is further reduced. There is no particular process control on the size of the emitter contact and the distance between the emitter contact and the trench gate. The step face width can be further reduced without being limited by the size and alignment of the emitter contact; blocking the trench gate adjacent to the emitter contact does not result in a significant increase in Qg due to the increased number of trench gates.
Description
Technical Field
The application belongs to the technical field of insulated gate bipolar transistors, and particularly relates to an insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss.
Background
In the optimization process of an Insulated Gate Bipolar Transistor (IGBT) device, reducing loss in the turn-off process is considered to be the most important issue, and usually, reducing the turn-off loss by reducing the carrier concentration inevitably increases the saturation voltage significantly, and the modern optimization idea is to change the device structure so that carriers change from a distribution to B distribution in the on state (as shown in fig. 6), wherein the most effective way is to reduce the size of a cell, especially the mesa width between trenches, and the mesa width of the most advanced IGBT process in the market has entered the submicron level. When the mesa width is in the sub-micron range, the distance from the electrode contact to the trench is compressed to below 300A, which greatly increases the difficulty of the manufacturing process and poses a great challenge to the controllability of the IGBT manufacturing process, especially the electrode contact process and the alignment of the electrode contact with other layers.
Disclosure of Invention
In view of the above drawbacks and deficiencies of the prior art, an object of the present invention is to provide an igbt for optimizing saturation voltage/turn-off loss, in which an effective width of a mesa region is further reduced by introducing a blocking trench in the mesa region without increasing process difficulty, so as to optimize a saturation voltage/turn-off loss relationship.
In order to solve the technical problem, the application is realized by the following technical scheme:
the application provides an insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, including the trench gate, adjacent setting is in mesa area has between the trench gate mesa area is equipped with the blocked trench gate of a plurality of, the blocked trench gate passes through the emitter contact and is connected with the emitter metal, the trench gate still with the emitter metal is connected.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, the blocking trench gate and the trench gate are arranged perpendicular to each other.
Optionally, the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss as described above, wherein the blocking trench gate and the trench gate have the same or different depths.
Optionally, the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss is described above, wherein adjacent blocking trench gates are arranged equidistantly or non-equidistantly.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, the blocking trench gate and the trench gate are arranged in a non-contact manner.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, P wells are further disposed between the trench gates and between the trench gate and the blocking trench.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, a gate oxide layer is further disposed on an outer surface of the trench gate.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, an emitter junction is further disposed at a connection position between the trench gate and the emitter metal.
Optionally, in the insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss, an oxide layer is further disposed at a connection position between the trench gate and the emitter metal.
Compared with the prior art, the method has the following technical effects:
under the condition that the processing difficulty is not increased, the effective width of the mesa region can be further reduced by introducing a plurality of blocking trench gates into the mesa region between the trench gates, so that the concentration of current carriers of the IGBT device is changed from A-type distribution to B-type distribution in the opening state, and the relation of saturation voltage/turn-off loss is further optimized.
The width of the step surface between the trench gate and the blocking trench gate is further reduced by arranging the blocking trench gate, and in the process, the size of the emitter contact and the distance between the emitter contact and the trench gate are not particularly controlled in a manufacturing process. By the arrangement, the width of the step surface between the trench gate and the blocking trench gate can be further reduced without being limited by the size and alignment of the emitter contact. Also, the blocking trench gate is directly adjacent to the emitter contact without a significant increase in Qg due to the increase in trench gates.
In the present application, the blocking trench gate is typically the same depth as the trench gate, but may be a different depth. Depth can be one way of adjusting device performance, and can affect carrier accumulation in the drift region at turn-on. Likewise, adjustment of the distance between adjacently disposed blocking trench gates may also be one of the ways to adjust device performance, with different distances meaning adjustment of mesa region width, while the present application preferably optimizes device performance by adjusting the mesa region width.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1: the insulated gate bipolar transistor is used for optimizing the saturation voltage/turn-off loss in the cross section view;
FIG. 2: a cross-sectional view of the structure of fig. 1 taken along direction C1;
FIG. 3: a cross-sectional view of the structure of fig. 1 taken along direction C2;
FIG. 4: a cross-sectional view of the structure of fig. 1 taken along direction C3;
FIG. 5: the working principle diagram of the insulated gate bipolar transistor is used for optimizing saturation voltage/turn-off loss;
FIG. 6: and the IGBT device is structurally schematic in the state that the carrier concentration is changed from A-type distribution to B-type distribution.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In one embodiment of the present application, as shown in fig. 1 to 4, an insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss includes a trench gate 10 having mesa regions between adjacent trench gates 10, wherein a plurality of blocking trench gates 20 are disposed in the mesa regions, the blocking trench gates 20 are connected to an emitter metal 40 through emitter contacts 30, and the trench gates 10 are further connected to the emitter metal 40.
In the present embodiment, under the condition that the process difficulty is not increased, the effective width of the mesa region can be further reduced by introducing the plurality of blocking trench gates 20 in the mesa region between the trench gates 10, so that the carrier concentration of the IGBT device is changed from a-type distribution to B-type distribution in the on state, thereby further optimizing the relationship between the saturation voltage and the turn-off loss.
As shown in fig. 1, in the present embodiment, the blocking trench gate 20 and the trench gate 10 are disposed perpendicular to each other. By the vertical arrangement mode, the step surface width between the blocking trench gate 20 and the trench gate 10 can be kept consistent, so that the stability of the device is more controllable.
Optionally, the blocking trench gate 20 has the same or a different depth than the trench gate 10.
Optionally, the adjacent blocking trench gates 20 are disposed equidistantly or non-equidistantly.
In the present embodiment, the blocking trench gate 20 is usually the same depth as the trench gate 10, but may be different depths. Depth can be one way of adjusting device performance, and can affect carrier accumulation in the drift region at turn-on. Likewise, adjustment of the distance between adjacently disposed blocking trench gates 20 may also be one of the ways to adjust device performance, with different distances meaning adjustment of mesa region width, while the present embodiment preferably optimizes device performance by adjusting the mesa region width.
The blocking trench gate 20 and the trench gate 10 are arranged in a non-contact manner, and through the arrangement, the width of a mesa region between the blocking trench gate 20 and the trench gate 10 can be realized, and compared with the prior art, the width of the mesa region between the blocking trench gate 20 and the trench gate 10 can be further reduced, so that the carrier concentration of the IGBT device is changed from A-type distribution to B-type distribution in an opening state, and the relation of saturation voltage/turn-off loss is further optimized.
As shown in fig. 2 to 4, P wells 50 are disposed between the trench gates 10 and between the trench gate 10 and the blocking trench gate 20.
Optionally, a gate oxide layer 11 is further disposed on an outer surface of the trench gate 10. Wherein, the surface of the gate oxide layer 11 is smooth and flat.
Further, an emitter junction 70 is further disposed at a connection position of the trench gate 10 and the emitter metal 40.
Further preferably, an oxide layer 70 is further disposed at a connection position of the trench gate 10 and the emitter metal 40.
In the present embodiment, as shown in fig. 5, it can be seen that the width of the step region is redefined by the distance between the trench gate 10 and the blocking trench gate 20, that is, the step surface width between the trench gate 10 and the blocking trench gate 20 is further reduced by disposing the blocking trench gate 20, and in this process, the size of the emitter contact 30 and the distance between the emitter contact 30 and the trench gate 10 are not particularly controlled. With the above arrangement, the step surface width between the trench gate 10 and the blocking trench gate 20 can be further reduced without being limited by the size and alignment of the emitter contact 30. Also, the blocking trench gate 20 is directly adjacent to the emitter contact 30 without a significant increase in Qg due to the increase in trench gates 10.
Under the condition that the processing difficulty is not increased, the effective width of the mesa region can be further reduced by introducing the blocking trench gates 20 into the mesa region between the trench gates 10, so that the carrier concentration of the IGBT device is changed from A-type distribution to B-type distribution in the opening state, and the loss in the turn-off process is further reduced. The step surface width between the trench gate 10 and the blocking trench gate 20 is further reduced by arranging the blocking trench gate 20, and in the process, the size of the emitter contact 30 and the distance between the emitter contact 30 and the trench gate 10 are not particularly controlled in the process. With the above arrangement, the step surface width between the trench gate 10 and the blocking trench gate 20 can be further reduced without being limited by the size and alignment of the emitter contact 30. Also, the blocking trench gate 20 is directly adjacent to the emitter contact 30 without a significant increase in Qg due to the increase in trench gates 10. In the present application, the blocking trench gate 20 is typically the same depth as the trench gate 10, but may be a different depth. Depth can be one way of adjusting device performance, and can affect carrier accumulation in the drift region at turn-on. Likewise, adjustment of the distance between adjacently disposed blocking trench gates 20 may also be one of the ways to adjust device performance, with different distances meaning adjustment of mesa region width, while the present application preferably optimizes device performance by adjusting the mesa region width.
In the description of the present application, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the present embodiment, the terms "upper", "lower", "left", "right", and the like are used based on the orientations and positional relationships shown in the drawings only for convenience of description and simplification of operation, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used only for descriptive purposes and are not intended to have a special meaning.
The above embodiments are merely to illustrate the technical solutions of the present application and are not limitative, and the present application is described in detail with reference to preferred embodiments. It will be understood by those skilled in the art that various modifications and equivalent arrangements may be made in the present invention without departing from the spirit and scope of the present invention and shall be covered by the appended claims.
Claims (9)
1. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss is characterized by comprising trench gates, wherein a mesa area is arranged between the trench gates adjacently, a plurality of blocking trench gates are arranged on the mesa area, the blocking trench gates are connected with emitter metal through emitter contacts, and the trench gates are also connected with the emitter metal.
2. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to claim 1, wherein said blocking trench gate and said trench gate are arranged perpendicular to each other.
3. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to claim 1, wherein said blocking trench gate has the same or different depth than said trench gate.
4. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to claim 1, wherein adjacent arrangement at said blocking trench gates is arranged equidistantly or non-equidistantly.
5. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to claim 1, wherein said blocking trench gate and said trench gate are in a non-contact arrangement.
6. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to any one of claims 1 to 5, wherein a P well is disposed adjacently between the trench gates and between the trench gate and the blocking trench gate.
7. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to any one of claims 1 to 5, wherein a gate oxide layer is further provided on an outer surface of the trench gate.
8. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to any one of claims 1 to 5, wherein an emitter junction is further provided at a connection position of the trench gate and the emitter metal.
9. The insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss according to claim 8, wherein an oxide layer is further provided at a connection position of said trench gate and said emitter metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111088801.4A CN113871469A (en) | 2021-09-16 | 2021-09-16 | Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111088801.4A CN113871469A (en) | 2021-09-16 | 2021-09-16 | Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113871469A true CN113871469A (en) | 2021-12-31 |
Family
ID=78996149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111088801.4A Pending CN113871469A (en) | 2021-09-16 | 2021-09-16 | Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113871469A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011165928A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Insulated gate bipolar transistor |
| JP2011165971A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Semiconductor device |
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| CN107636836A (en) * | 2015-12-11 | 2018-01-26 | 富士电机株式会社 | Semiconductor device |
| CN113054009A (en) * | 2019-12-27 | 2021-06-29 | 株洲中车时代半导体有限公司 | Trench IGBT chip |
-
2021
- 2021-09-16 CN CN202111088801.4A patent/CN113871469A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011165928A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Insulated gate bipolar transistor |
| JP2011165971A (en) * | 2010-02-10 | 2011-08-25 | Toyota Central R&D Labs Inc | Semiconductor device |
| CN102792448A (en) * | 2010-03-09 | 2012-11-21 | 富士电机株式会社 | Semiconductor device |
| CN107636836A (en) * | 2015-12-11 | 2018-01-26 | 富士电机株式会社 | Semiconductor device |
| CN113054009A (en) * | 2019-12-27 | 2021-06-29 | 株洲中车时代半导体有限公司 | Trench IGBT chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6031265A (en) | Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area | |
| JP5001895B2 (en) | Low on-resistance trench MOSFET with delta layer | |
| JP4456013B2 (en) | Semiconductor device | |
| US11139291B2 (en) | Semiconductor device | |
| US20120025262A1 (en) | MOS Type Semiconductor Device and Method of Manufacturing Same | |
| US20080029812A1 (en) | Planar SRFET using no additional masks and layout method | |
| US11380784B2 (en) | Semiconductor device | |
| US11107910B2 (en) | Semiconductor device | |
| WO2019154219A1 (en) | Igbt power device and fabrication method therefor | |
| US20210305051A1 (en) | Metal Wiring Method for Reducing Gate Resistance of a Narrow Control Gate Structure | |
| US20190097005A1 (en) | Semiconductor Device Having Termination Trench | |
| CN116072710B (en) | Double-groove type SiC MOSFET cell structure, device and preparation method | |
| CN104377242A (en) | Ldmos device and manufacturing method thereof | |
| US20220328618A1 (en) | Semiconductor power device | |
| US11374119B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN109461769B (en) | Trench gate IGBT device structure and manufacturing method thereof | |
| CN113871469A (en) | Insulated gate bipolar transistor for optimizing saturation voltage/turn-off loss | |
| JP7107718B2 (en) | Method for manufacturing switching element | |
| JP3677489B2 (en) | Vertical field effect transistor | |
| KR102515335B1 (en) | Mosfet device and method thereof | |
| CN209104157U (en) | A kind of trench gate IGBT device structure | |
| CN100431168C (en) | High power semiconductor device capable of preventing parasitical bipolar transistor | |
| CN113972272B (en) | MOSFET device | |
| US11411076B2 (en) | Semiconductor device with fortifying layer | |
| US20220352369A1 (en) | Laterally double-diffused metal oxide semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |