CN113871466A - GaN HEMT device and preparation method thereof - Google Patents
GaN HEMT device and preparation method thereof Download PDFInfo
- Publication number
- CN113871466A CN113871466A CN202111004565.3A CN202111004565A CN113871466A CN 113871466 A CN113871466 A CN 113871466A CN 202111004565 A CN202111004565 A CN 202111004565A CN 113871466 A CN113871466 A CN 113871466A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- silicon nitride
- substrate
- layer
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 128
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 87
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 86
- 238000005530 etching Methods 0.000 claims abstract description 67
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 64
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000002131 composite material Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 36
- 238000009616 inductively coupled plasma Methods 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 9
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 239000003960 organic solvent Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 2
- ODAOZWTYNWZSBY-SPIKMXEPSA-N (z)-but-2-enedioic acid;6-[2-(1h-imidazol-5-yl)ethylamino]-n-[4-(trifluoromethyl)phenyl]heptanamide Chemical compound OC(=O)\C=C/C(O)=O.OC(=O)\C=C/C(O)=O.C=1N=CNC=1CCNC(C)CCCCC(=O)NC1=CC=C(C(F)(F)F)C=C1 ODAOZWTYNWZSBY-SPIKMXEPSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- -1 silicon nitride compound Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a GaN HEMT device and a preparation method thereof, belonging to the technical field of semiconductor device preparation, wherein the GaN HEMT device comprises a substrate, an ohmic electrode, a silicon dioxide dielectric layer, a silicon nitride dielectric layer and a gate metal layer, the preparation method comprises the steps of manufacturing the ohmic electrode on the substrate, sequentially forming the silicon dioxide dielectric layer and the silicon nitride dielectric layer, etching the silicon nitride dielectric layer and the silicon dioxide dielectric layer, forming an etching groove in the middle of the substrate, forming the gate metal layer in the etching groove and on the region adjacent to the silicon nitride dielectric layer, solving the technical problems of large gate parasitic capacitance, reduced gain and poor high-frequency characteristic of the GaN HEMT device, replacing the silicon nitride dielectric with a silicon dioxide and silicon nitride composite dielectric, reducing the dielectric constant, manufacturing a T-shaped gate of the composite dielectric, reducing the gate parasitic capacitance of the device, realizing low parasitic capacitance, low parasitic resistance and low dielectric constant, A high-gain GaN HEMT device has improved high-frequency characteristics.
Description
Technical Field
The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a GaN HEMT device and a preparation method thereof.
Background
As a wide bandgap semiconductor material, GaN has a large bandgap width Eg, high breakdown field strength, high electron saturation drift velocity, high thermal conductivity and the like, so that GaN has great potential in the fields of high-speed high-power switches, radio-frequency power device manufacturing and the like. The traditional GaN HEMT device dielectric gate generally adopts a silicon nitride dielectric structure, and the silicon nitride material has a large dielectric constant, so that the problems of large parasitic capacitance of the device gate, reduced gain, poor high-frequency characteristics and the like are caused.
Disclosure of Invention
The invention aims to provide a GaN HEMT device and a preparation method thereof, and aims to solve the technical problems of large grid parasitic capacitance, reduced gain and poor high-frequency characteristics of the GaN HEMT device.
In order to achieve the purpose, the invention adopts the technical scheme that: provided is a GaN HEMT device including: the device comprises a substrate, an ohmic electrode, a silicon dioxide dielectric layer, a silicon nitride dielectric layer and a gate metal layer, wherein the ohmic electrode is formed on the substrate; a silicon dioxide dielectric layer is formed on the substrate and the ohmic electrode; a silicon nitride dielectric layer is formed on the silicon dioxide dielectric layer, etching grooves are formed in the silicon nitride dielectric layer and the silicon dioxide dielectric layer at positions corresponding to the middle area of the substrate, and the bottom walls of the etching grooves are the upper surface of the substrate; and the gate metal layer is formed in the etching groove and on the area adjacent to the silicon nitride dielectric layer.
In a possible implementation manner, the thickness of the silicon dioxide dielectric layer is 180nm to 200nm, and the thickness of the silicon nitride dielectric layer is 30nm to 50 nm.
The GaN HEMT device provided by the invention has the beneficial effects that: compared with the prior art, the GaN HEMT device solves the technical problems of large gate parasitic capacitance, reduced gain and poor high-frequency characteristic of the GaN HEMT device, silicon dioxide and silicon nitride composite media are used for replacing silicon nitride media, the dielectric constant is reduced, T-shaped gates (T gates for short) of the composite media are manufactured, the gate parasitic capacitance of the device is reduced, the low-parasitic and high-gain GaN HEMT device is realized, and the high-frequency characteristic is improved.
The invention also provides a preparation method of the GaN HEMT device, which comprises the following steps:
forming an ohmic electrode on a substrate;
sequentially forming a silicon dioxide dielectric layer and a silicon nitride dielectric layer on the substrate and the ohmic electrode;
etching the silicon nitride dielectric layer and the silicon dioxide dielectric layer, forming an etching groove at a position corresponding to the middle area of the substrate, wherein the bottom wall of the etching groove is the upper surface of the substrate;
and forming a gate metal layer in the etching groove and on the area adjacent to the silicon nitride dielectric layer.
In one possible implementation, forming an ohmic electrode on the substrate includes:
and manufacturing the ohmic electrode on the upper surface of the substrate by adopting a photoetching-evaporation-stripping method, wherein the substrate is GaN.
In one possible implementation manner, sequentially forming a silicon dioxide dielectric layer and a silicon nitride dielectric layer on the substrate and the ohmic electrode includes:
depositing a silicon dioxide medium on the upper surface of the substrate and the upper surface of the ohmic electrode by using a PEVCD method to form the silicon dioxide medium layer;
and depositing a silicon nitride medium on the upper surface of the silicon dioxide medium layer by using a PEVCD (plasma enhanced chemical vapor deposition) method to form the silicon nitride medium layer.
In a possible implementation manner, etching the silicon nitride dielectric layer and the silicon dioxide dielectric layer, and forming an etching groove at a position corresponding to the middle region of the substrate includes:
coating photoresist on the upper surface of the silicon nitride dielectric layer;
the silicon nitride dielectric layer and the silicon dioxide dielectric layer are combined to form a composite dielectric layer, the etching area in the middle of the composite dielectric layer is exposed and developed, and the V-shaped etching area is exposed to form a V-shaped photoresist shape;
sequentially removing the silicon nitride dielectric layer and the silicon dioxide dielectric layer in the V-shaped etching area by using an ICP (inductively coupled plasma) etching process;
the coated photoresist is removed.
In a possible implementation manner, the silicon nitride dielectric layer and the silicon dioxide dielectric layer are removed by using an ICP etching process to form the inverted trapezoidal etching groove.
In one possible implementation manner, forming a gate metal layer in the etching groove and on a region adjacent to the silicon nitride dielectric layer includes:
coating photoresist on the upper surface of the silicon nitride dielectric layer, exposing and developing the etching groove area to expose the gate metal layer manufacturing area, and forming a T-shaped photoresist shape;
and depositing the gate metal layer on the upper surface of the photoresist by using an electron beam evaporation table, wherein the gate metal layer is sequentially deposited in the areas etched by the ICP etching process on the silicon dioxide dielectric layer and the silicon nitride dielectric layer.
In one possible implementation, the preparation method further includes:
and stripping the T-shaped photoresist morphology by using an organic solvent.
In a possible implementation manner, the photoresist coated on the upper surface of the silicon nitride dielectric layer is a double layer, the thickness of the lower layer photoresist is 0.9 μm to 1 μm, the thickness of the upper layer photoresist is 0.7 μm to 0.8 μm, and the coating area of the lower layer photoresist is smaller than that of the upper layer photoresist.
The preparation method of the GaN HEMT device has the beneficial effects that: compared with the prior art, the preparation method of the GaN HEMT device comprises the steps of manufacturing an ohmic electrode on a substrate, sequentially forming a silicon dioxide dielectric layer and a silicon nitride dielectric layer, etching the silicon nitride dielectric layer and the silicon dioxide dielectric layer, forming an etching groove in the middle of the substrate, and forming a gate metal layer in the etching groove and on the region adjacent to the silicon nitride dielectric layer, so that the technical problems of large gate parasitic capacitance, reduced gain and poor high-frequency characteristic of the GaN HEMT device are solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic view of an ohmic electrode and a GaN surface of a method for manufacturing a GaN HEMT device according to an embodiment of the present invention;
fig. 2 is a schematic view of a surface condition of a deposited composite dielectric layer of a method for manufacturing a GaN HEMT device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a T-shaped etching region of a method for manufacturing a GaN HEMT device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a GaN HEMT device manufacturing method according to an embodiment of the present invention after completion of etching of the composite dielectric layer;
fig. 5 is a schematic diagram after completion of a double-layer adhesive of the method for manufacturing a GaN HEMT device according to the embodiment of the present invention;
fig. 6 is a schematic diagram of a GaN HEMT device according to the method of the present invention after deposition of the gate metal layer;
fig. 7 is a schematic diagram of a GaN HEMT device provided in an embodiment of the present invention after the fabrication process is completed.
Description of reference numerals:
1. a substrate; 2. an ohmic electrode; 3. a silicon dioxide dielectric layer; 4. a silicon nitride dielectric layer; 5. photoresist; 6. the shape of the T-shaped photoresist; 61. a lower layer of photoresist; 62. an upper layer of photoresist; 7. and a gate metal layer.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 7, the present invention provides a GaN HEMT device, including: the device comprises a substrate 1, an ohmic electrode 2, a silicon dioxide dielectric layer 3, a silicon nitride dielectric layer 4 and a gate metal layer 7, wherein the ohmic electrode 2 is formed on the substrate 1; a silicon dioxide dielectric layer 3 is formed on the substrate 1 and the ohmic electrode 2; a silicon nitride dielectric layer 4 is formed on the silicon dioxide dielectric layer 3, etching grooves are formed in the positions, corresponding to the middle area of the substrate 1, of the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3, and the bottom walls of the etching grooves are the upper surface of the substrate 1; a gate metal layer 7 is formed in the etched trench and on the region adjacent to the silicon nitride dielectric layer 4.
The GaN HEMT device provided by the invention has the beneficial effects that: compared with the prior art, the dielectric constant of the silicon dioxide medium and the silicon nitride medium after compounding is smaller, the technical problems of large grid parasitic capacitance, reduced gain and poor high-frequency characteristic of the GaN HEMT device are solved, the silicon dioxide and silicon nitride compound medium is used for replacing the silicon nitride medium, the dielectric constant is reduced, a T-shaped grid (T grid for short) of the compound medium is manufactured, the grid parasitic capacitance of the device is reduced, the GaN HEMT device with low parasitic and high gain is realized, and the high-frequency characteristic is improved.
In some embodiments, referring to FIG. 7, the silicon dioxide dielectric layer 3 has a thickness of 180nm to 200nm, and the silicon nitride dielectric layer 4 has a thickness of 30nm to 50 nm.
The present invention also provides a method for manufacturing a GaN HEMT device, referring to fig. 1 to 7, including:
forming an ohmic electrode 2 on a substrate 1;
sequentially forming a silicon dioxide dielectric layer 3 and a silicon nitride dielectric layer 4 on the substrate 1 and the ohmic electrode 2;
etching the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3, forming an etching groove at a position corresponding to the middle area of the substrate 1, wherein the bottom wall of the etching groove is the upper surface of the substrate 1;
a gate metal layer 7 is formed in the etched trench and on the region adjacent to the silicon nitride dielectric layer 4.
The preparation method of the GaN HEMT device has the beneficial effects that: compared with the prior art, the preparation method of the GaN HEMT device comprises the steps of manufacturing an ohmic electrode 2 on a substrate 1, sequentially forming a silicon dioxide dielectric layer 3 and a silicon nitride dielectric layer 4, etching the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3, forming an etching groove in the middle of the substrate 1, and forming a gate metal layer 7 in the etching groove and on a region adjacent to the silicon nitride dielectric layer 4, so that the technical problems of large gate parasitic capacitance, reduced gain and poor high-frequency characteristic of the GaN HEMT device are solved.
In some embodiments, referring to fig. 1-7, forming an ohmic electrode 2 on a substrate 1 includes:
the ohmic electrode 2 is manufactured on the upper surface of the substrate 1 by adopting a photoetching-evaporation-stripping method, the substrate 1 is GaN, and the ohmic electrode 2 can be manufactured by adopting a manufacturing method in the prior art.
The number of ohmic electrodes 2 deposited on the substrate 1 is 2 and they are spaced apart from each other, and in this embodiment, the number of ohmic electrodes 2 deposited on GaN is 2 and they are spaced apart from each other, and they are uniformly distributed on the upper end surface of the substrate 1(GaN) and have the same height. The dielectric constant of the compounded silicon nitride dielectric layer 4 and silicon dioxide dielectric layer 3 is smaller than that of silicon nitride, so that the gate parasitic capacitance of the HEMT device is smaller, and the gain is not reduced.
In some embodiments, referring to fig. 1-7, a silicon dioxide dielectric layer 3 and a silicon nitride dielectric layer 4 are sequentially formed on the substrate 1 and the ohmic electrode 2, including:
depositing a silicon dioxide medium on the upper surface of the substrate 1 and the upper surface of the ohmic electrode 2 by using a PEVCD method to form a silicon dioxide medium layer 3;
and depositing a silicon nitride medium on the upper surface of the silicon dioxide medium layer 3 by using a PEVCD (plasma enhanced chemical vapor deposition) method to form a silicon nitride medium layer 4.
In the present embodiment, the deposited silicon dioxide dielectric layer 3 is uniformly distributed on the upper end face of the substrate 1 and the upper end face of the ohmic electrode 2, and two continuous zigzag structures are formed in shape.
In the present embodiment, the deposited silicon nitride dielectric layer 4 is uniformly coated on the upper surface of the silicon dioxide dielectric layer 3, and two continuous zigzag structures are formed in shape.
In some embodiments, referring to fig. 1 to 7, the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 are etched, and an etching groove is formed at a position corresponding to the middle region of the substrate 1, including:
the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 are combined to form a composite dielectric layer, the etching area in the middle of the composite dielectric layer is exposed and developed, and the V-shaped etching area is exposed to form the shape of a V-shaped photoresist, namely the area above the middle of the silicon nitride dielectric layer 4, namely the shape of the middle of the photoresist 5;
sequentially removing the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 below the V-shaped etching area by using an ICP (inductively coupled plasma) etching process;
the coated photoresist 5 is removed.
In this embodiment, the shape of the V-shaped photoresist is a shape formed by combining the blank region located above the silicon nitride dielectric layer 4 and the blank region outside the silicon nitride dielectric layer 4, and the etched groove after the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 are removed is in an inverted trapezoid shape. The etching groove is a groove body formed after the middle parts of the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 are etched.
In some embodiments, referring to fig. 1-7, an ICP etching process is used to remove the silicon nitride dielectric layer 4 and the silicon dioxide dielectric layer 3 to form an inverted trapezoidal etching trench.
In some embodiments, referring to fig. 1-7, forming a gate metal layer 7 in the etched trench and on the region adjacent to the silicon nitride dielectric layer 4 includes:
coating photoresist on the upper surface of the silicon nitride dielectric layer 4, exposing and developing the etching groove area to expose the manufacturing area of the gate metal layer 7, and forming a T-shaped photoresist appearance 6;
and depositing a gate metal layer 7 on the upper surface of the photoresist by using an electron beam evaporation table, wherein the gate metal layer 7 is sequentially deposited in the area etched by the ICP etching process on the silicon dioxide dielectric layer 3 and the silicon nitride dielectric layer 4.
In the present embodiment, the electron beam evaporation stage is implemented by conventional techniques in the art to deposit the gate metal layer 7. The T-shaped photoresist feature 6 can also be understood as a post-coated photoresist.
In some embodiments, referring to fig. 1-7, the method further comprises:
the T-photoresist feature 6, i.e., the photoresist coated after stripping, is stripped using an organic solvent. The organic solvent may be various, and the photoresist may be eliminated, which is not limited in the present invention.
In some embodiments, referring to fig. 1-7, the photoresist (T-shaped photoresist feature 6) coated on the upper surface of the silicon nitride dielectric layer 4 is a bilayer, the lower layer photoresist has a thickness of 0.9 μm to 1 μm, the upper layer photoresist has a thickness of 0.7 μm to 0.8 μm, and the coating area of the lower layer photoresist is smaller than that of the upper layer photoresist.
For convenience of understanding, the photoresist layer positioned at the lower layer is defined as a lower layer photoresist 61, and the photoresist layer positioned at the upper layer is defined as an upper layer photoresist 62. The lower layer of photoresist 61 has a small coating area and is coated in two pieces, the middle parts of the two pieces are arranged at intervals, and the etching grooves are exposed; the coating area of the upper layer of photoresist 62 is relatively large, the two photoresist layers are coated, the middle parts of the two photoresist layers are arranged at intervals, and the etching grooves are exposed; the coating thickness of the upper layer of photoresist 62 is smaller than that of the lower layer of photoresist 61, a structure similar to a trapezoid is formed after the upper layer of photoresist 62 is coated, and a structure similar to a few characters is formed after the lower layer of photoresist 61 is coated.
In the embodiment, the ICP etching process adopts the ICP etching process in the prior art, and in operation, etching damage can be selected or adjusted so as to realize low-damage etching.
After the GaN HTMT device is prepared, the method has the beneficial effects of low parasitic capacitance and high gain, and can effectively reduce the gate parasitic capacitance of the device, thereby improving the gain and high-frequency characteristics of the device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A GaN HEMT device, comprising:
a substrate;
an ohmic electrode formed on the substrate;
a silicon dioxide dielectric layer formed on the substrate and the ohmic electrode;
the silicon nitride dielectric layer is formed on the silicon dioxide dielectric layer, etching grooves are formed in the positions, corresponding to the middle area of the substrate, of the silicon nitride dielectric layer and the silicon dioxide dielectric layer, and the bottom walls of the etching grooves are the upper surface of the substrate;
and the gate metal layer is formed in the etching groove and on the area adjacent to the silicon nitride dielectric layer.
2. The GaN HEMT device of claim 1, wherein said silicon dioxide dielectric layer has a thickness of 180nm to 200nm and said silicon nitride dielectric layer has a thickness of 30nm to 50 nm.
3. A preparation method of a GaN HEMT device is characterized by comprising the following steps:
forming an ohmic electrode on a substrate;
sequentially forming a silicon dioxide dielectric layer and a silicon nitride dielectric layer on the substrate and the ohmic electrode;
etching the silicon nitride dielectric layer and the silicon dioxide dielectric layer, forming an etching groove at a position corresponding to the middle area of the substrate, wherein the bottom wall of the etching groove is the upper surface of the substrate;
and forming a gate metal layer in the etching groove and on the area adjacent to the silicon nitride dielectric layer.
4. The method of claim 3, wherein forming an ohmic electrode on the substrate comprises:
and manufacturing the ohmic electrode on the upper surface of the substrate by adopting a photoetching-evaporation-stripping method, wherein the substrate is GaN.
5. The method of claim 3, wherein sequentially forming a silicon dioxide dielectric layer and a silicon nitride dielectric layer on the substrate and the ohmic electrode comprises:
depositing a silicon dioxide medium on the upper surface of the substrate and the upper surface of the ohmic electrode by using a PEVCD method to form the silicon dioxide medium layer;
and depositing a silicon nitride medium on the upper surface of the silicon dioxide medium layer by using a PEVCD (plasma enhanced chemical vapor deposition) method to form the silicon nitride medium layer.
6. The method of claim 3, wherein the etching of the silicon nitride dielectric layer and the silicon dioxide dielectric layer is performed, and an etching groove is formed at a position corresponding to the middle region of the substrate, and the method comprises:
coating photoresist on the upper surface of the silicon nitride dielectric layer;
the silicon nitride dielectric layer and the silicon dioxide dielectric layer are combined to form a composite dielectric layer, the etching area in the middle of the composite dielectric layer is exposed and developed, and the V-shaped etching area is exposed to form a V-shaped photoresist shape;
sequentially removing the silicon nitride dielectric layer and the silicon dioxide dielectric layer in the V-shaped etching area by using an ICP (inductively coupled plasma) etching process;
the coated photoresist is removed.
7. The method of claim 6, wherein the silicon nitride dielectric layer and the silicon dioxide dielectric layer are removed by an ICP etching process to form the inverted trapezoidal etching groove.
8. The method of claim 3, wherein forming a gate metal layer in the etched trench and on a region adjacent to the silicon nitride dielectric layer comprises:
coating photoresist on the upper surface of the silicon nitride dielectric layer, exposing and developing the etching groove area to expose the gate metal layer manufacturing area, and forming a T-shaped photoresist shape;
and depositing the gate metal layer on the upper surface of the photoresist by using an electron beam evaporation table, wherein the gate metal layer is sequentially deposited in the areas etched by the ICP etching process on the silicon dioxide dielectric layer and the silicon nitride dielectric layer.
9. The method of fabricating a GaN HEMT device according to claim 8, further comprising:
and stripping the T-shaped photoresist morphology by using an organic solvent.
10. The method of claim 8, wherein the photoresist coated on the upper surface of the silicon nitride dielectric layer is a double layer, the lower layer photoresist has a thickness of 0.9 μm to 1 μm, the upper layer photoresist has a thickness of 0.7 μm to 0.8 μm, and the coating area of the lower layer photoresist is smaller than that of the upper layer photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004565.3A CN113871466A (en) | 2021-08-30 | 2021-08-30 | GaN HEMT device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111004565.3A CN113871466A (en) | 2021-08-30 | 2021-08-30 | GaN HEMT device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113871466A true CN113871466A (en) | 2021-12-31 |
Family
ID=78988861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111004565.3A Pending CN113871466A (en) | 2021-08-30 | 2021-08-30 | GaN HEMT device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113871466A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507072A (en) * | 2002-11-26 | 2004-06-23 | ��������ͨ���о�Ժ | Semiconductor device with T-shape grid electrode and producing method thereof |
| KR20060010245A (en) * | 2004-07-27 | 2006-02-02 | 학교법인 동국대학교 | Damascene gate in element of semiconductor and method for producing the same |
| KR101078143B1 (en) * | 2010-08-09 | 2011-10-28 | 홍익대학교 산학협력단 | Hetero-junction field effect transistor with multi-layered passivation dielectrics and manufacturing method of the same |
| CN102437182A (en) * | 2011-12-01 | 2012-05-02 | 中国科学院半导体研究所 | SiO2/SiN double layer passivation layer T-typed grid AlGaN/GaN HEMT and manufacturing method thereof |
| JP2018182057A (en) * | 2017-04-13 | 2018-11-15 | 日本電信電話株式会社 | Semiconductor device |
| CN111933523A (en) * | 2020-07-08 | 2020-11-13 | 中电科工程建设有限公司 | Method for manufacturing T-shaped gate for compound semiconductor device |
-
2021
- 2021-08-30 CN CN202111004565.3A patent/CN113871466A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507072A (en) * | 2002-11-26 | 2004-06-23 | ��������ͨ���о�Ժ | Semiconductor device with T-shape grid electrode and producing method thereof |
| KR20060010245A (en) * | 2004-07-27 | 2006-02-02 | 학교법인 동국대학교 | Damascene gate in element of semiconductor and method for producing the same |
| KR101078143B1 (en) * | 2010-08-09 | 2011-10-28 | 홍익대학교 산학협력단 | Hetero-junction field effect transistor with multi-layered passivation dielectrics and manufacturing method of the same |
| CN102437182A (en) * | 2011-12-01 | 2012-05-02 | 中国科学院半导体研究所 | SiO2/SiN double layer passivation layer T-typed grid AlGaN/GaN HEMT and manufacturing method thereof |
| JP2018182057A (en) * | 2017-04-13 | 2018-11-15 | 日本電信電話株式会社 | Semiconductor device |
| CN111933523A (en) * | 2020-07-08 | 2020-11-13 | 中电科工程建设有限公司 | Method for manufacturing T-shaped gate for compound semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8344358B2 (en) | Graphene transistor with a self-aligned gate | |
| WO2021027241A1 (en) | Gan-based radio frequency device having п-shaped gate and manufacturing method therefor | |
| CN111430458B (en) | AlGaAs/GaAs high electron mobility transistor with multi-channel insulating fin gate composite groove gate and preparation method thereof | |
| CN103887335B (en) | Manufacture method of pseudomorphic high electron mobility transistor for improving frequency characteristic | |
| CN103715255B (en) | A kind of sag GaN HEMT device and preparation method thereof | |
| WO2021027242A1 (en) | Gan-based mis-hemt device having г-shaped gate and preparation method | |
| JPWO2007058265A1 (en) | Bipolar transistor and manufacturing method thereof | |
| CN117790575A (en) | Gate-around field effect transistor based on gallium oxide substrate and preparation method thereof | |
| CN105448713B (en) | A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method | |
| CN105047548A (en) | Method for manufacturing 10-nanometer T-shaped gate through electron beam lithography | |
| CN113871466A (en) | GaN HEMT device and preparation method thereof | |
| CN107302022A (en) | Low injured surface processing high efficiency device and preparation method thereof | |
| CN111430459B (en) | AlGaAs/GaAs high electron mobility transistor and preparation method thereof | |
| CN112599589B (en) | Semiconductor device and preparation method | |
| CN102064104B (en) | Method for manufacturing T-shaped grid of GaN microwave device | |
| WO2017190511A1 (en) | Field emission device and manufacturing method therefor | |
| CN112186033A (en) | Gallium nitride junction barrier Schottky diode with slant field plate and manufacturing method thereof | |
| CN1034894C (en) | Self-alignment production method for high electron mobility transistor | |
| CN107644833A (en) | A kind of gallium nitride device Making programme of effectively lifting high frequency performance | |
| KR100497840B1 (en) | Manufacturing method for Heterojunction bipolar transistor, HBT therefrom | |
| CN113540229B (en) | Semiconductor device and method for manufacturing the same | |
| WO2024105724A1 (en) | Bipolar transistor and method for manufacturing same | |
| CN107346720B (en) | Field emission device and manufacturing method thereof | |
| CN108010844B (en) | HEMT device and preparation method thereof | |
| CN114242587A (en) | GaN HEMT device with air gap structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20230802 Address after: No. 113 Hezuo Road, High tech Zone, Shijiazhuang City, Hebei Province, 050000 Applicant after: Hebei Zhongci Electronic Technology Co.,Ltd. Shijiazhuang High tech Branch Address before: 050051 No. 113, cooperation Road, Shijiazhuang, Hebei Applicant before: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY Group Corp. |