CN102064104B - Method for manufacturing T-shaped grid of GaN microwave device - Google Patents
Method for manufacturing T-shaped grid of GaN microwave device Download PDFInfo
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- CN102064104B CN102064104B CN201010579121A CN201010579121A CN102064104B CN 102064104 B CN102064104 B CN 102064104B CN 201010579121 A CN201010579121 A CN 201010579121A CN 201010579121 A CN201010579121 A CN 201010579121A CN 102064104 B CN102064104 B CN 102064104B
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Abstract
The invention discloses a method for manufacturing a T-shaped grid of a GaN microwave device. The method comprises the following steps: (1) growing a high temperature dielectric layer on a GaN substrate, wherein the ingredient of the high temperature dielectric layer is Si3N4; (2) growing a low temperature dielectric layer on the upper surface of the high temperature dielectric layer, wherein the ingredient of the low temperature dielectric layer is SiOxNy; (3) photoetching a grid groove photoetched pattern in a required size on the low temperature dielectric layer, etching a grid groove on the low temperature dielectric layer and the high temperature dielectric layer through dry etching and removing the residual photoresist; (4) photoetching a grid cover photoetched pattern aligned with the grid groove on the low temperature dielectric layer; and (5) manufacturing a Schottky electrode on the GaN substrate in the grid cover pattern. By adopting the method, the grid length is easier to control and the reliability of the GaN microwave device is improved.
Description
Technical field
The present invention relates to semiconductor device structure design and fabrication method, especially a kind of manufacture method of GaN microwave device T type grid.
Background technology
The GaN material has good characteristics such as broad stopband, high critical breakdown electric field, high heat conductance, high carrier saturation drift velocity because of it, determined the advantage of using in microwave, millimeter wave field based on its GaN base power device.
Improving constantly of frequency characteristic makes the grid manufacture craft of GaN base power device mainly adopt the noncontact photoetching technique (as direct electronic beam writing technology, stepping projection lithography technology etc.) carrying out grid makes, its method commonly used is: coating three layer photoetching glue on the GaN substrate, and carry out a photoetching and obtain the grid litho pattern.The shortcoming of this method maximum is process conditions are required comparatively harsh, and the grid shape is wayward, and the repeatability of technology and less stable; And often occur in the T type grid structure of made between grid foot and the deielectric-coating having the cavity, the grid metal can't be filled full drawback, as application number be 00105221.7 and application number be 02124062.0 Chinese patent; The existence of air-conditioning has reduced the reliability of GaN base power device to a great extent.
Summary of the invention
The technical problem to be solved in the present invention provides the manufacture method of the GaN microwave device T type grid that a kind of grid length is controlled easily, reliability is high.
For solving the problems of the technologies described above, the technical solution used in the present invention is making according to following step of described T type grid:
1. growth high-temperature medium layer on the GaN substrate, the composition of described high-temperature medium layer is Si
3N
4
2. at the upper surface growing low temperature dielectric layer of described high-temperature medium layer, the composition of described cryogenic media layer is SiO
xN
y
3. on above-mentioned cryogenic media layer, adopt single-layer lithography glue to make the litho pattern of the grid recess of required size by lithography, adopt to be dry-etched on described cryogenic media layer and the high-temperature medium layer again to etch grid recess, and remove remaining photoresist;
4. on the cryogenic media layer, adopt multilevel resist to make by lithography and described grid recess alignment grid grid cover litho pattern;
5. in above-mentioned grid cover litho pattern, make the Schottky barrier gate on the GaN matrix.
Preferably, the thickness of described high-temperature medium layer is 100 ± 20 dusts; The thickness of described cryogenic media layer is 1500 ± 200 dusts.
Preferably, step 3. described in the grid recess litho pattern adopt inductively coupled plasma or reactive ion etching process.
The metal level of Schottky barrier gate is made of nickel dam, platinum layer and gold layer or nickel dam, molybdenum layer and gold layer.
Also comprise after 5. in step and to increase step 6.: at Schottky barrier gate surface deposition passivation layer, the composition of described passivation layer is Si
3N
4
Adopt the groove structure of high-temperature medium film and the film formed composite dielectric film of cryogenic media in the technique scheme, the grid making is divided into two step process, promptly make by long size of composite dielectric film groove control gate and Schottky barrier gate.Owing to adopt the size of individual layer glue photoetching litho pattern more easy to control, thereby improved the controlled of the long sizes of grid; And utilize the different choice specific characteristic of composite dielectric film etching, and obtained falling trapezoidal grid foot shape, avoided existing between the normal grid foot that occurs and passivation layer in the T type grid structure drawback in cavity, reduced the grid parasitic parameter; In addition,, improved the puncture voltage of device, realized high voltage operation, improved device performance comprehensively because the existence of composite dielectric film is played passivation to the surf zone beyond the Schottky barrier, thereby significantly reduced the electric leakage of device.
Adopt the beneficial effect that technique scheme produced to be: different with direct writing technology of grid pattern commonly used, the present invention is more obvious to the very little control advantage of grid full size, also can carry out the optimization of grid pattern better, help reducing parasitic parameters such as gate resistance and electric capacity, thereby the grid characteristic of raising device and noise characteristic etc. also can have higher controllability to the device frequency characteristic.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1-Fig. 7 is the cross-sectional view in the T type grid preparation process of the present invention.
Embodiment
Referring to Fig. 1-Fig. 7, the step of preparation T type grid of the present invention is as follows:
1. growth high-temperature medium layer 2 on GaN substrate 1, the composition of described high-temperature medium layer 2 is Si
3N
4
At first clean is carried out on the surface of GaN substrate 1, cleaning step is: trichloroethanes soaked 5-10 minute; Acetone soaked 5-10 minute; Isopropyl alcohol soaked 5-10 minute; Last deionized water rinsing 5-10 minute.
Adopt MOVCD(Metal-organic Chemical Vapor DePosition then, the metallo-organic compound CVD (Chemical Vapor Deposition) method) growth technique making Si
3N
4, growth temperature is 1000 ℃-1200 ℃, Si
3N
4Thickness 100 dusts ± 20 dusts.
2. at the upper surface growing low temperature dielectric layer 3 of above-mentioned high-temperature medium layer 2, the composition of described cryogenic media layer 3 is SiO
xN
y
Described cryogenic media layer 3 adopts PECVD(plasma-enhanced chemical vapor deposition, plasma-reinforced chemical vapor deposition) growth technique, reacting gas is silane and nitrogen, 280 ℃-320 ℃ of growth temperatures, SiO
xN
yThickness be 1500 dusts ± 200 dusts.
3. on above-mentioned cryogenic media layer 3, adopt single-layer lithography glue to make the grid recess litho pattern of required size by lithography, adopt to be dry-etched on described cryogenic media layer 3 and the high-temperature medium layer 2 again to etch grid recess, and remove remaining photoresist.
Concrete steps are as follows:
At first, upper surface at cryogenic media layer 3 carries out coating technique, the glue type is a PMMA individual layer glue, thick 2500 dusts of glue ± 500 dusts, utilize electron-beam direct writing technology, expose, developing procedure, obtain the grid recess litho pattern 4 of 0.25 μ m ± 0.05 μ m, individual layer glue plays the effect of mask, referring to Fig. 2.This step process requires the highest to the equipment alignment precision, adopt the direct electronic beam writing technology alignment precision can reach 0.01 μ m.Adopt individual layer glue directly to write technology, dimension of picture control is more prone to, and repeatability and consistency are also better.To the 0.25 μ m grid recess litho pattern of being manufactured, dimensional discrepancy is less than 10%.
Then, adopting the RIE(reactive ion etching) etching technics etches grid recess 5 on cryogenic media layer 3 and high-temperature medium layer 2, and the etching of control high-temperature medium layer 2 and cryogenic media layer 3 is than being 10:1, referring to Fig. 4.Reacting gas is fluoroform and oxygen, and this step operation should be selected ratio and thickness according to etch rate between the different medium film, can accurately control etch period, avoids over etching.
To remaining photoresist, adopt oxygen plasma to remove, basis of time cull thickness and deciding.
Above-mentioned steps 3. in, the groove size of grid recess 5 and litho pattern size are relevant with etching technics control, pattern is relevant with the composition and the thickness of composite dielectric film.Present embodiment is by the composition and the thickness of control composite dielectric film, and the grid recess 5 of gained is an inverted trapezoidal structure, and trapezoidal bottom width is the long sizes of effective grid of T type grid; Inverted trapezoidal structure has effectively been avoided having the cavity between the grid foot that occurs in the T type grid structure and the deielectric-coating, and the grid metal can't be filled full problem.Be of a size of 0.25 μ m ± 0.05 μ m after the grid recess etching, the controllability height.
4. on cryogenic media layer 3, adopt multilevel resist to make the grid cover litho pattern of aiming at described grid recess by lithography.
GaN substrate behind the etching grid recess 51 is carried out surface cleaning processing.Cleaning step is: trichloroethanes soaked 5-10 minute, and acetone soaked 5-10 minute, and isopropyl alcohol soaked 5-10 minute, and last deionized water rinsing 5-10 minute, nitrogen blew 1-3 minute.
Carry out coating technique then, adopting the glue type is the PMMA glue of C4 and C5, the thickness of photoresist is respectively 2500 dusts ± 500 dusts and 10000 dusts ± 1000 dusts, utilizes direct electronic beam writing technology GaN substrate 1 to be carried out operations such as exposure imaging, obtains the grid cover litho pattern 6 of 1.25 μ m ± 0.05 μ m.
5. in above-mentioned grid cover litho pattern 6, make the Schottky barrier gate on the GaN matrix 1
Adopt electron beam evaporation deposition technology to carry out the making of metal gate 7, metal gate 7 is made up of titanium layer, platinum layer and gold layer, and thickness is respectively 500 dusts ± 50 dusts, 500 dusts ± 50 dusts and 7000 dusts ± 700 dusts.
After metal gate 7 evaporates, adopt stripping technology to obtain Schottky barrier gate 8, concrete operation is: described GaN substrate is soaked 5-10 minute (100 ℃) in 1165 photoresist lift off liquid; In trichloroethanes, soak 5-10 minute (40 ℃), acetone immersion 5-10 minute (40 ℃), 5-10 minute (25 ℃) of isopropyl alcohol immersion then successively; Last deionized water rinsing 5-10 minute, nitrogen blew 1-3 minute.Obtain the Schottky barrier gate 8 of T type as shown in Figure 7.
6. at the basic barrier gate surface deposition of spy passivation layer, the composition of described passivation layer is Si
3N
4
Adopt the PECVD growth technique, reacting gas is silane and laughing gas, 280 ℃-320 ℃ of growth temperatures, Si
3N
4Thickness be 500 dusts ± 100 dusts.
In sum, the present invention is different with direct writing technology of grid pattern commonly used, adopting direct electronic beam writing technology to carry out twice grid pattern makes, it is more obvious to the very little control advantage of grid full size, also can carry out the optimization of grid pattern better, help reducing parasitic parameters such as gate resistance and electric capacity, improve the reliability of device.
Claims (8)
1. the manufacture method of GaN microwave device T type grid is characterized in that comprising the steps:
1. go up growth high-temperature medium layer (2) at GaN substrate (1), the composition of described high-temperature medium layer (2) is Si
3N
4
2. at the upper surface growing low temperature dielectric layer (3) of described high-temperature medium layer (2), the composition of described cryogenic media layer (3) is SiO
xN
y, x＞0, y＞0;
3. going up at above-mentioned cryogenic media layer (3) adopts single-layer lithography glue to make the litho pattern (4) of the grid recess of required size by lithography, adopt to be dry-etched on described cryogenic media layer (3) and the high-temperature medium layer (2) again to etch grid recess (5), and remove remaining photoresist;
4. going up at cryogenic media layer (3) adopts multilevel resist to make the grid cover litho pattern of aiming at described grid recess (5) (6) by lithography;
5. in above-mentioned grid cover litho pattern (6), make the Schottky barrier gate (8) on the GaN matrix (1).
2. the manufacture method of GaN microwave device T type grid according to claim 1, the thickness that it is characterized in that described high-temperature medium layer (2) is 100 ± 20 dusts; The thickness of described cryogenic media layer (3) is 1500 ± 200 dusts.
3. the manufacture method of GaN microwave device T type grid according to claim 2 is characterized in that the 1. middle high-temperature medium layer of step adopts the MOCVD growth technique.
4. the manufacture method of GaN microwave device T type grid according to claim 3 is characterized in that the 2. middle cryogenic media layer of step adopts the PECVD growth technique.
5. the manufacture method of GaN microwave device T type grid according to claim 4 is characterized in that grid recess described in step 3. adopts inductively coupled plasma or reactive ion etching process.
6. the manufacture method of GaN microwave device T type grid according to claim 1 is characterized in that the metal level of Schottky barrier gate described in step 5. (8) is made of nickel dam, platinum layer and gold layer or nickel dam, molybdenum layer and gold layer.
7. the manufacture method of GaN microwave device T type grid according to claim 1, it is characterized in that also comprising after 5. in step increasing step 6.: at Schottky barrier gate (8) surface deposition passivation layer, the composition of described passivation layer is Si
3N
4
8. the manufacture method of GaN microwave device T type grid according to claim 7 is characterized in that described passivation layer adopts pecvd process.
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| CN102437182A (en) * | 2011-12-01 | 2012-05-02 | 中国科学院半导体研究所 | SiO2/SiN double layer passivation layer T-typed grid AlGaN/GaN HEMT and manufacturing method thereof |
| CN108172512A (en) * | 2017-12-27 | 2018-06-15 | 成都海威华芯科技有限公司 | A kind of T-shaped grid preparation method for increasing silicon nitride medium angle of groove inclination degree |
| CN112509912B (en) * | 2021-02-03 | 2021-04-30 | 成都市克莱微波科技有限公司 | Preparation method of semiconductor device |
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|---|---|---|---|---|
| US6271128B1 (en) * | 2000-09-29 | 2001-08-07 | Vanguard International Semiconductor Corp. | Method for fabricating transistor |
| CN1373502A (en) * | 2001-03-02 | 2002-10-09 | 中国科学院微电子中心 | Process for preparing metal pattern of T-shaped emitter or grid of transistor |
| CN101276750A (en) * | 2007-03-28 | 2008-10-01 | 中国科学院微电子研究所 | Method for preparing transistor T type nano grid |
| CN101431020A (en) * | 2007-11-09 | 2009-05-13 | 上海华虹Nec电子有限公司 | Production method of T type polysilicon gate electrode |
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| JPH0982727A (en) * | 1995-09-14 | 1997-03-28 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US6737202B2 (en) * | 2002-02-22 | 2004-05-18 | Motorola, Inc. | Method of fabricating a tiered structure using a multi-layered resist stack and use |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271128B1 (en) * | 2000-09-29 | 2001-08-07 | Vanguard International Semiconductor Corp. | Method for fabricating transistor |
| CN1373502A (en) * | 2001-03-02 | 2002-10-09 | 中国科学院微电子中心 | Process for preparing metal pattern of T-shaped emitter or grid of transistor |
| CN101276750A (en) * | 2007-03-28 | 2008-10-01 | 中国科学院微电子研究所 | Method for preparing transistor T type nano grid |
| CN101431020A (en) * | 2007-11-09 | 2009-05-13 | 上海华虹Nec电子有限公司 | Production method of T type polysilicon gate electrode |
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