CN113825057B - Bluetooth headset charging box boost circuit - Google Patents
Bluetooth headset charging box boost circuit Download PDFInfo
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- CN113825057B CN113825057B CN202110938781.9A CN202110938781A CN113825057B CN 113825057 B CN113825057 B CN 113825057B CN 202110938781 A CN202110938781 A CN 202110938781A CN 113825057 B CN113825057 B CN 113825057B
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- 238000006243 chemical reaction Methods 0.000 abstract description 12
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- 230000001360 synchronised effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000000243 photosynthetic effect Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R1/00—Details of transducers, loudspeakers or microphones
- H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
- H04R1/1025—Accumulators or arrangements for charging
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Abstract
The invention relates to a Bluetooth headset charging box booster circuit, which comprises a first power input end, a second power input end, a first power output end, a second power output end, a first charge pump switch bridge circuit, a second charge pump switch bridge circuit, an output storage capacitor unit, a first signal output circuit and a second signal output circuit, wherein the first signal output circuit and the second signal output circuit have 50% duty ratio and opposite phases; the first charge pump switch bridge circuit and the second charge pump switch bridge circuit comprise a first charge temporary capacitor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit and a photoelectric coupler; the switch capacitor type boost is adopted, so that the conversion efficiency is greatly improved, and particularly, the output storage capacitor unit is in a linear state and continuously outputs, the influence of the switching frequency is avoided, the conventional switch type buck charging circuit can be used at the subsequent earphone end, and the total conversion efficiency is greatly improved.
Description
Technical Field
The invention relates to the technical field of manufacturing of Bluetooth headphones, in particular to a Bluetooth headphone charging box booster circuit.
Background
With the elimination of the 3.5 interface of the mobile phone, a true wireless Bluetooth headset is also a mainstream, and the true wireless Bluetooth headset consists of two headsets and a charging box. In order to consider portability, the whole product appearance is smaller and more exquisite, the duration is required to be longer and longer, and even the duration is used as a main selling point, so that better market acceptance and acceptance are obtained.
The current earphone uses the principle that the current in the inductor cannot be suddenly changed to boost the voltage of the battery with 3.7V in the charging box to 5V, then converts the 5V into the voltage (usually 3.0-4.2V) required by the battery at the earphone end, and charges the battery into the earphone. In the process, the charging box booster circuit is in a switch mode, the efficiency of the switch frequency from 200KHz to 2MHz can be over 95 percent, and the charging circuit in the earphone can only be in a linear working mode due to the synchronous problem of the earphone and the charging box switch (the switch is not synchronous and can not normally transmit electric energy), so that the average efficiency is about 65 percent. During this voltage step-down transition, the overall efficiency is below 62%.
However, the electric energy stored in the battery of the charging box is limited, but more than 1/3 of energy is lost in practical use, and the energy-saving requirement is not met. In addition, the endurance time is longer in a limited space, and the improvement of the charging conversion efficiency of the charging box to the earphone is a primary problem which needs to be solved. From the above data, the linear charging circuit in the earphone is mainly lost, if the circuit can be designed to be switched-mode charging, the conversion efficiency can be improved, so that the frequency synchronization is a problem, and if the problem is avoided, a new scheme is needed to solve the pain point.
Accordingly, in the present patent application, the applicant has studied a booster circuit of a charging box of a bluetooth headset to solve the above-mentioned problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention mainly aims to provide a Bluetooth headset charging box booster circuit, which is realized by adopting switched capacitor boosting, so that the conversion efficiency is greatly improved and can reach more than 97 percent, particularly, an output storage capacitor unit is in a linear state and continuously outputs, the influence of switching frequency is avoided, the subsequent headset end can use the conventional switched-mode buck charging circuit, and the maximum value of the total conversion efficiency can be improved to 92 percent.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a Bluetooth headset charging box boost circuit comprises a first power input end, a second power input end, a first power output end, a second power output end, a first charge pump switch bridge circuit, a second charge pump switch bridge circuit, an output storage capacitor unit, a first signal output circuit and a second signal output circuit, wherein the first signal output circuit and the second signal output circuit have 50% duty ratio and opposite phases;
the first charge pump switch bridge circuit and the second charge pump switch bridge circuit comprise a first charge temporary storage capacitor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit for driving the first switch unit, a sixth switch unit for driving the second switch unit and a photoelectric coupler for driving the fourth switch unit;
the first switch unit and the second switch unit are connected in series, a non-series node of the first switch unit is connected with the first power input end, and a non-series node of the second switch unit is connected with the first power output end; the two ends of the output storage capacitor unit are respectively connected with a first power supply output end and a second power supply output end, and the second power supply output end is connected with a sixth switch unit;
the third switch unit and the fourth switch unit are connected in series, a non-series node of the third switch unit is connected with the second power input end, a non-series node of the fourth switch unit is connected with the first power input end, and a series node of the first switch unit and the second switch unit is connected with a series node of the third switch unit and the fourth switch unit through a first charge temporary capacitor; the two ends of the first charge temporary storage capacitor are connected with a second charge temporary storage capacitor in parallel;
the first signal output circuit is respectively connected with a third switch unit of the first charge pump switch bridge circuit, a fifth switch unit of the first charge pump switch bridge circuit, a sixth switch unit of the second charge pump switch bridge circuit and a photoelectric coupler of the second charge pump switch bridge circuit;
the second signal output circuit is respectively connected with a sixth switch unit of the first charge pump switch bridge circuit, a photoelectric coupler of the first charge pump switch bridge circuit, a third switch unit of the second charge pump switch bridge circuit and a fifth switch unit of the second charge pump switch bridge circuit;
the photoelectric coupler comprises a light emitting diode and a phototriode;
the collector of the phototriode is connected with the first switch unit, the emitter of the phototriode is connected with the fourth switch unit, the anode of the light emitting diode of the first charge pump switch bridge circuit is connected with the second signal output circuit through the fourth resistor, and the anode of the light emitting diode of the second charge pump switch bridge circuit is connected with the first signal output circuit through the fourth resistor.
As a preferred scheme, the first switch unit comprises a first switch tube and a first resistor;
the first end of the first switching tube is connected with a first power input end, the second end of the first switching tube is connected with a second switching unit and a first charge temporary storage capacitor, the control end of the first switching tube is connected with the first end of the first switching tube through a first resistor, and the control end of the first switching tube is also connected with a fifth switching unit;
the first switch unit of the first charge pump switch bridge circuit further comprises a power supply filter capacitor, and two ends of the power supply filter capacitor are respectively connected with the first power supply input end and the second power supply input end.
As a preferred scheme, the second switching unit comprises a second switching tube and a second resistor;
the first end of the second switching tube is connected with the first switching unit and the first charge temporary storage capacitor, the second end of the second switching tube is connected with the first power output end, the control end of the second switching tube is connected with the first end of the second switching tube through the second resistor, and the control end of the second switching tube is also connected with the sixth switching unit.
As a preferable scheme, the third switching unit comprises a third switching tube, a first end of the third switching tube is connected with the second power input end, a second end of the third switching tube is connected with the fourth switching unit and the first charge temporary storage capacitor, and the first signal output circuit is connected with the control end of the third switching tube.
As a preferable scheme, the fourth switching unit comprises a fourth switching tube and a third resistor;
the first end of the fourth switching tube is connected with the third switching unit and the first charge temporary storage capacitor, the second end of the fourth switching tube is connected with the first power input end, the control end of the fourth switching tube is connected with the photoelectric coupler, and the control end of the fourth switching tube is also connected with the first end of the fourth switching tube through the third resistor.
As a preferable scheme, the fifth switching unit comprises a fifth switching tube, a first end of the fifth switching tube is connected with the first power input end and grounded, and a second end of the fifth switching tube is connected with the first switching unit;
the control end of the fifth switching tube of the first charge pump switching bridge circuit is connected with the first signal output circuit, and the control end of the fifth switching tube of the second charge pump switching bridge circuit is connected with the second signal output circuit.
As a preferable scheme, the sixth switching unit comprises a sixth switching tube, a first end of the sixth switching tube is connected with the second power supply output end and grounded, and a second end of the sixth switching tube is connected with the second switching unit;
the control end of a sixth switching tube of the first charge pump switching bridge circuit is connected with the second signal output circuit, and the control end of the sixth switching tube of the second charge pump switching bridge circuit is connected with the first signal output circuit.
As a preferable scheme, the output storage capacitor unit comprises a first sub-output storage capacitor and a second sub-output storage capacitor which are connected in series, wherein a non-series node of the first sub-output storage capacitor is connected with a first power supply output end, a non-series node of the second sub-output storage capacitor is connected with a second power supply output end, and a series node of the first sub-output storage capacitor and the second sub-output storage capacitor is connected with a first power supply input end.
Compared with the prior art, the invention has obvious advantages and beneficial effects, in particular: the switching capacitor type voltage-reducing charging circuit mainly adopts the matching of a first charge pump switching bridge circuit, a second charge pump switching bridge circuit, a first signal output circuit and a second signal output circuit, wherein the duty ratio of the first signal output circuit is 50% and the phases of the first signal output circuit and the second signal output circuit are opposite, so that the switching capacitor type voltage-reducing charging circuit greatly improves the conversion efficiency;
and a plurality of switching tubes can select a high-power switching tube according to the requirement, and then the situation that the voltage output is 2 times or the single power supply is changed into the double power supply in any occasion can be realized under the condition that the power supply current is enough.
In order to more clearly illustrate the structural features and efficacy of the present invention, a detailed description thereof will be given below with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a circuit structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the first signal output circuit and the second signal output circuit according to the embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of another embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and detailed description.
As shown in fig. 1 to 3, a boost circuit of a bluetooth headset charging box includes a first power input end, a second power input end, a first power output end, a second power output end, a first charge pump switch bridge circuit, a second charge pump switch bridge circuit, an output storage capacitor unit, a first signal output circuit and a second signal output circuit, wherein the first signal output circuit and the second signal output circuit have a duty ratio of 50% and opposite phases;
the first charge pump switch bridge circuit and the second charge pump switch bridge circuit comprise a first charge temporary storage capacitor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit for driving the first switch unit, a sixth switch unit for driving the second switch unit and a photoelectric coupler for driving the fourth switch unit;
the first switch unit and the second switch unit are connected in series, a non-series node of the first switch unit is connected with the first power input end, and a non-series node of the second switch unit is connected with the first power output end; the two ends of the output storage capacitor unit are respectively connected with a first power supply output end and a second power supply output end, and the second power supply output end is connected with a sixth switch unit;
the third switch unit and the fourth switch unit are connected in series, a non-series node of the third switch unit is connected with the second power input end, a non-series node of the fourth switch unit is connected with the first power input end, and a series node of the first switch unit and the second switch unit is connected with a series node of the third switch unit and the fourth switch unit through a first charge temporary capacitor.
In this embodiment, the first charge temporary capacitor and the second charge temporary capacitor of the first charge pump switching bridge circuit are a capacitor C3 and a capacitor C5, respectively; the first charge temporary capacitor and the second charge temporary capacitor of the second charge pump switch bridge circuit are a capacitor C4 and a capacitor C6 respectively; in this embodiment, the output storage capacitor unit is a capacitor C7.
The first signal output circuit is respectively connected with a third switch unit of the first charge pump switch bridge circuit, a fifth switch unit of the first charge pump switch bridge circuit, a sixth switch unit of the second charge pump switch bridge circuit and a photoelectric coupler of the second charge pump switch bridge circuit;
the second signal output circuit is respectively connected with a sixth switch unit of the first charge pump switch bridge circuit, a photoelectric coupler of the first charge pump switch bridge circuit, a third switch unit of the second charge pump switch bridge circuit and a fifth switch unit of the second charge pump switch bridge circuit.
Preferably, the first switching unit includes a first switching tube and a first resistor, where the first switching tube is a PMOS tube or a PNP triode, which is not limited herein.
The first end of the first switching tube is connected with a first power input end, the second end of the first switching tube is connected with a second switching unit and a first charge temporary storage capacitor, the control end of the first switching tube is connected with the first end of the first switching tube through a first resistor, and the control end of the first switching tube is also connected with a fifth switching unit;
the first switch unit of the first charge pump switch bridge circuit further comprises a power supply filter capacitor, and two ends of the power supply filter capacitor are respectively connected with the first power supply input end and the second power supply input end. In this embodiment, the power filter capacitor is a polarity capacitor C1, and the positive electrode and the negative electrode of the polarity capacitor C1 are respectively connected to the first power input end and the second power input end. In this embodiment, the first switching tube and the first resistor of the first charge pump switching bridge circuit are a PMOS tube Q1 and a resistor R1, respectively; the first switch tube and the first resistor of the second charge pump switch bridge circuit are a PMOS tube Q3 and a resistor R4 respectively.
Preferably, the second switching unit includes a second switching tube and a second resistor, where the second switching tube is a PMOS tube or a PNP triode, which is not limited herein.
The first end of the second switching tube is connected with the first switching unit and the first charge temporary storage capacitor, the second end of the second switching tube is connected with the first power output end, the control end of the second switching tube is connected with the first end of the second switching tube through the second resistor, and the control end of the second switching tube is also connected with the sixth switching unit. In this embodiment, the second switching tube and the second resistor of the first charge pump switching bridge circuit are a PMOS tube Q2 and a resistor R3, respectively; the second switching tube and the second resistor of the second charge pump switching bridge circuit are a PMOS tube Q4 and a resistor R6 respectively.
Preferably, the third switching unit includes a third switching tube, and the third switching tube is an NMOS tube or an NPN triode, which is not limited herein.
The first end of the third switching tube is connected with the second power input end, the second end of the third switching tube is connected with the fourth switching unit and the first charge temporary storage capacitor, and the first signal output circuit is connected with the control end of the third switching tube. In this embodiment, the third switching tube of the first charge pump switching bridge circuit is an NMOS tube Q7; the third switching tube of the second charge pump switching bridge circuit is an NMOS tube Q11.
The fourth switching unit comprises a fourth switching tube and a third resistor, wherein the fourth switching tube is an NMOS tube or an NPN triode, and the fourth switching tube is not limited herein.
The first end of the fourth switching tube is connected with the third switching unit and the first charge temporary storage capacitor, the second end of the fourth switching tube is connected with the first power input end, the control end of the fourth switching tube is connected with the photoelectric coupler, and the control end of the fourth switching tube is also connected with the first end of the fourth switching tube through the third resistor. In this embodiment, the fourth switching tube and the third resistor of the first charge pump switching bridge circuit are respectively an NMOS tube Q9 and a resistor R2; the fourth switching tube and the third resistor of the second charge pump switching bridge circuit are an NMOS tube Q13 and a resistor R5 respectively.
The fifth switching unit includes a fifth switching tube, where the fifth switching tube is an NMOS tube or an NPN triode, which is not limited herein. The first end of the fifth switching tube is connected with the first power input end and grounded, and the second end of the fifth switching tube is connected with the first switching unit;
the control end of the fifth switching tube of the first charge pump switching bridge circuit is connected with the first signal output circuit, and the control end of the fifth switching tube of the second charge pump switching bridge circuit is connected with the second signal output circuit. In this embodiment, the fifth switching tube of the first charge pump switching bridge circuit is an NMOS tube Q8; the fifth switching tube of the second charge pump switching bridge circuit is an NMOS tube Q12.
The sixth switching unit includes a sixth switching tube, where the sixth switching tube is an NMOS tube or an NPN triode, which is not limited herein. The first end of the sixth switching tube is connected with the second power supply output end and grounded, and the second end of the sixth switching tube is connected with the second switching unit;
the control end of a sixth switching tube of the first charge pump switching bridge circuit is connected with the second signal output circuit, and the control end of the sixth switching tube of the second charge pump switching bridge circuit is connected with the first signal output circuit. In this embodiment, the sixth switching tube of the first charge pump switching bridge circuit is an NMOS tube Q10; the sixth switching tube of the second charge pump switching bridge circuit is an NMOS tube Q14.
The photoelectric coupler comprises a light emitting diode and a phototriode;
the collector of the phototriode is connected with a first switch unit, the emitter of the phototriode is connected with a fourth switch unit,
the anode of the light-emitting diode of the first charge pump switch bridge circuit is connected with the second signal output circuit through a fourth resistor, and the anode of the light-emitting diode of the second charge pump switch bridge circuit is connected with the first signal output circuit through a fourth resistor. In this embodiment, the photo coupler of the first charge pump switching bridge circuit is a photo coupler Q5, the light emitting diode and the phototransistor thereof are a light emitting diode Q5A and a phototransistor Q5B, respectively, and the photo coupler of the first charge pump switching bridge circuit is a photo coupler Q6, the light emitting diode and the phototransistor thereof are a light emitting diode Q5A and a phototransistor Q5B, respectively.
It should be noted that, the first ends of all the switching tubes are emitters of the triodes or sources of the MOS tubes, the second ends of all the switching tubes are collectors of the triodes or drains of the MOS tubes, and the control ends of all the switching tubes are bases of the triodes or gates of the MOS tubes. In this embodiment, as shown in fig. 2, the first signal output circuit and the second signal output circuit are square wave signal generator circuits with 50% duty ratio and opposite phases, which are conventional general purpose oscillating circuits, and of course, the first signal output circuit and the second signal output circuit may also be formed by two paths of PWM square wave signals with 50% duty ratio and opposite phases output by GPIO ports of a singlechip.
The following generally describes the following working principles:
as shown in fig. 1, PWM1 is a signal output by the first signal output circuit, and PWM2 is a signal output by the second signal output circuit.
First, the principle of the first charge pump switching bridge circuit will be described: when the signal PWM1 is IN high potential, the NMOS tube Q7, the NMOS tube Q8 and the PMOS tube Q1 are conducted, at this time, the electric energy of the first power input end IN+ and the second power input end IN-charges the capacitor C3 and the capacitor C5 through the PMOS tube Q1 and the NMOS tube Q7, and as the PMOS tube Q1 and the NMOS tube Q7 are saturated and conducted and the impedance is only a few milliohms, the voltage at the two ends of the capacitor C3 and the capacitor C5 is quickly charged to the VCC voltage level.
Meanwhile, PWM2 is low potential, the photosynthetic coupler Q5, the NMOS tube Q10, the PMOS tube Q2 and the NMOS tube Q9 are all non-conductive, and the following circuits have no effect. When the PWM1 becomes low potential, the NMOS tube Q7, the NMOS tube Q8 and the PMOS tube Q1 are not conducted, at the moment, the capacitor C3 and the capacitor C5 are completely disconnected from the first power input end IN+ and the second power input end IN-, meanwhile, the PWM2 becomes high potential, the photosynthetic coupler Q5, the NMOS tube Q10, the PMOS tube Q2 and the NMOS tube Q9 are conducted, at the moment, the electric energy stored IN the capacitor C3 and the capacitor C5 charges the capacitor C7 through the PMOS tube Q2 and the NMOS tube Q9, and the voltage at two ends of the capacitor C7 is quickly charged to the voltage level of the capacitor C3 and the capacitor C5 due to the fact that the saturated conduction impedance of the PMOS tube Q2 and the NMOS tube Q9 is only a few milliohms, so that the electric energy of the first power input end IN+ and the second power input end IN-is converted into the capacitor C7 IN a cycle.
Because the load exists all the time, when the PMOS tube Q2 and the NMOS tube Q9 are not conducted, the energy consumption of the load can only come from the electric energy stored in the capacitor C7, and the power supply ripple synchronous with the PWM2 switching frequency can be formed on the first power supply output end OUT+. The other switch bridge circuit is just opposite to the first switch bridge circuit in switching time, when the PMOS tube Q2 and the NMOS tube Q9 are not conducted, the other PMOS tube Q4 and the NMOS tube Q13 are conducted to charge the capacitor C7, so that the charging current of the capacitor C7 is ensured to be continuous (the working principle and parameters of the principle of the second charge pump switch bridge circuit are identical to those of the first charge pump switch bridge circuit, and the description is not repeated here).
Since the negative electrode of the capacitor C7 is connected to the positive electrode VCC of the power supply of fig. 1, and the voltage across the capacitor C7 is approximately equal to VCC, the voltage between the positive electrode of the capacitor C7 and the negative electrode GND of the power supply is approximately equal to 2 times VCC, and a 2 times voltage conversion function is realized. Of course, if the positive electrode of the capacitor C7 is connected to the negative electrode GND of the power supply, the voltage of the negative electrode of the capacitor C7 is approximately equal to-VCC, so that the conversion from positive voltage to negative voltage is realized. Unlike the common charge pump circuit, the embodiment turns on the corresponding switch units through the two paths of charge pump switch bridge circuits, ensures that the output current is continuous, does not influence the circuits at the input end and the output end by the circuit switch of the embodiment, and is practical for the load with switchability. It should be noted that, in this embodiment, a high-power transistor may be selected, and then the method may be used for voltage conversion in high-power situations.
The energy loss of the circuit in this embodiment is only related to the on-resistances of the 8 power transistors, i.e., the PMOS transistor Q1, the PMOS transistor Q2, the NMOS transistor Q7, the NMOS transistor Q9, the PMOS transistor Q3, the PMOS transistor Q4, the NMOS transistor Q11, and the NMOS transistor Q13, and the energy consumed by other oscillating circuits and driving circuits is constant and weak, and the greater the power, the higher the efficiency.
In another embodiment, the output storage capacitor unit includes a first output storage capacitor and a second output storage capacitor connected in series, a non-series node of the first output storage capacitor is connected to the first power output end, a non-series node of the second output storage capacitor is connected to the second power output end, and a series node of the first output storage capacitor and the second output storage capacitor is connected to the first power input end. The two ends of the first sub output storage capacitor are connected with a third sub output storage capacitor in parallel, the two ends of the second sub output storage capacitor are connected with a fourth sub output storage capacitor in parallel, as shown in fig. 3, the first sub output storage capacitor is a capacitor C71, the second sub output storage capacitor is a capacitor C8, the third sub output storage capacitor is a capacitor C11, and the fourth sub output storage capacitor is a capacitor C12.
The invention is characterized in that the invention adopts the switch capacitance boosting to greatly improve the conversion efficiency mainly through the matching of a first charge pump switch bridge circuit, a second charge pump switch bridge circuit, a first signal output circuit with 50 percent of duty ratio and opposite phase and a second signal output circuit, and particularly, as the two switches with 50 percent of duty ratio and opposite polarity charge an output storage capacitance unit in turn, the output storage capacitance unit is continuously output in a linear state, the influence of the switching frequency is avoided, and the follow-up earphone end can use the conventional switch type step-down charging circuit to greatly improve the total conversion efficiency;
and a plurality of switching tubes can select a high-power switching tube according to the requirement, and then the situation that the voltage output is 2 times or the single power supply is changed into the double power supply in any occasion can be realized under the condition that the power supply current is enough.
Claims (8)
1. A Bluetooth headset charging box boost circuit, its characterized in that: the circuit comprises a first power input end, a second power input end, a first power output end, a second power output end, a first charge pump switch bridge circuit, a second charge pump switch bridge circuit, an output storage capacitor unit, a first signal output circuit and a second signal output circuit, wherein the first signal output circuit and the second signal output circuit have 50% duty ratio and opposite phases;
the first charge pump switch bridge circuit and the second charge pump switch bridge circuit comprise a first charge temporary storage capacitor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit for driving the first switch unit, a sixth switch unit for driving the second switch unit and a photoelectric coupler for driving the fourth switch unit;
the first switch unit and the second switch unit are connected in series, a non-series node of the first switch unit is connected with the first power input end, and a non-series node of the second switch unit is connected with the first power output end; the two ends of the output storage capacitor unit are respectively connected with a first power supply output end and a second power supply output end, and the second power supply output end is connected with a sixth switch unit;
the third switch unit and the fourth switch unit are connected in series, a non-series node of the third switch unit is connected with the second power input end, a non-series node of the fourth switch unit is connected with the first power input end, and a series node of the first switch unit and the second switch unit is connected with a series node of the third switch unit and the fourth switch unit through a first charge temporary capacitor; the two ends of the first charge temporary storage capacitor are connected with a second charge temporary storage capacitor in parallel;
the first signal output circuit is respectively connected with a third switch unit of the first charge pump switch bridge circuit, a fifth switch unit of the first charge pump switch bridge circuit, a sixth switch unit of the second charge pump switch bridge circuit and a photoelectric coupler of the second charge pump switch bridge circuit;
the second signal output circuit is respectively connected with a sixth switch unit of the first charge pump switch bridge circuit, a photoelectric coupler of the first charge pump switch bridge circuit, a third switch unit of the second charge pump switch bridge circuit and a fifth switch unit of the second charge pump switch bridge circuit;
the photoelectric coupler comprises a light emitting diode and a phototriode;
the collector of the phototriode is connected with the first switch unit, the emitter of the phototriode is connected with the fourth switch unit, the anode of the light emitting diode of the first charge pump switch bridge circuit is connected with the second signal output circuit through the fourth resistor, and the anode of the light emitting diode of the second charge pump switch bridge circuit is connected with the first signal output circuit through the fourth resistor.
2. The bluetooth headset charging box boost circuit of claim 1, wherein: the first switch unit comprises a first switch tube and a first resistor;
the first end of the first switching tube is connected with a first power input end, the second end of the first switching tube is connected with a second switching unit and a first charge temporary storage capacitor, the control end of the first switching tube is connected with the first end of the first switching tube through a first resistor, and the control end of the first switching tube is also connected with a fifth switching unit;
the first switch unit of the first charge pump switch bridge circuit further comprises a power supply filter capacitor, and two ends of the power supply filter capacitor are respectively connected with the first power supply input end and the second power supply input end.
3. The bluetooth headset charging box boost circuit of claim 1, wherein: the second switch unit comprises a second switch tube and a second resistor;
the first end of the second switching tube is connected with the first switching unit and the first charge temporary storage capacitor, the second end of the second switching tube is connected with the first power output end, the control end of the second switching tube is connected with the first end of the second switching tube through the second resistor, and the control end of the second switching tube is also connected with the sixth switching unit.
4. The bluetooth headset charging box boost circuit of claim 1, wherein: the third switching unit comprises a third switching tube, a first end of the third switching tube is connected with a second power input end, a second end of the third switching tube is connected with a fourth switching unit and a first charge temporary storage capacitor, and the first signal output circuit is connected with a control end of the third switching tube.
5. The bluetooth headset charging box boost circuit of claim 1, wherein: the fourth switching unit comprises a fourth switching tube and a third resistor;
the first end of the fourth switching tube is connected with the third switching unit and the first charge temporary storage capacitor, the second end of the fourth switching tube is connected with the first power input end, the control end of the fourth switching tube is connected with the photoelectric coupler, and the control end of the fourth switching tube is also connected with the first end of the fourth switching tube through the third resistor.
6. The bluetooth headset charging box boost circuit of claim 1, wherein: the fifth switching unit comprises a fifth switching tube, a first end of the fifth switching tube is connected with the first power input end and grounded, and a second end of the fifth switching tube is connected with the first switching unit;
the control end of the fifth switching tube of the first charge pump switching bridge circuit is connected with the first signal output circuit, and the control end of the fifth switching tube of the second charge pump switching bridge circuit is connected with the second signal output circuit.
7. The bluetooth headset charging box boost circuit of claim 1, wherein: the sixth switching unit comprises a sixth switching tube, a first end of the sixth switching tube is connected with the second power supply output end and grounded, and a second end of the sixth switching tube is connected with the second switching unit;
the control end of a sixth switching tube of the first charge pump switching bridge circuit is connected with the second signal output circuit, and the control end of the sixth switching tube of the second charge pump switching bridge circuit is connected with the first signal output circuit.
8. The bluetooth headset charging box boost circuit of claim 1, wherein: the output storage capacitor unit comprises a first sub-output storage capacitor and a second sub-output storage capacitor which are connected in series, wherein a non-series node of the first sub-output storage capacitor is connected with a first power supply output end, a non-series node of the second sub-output storage capacitor is connected with a second power supply output end, and a series node of the first sub-output storage capacitor and the second sub-output storage capacitor is connected with a first power supply input end.
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