CN113823621A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113823621A CN113823621A CN202010567174.1A CN202010567174A CN113823621A CN 113823621 A CN113823621 A CN 113823621A CN 202010567174 A CN202010567174 A CN 202010567174A CN 113823621 A CN113823621 A CN 113823621A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate; a plurality of first electrode layers and second electrode layers on the substrate; a first interconnect layer and a second interconnect layer on the substrate; and the first conductive plugs and the second conductive plugs are positioned on the substrate, each first conductive plug is connected with the first interconnection layer or the second interconnection layer, and each second conductive plug is connected with the first electrode layer or the second electrode layer. The first conductive plug is connected with the first interconnection layer or the second interconnection layer, and the second conductive plug is connected with the first electrode layer or the second electrode layer, so that the number of the whole conductive plugs is increased, the contact resistance among the first interconnection layer, the second interconnection layer, the first electrode layer and the second electrode layer and other device structures is reduced, and the quality factor of the capacitor is improved; in addition, because the second conductive plug is connected with the first electrode layer or the second electrode layer, additional occupied space is not needed, and the integration level of the finally formed semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid increase of the integration level of various functional circuits and the need for miniaturization of functional modules and components, the integrated passive technology becomes a solution to replace discrete passive devices to achieve miniaturization of the devices. In various typical circuits, 80% of the components are passive devices, which occupy nearly 50% of the area on the printed circuit board, and the capacitors are the most common and most distributed components on the substrate, making the integration technology of the capacitors a key technology for integrating the passive technology.
Two types of capacitors commonly used in current integrated circuit design are MIM (metal insulator metal) capacitors and MOM (metal oxide metal) capacitors. The MIM capacitor is a parallel plate capacitor, and has the advantages that the capacitance value of the capacitor can be changed by changing the thickness of a dielectric layer (generally, a silicon nitride layer) between two parallel plates, the capacitance density (capacitance value per unit area) of the current MIM capacitor can be maximally 2fF/μm2, however, compared with the MOM capacitor, in the process of manufacturing the MIM capacitor, a mask (such as mask used in photolithography of an upper plate of the capacitor) is inevitably added, and a photolithography and etching process is added at the same time, which inevitably increases the process cost.
The MOM capacitor obtains a plurality of conductive electrode wires which are parallel to each other by photoetching and etching metal on the same metal layer, namely the metal on the same layer is arranged in a COMB shape (namely a COMB structure), the conductive electrode wires are COMB-tooth parts, a dielectric medium is arranged between the conductive electrode wires on the same layer, and a combined layer which is formed by the conductive electrode wires which are arranged on the same layer in the COMB shape and the dielectric medium between the conductive electrode wires is called as a metallization layer. On the same metallization layer, two adjacent conductive electrode lines and the dielectric medium between the two adjacent conductive electrode lines form a capacitance structure to generate capacitance, and the total capacitance value of the MOM capacitor is generated by connecting the capacitances on the multiple metallization layers in parallel, that is, the capacitance values on the multiple metallization layers are added to obtain the capacitance value of the MOM capacitor.
However, the performance of the MOM capacitor in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the finally formed semiconductor structure.
To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate; the first electrode layers and the second electrode layers are positioned on the substrate and arranged in parallel along a first direction, and the second electrode layers are positioned between the adjacent first electrode layers; a first interconnect layer and a second interconnect layer on the substrate, the first interconnect layer connecting a number of the first electrode layers and the second interconnect layer connecting a number of the second electrode layers; a plurality of first conductive plugs and a plurality of second conductive plugs on the substrate, each of the first conductive plugs being connected to the first interconnect layer or the second interconnect layer, each of the second conductive plugs being connected to the first electrode layer or the second electrode layer.
Optionally, the width of the first electrode layer along the second direction is 20nm to 500 nm; the width of the second electrode layer along a second direction is 20 nm-500 nm, and the first direction is perpendicular to the second direction.
Optionally, a distance between the first electrode layer and the second electrode layer is 20nm to 200nm, and the distance direction is along the first direction.
Optionally, the number of the first conductive plugs is 2-20; the number of the second conductive plugs is 2-10.
Optionally, the method further includes: a first dielectric layer on the substrate, the first electrode layer, the second electrode layer, the first interconnect layer, and the second interconnect layer being within the first dielectric layer.
Optionally, the method further includes: and the first conductive plug and the second conductive plug are positioned in the interlayer dielectric layer.
Optionally, the method further includes: a first device layer on the substrate, the first device layer being connected to the first and second conductive plugs.
Optionally, each of the first conductive plugs is located on a top surface of the first interconnect layer or the second interconnect layer, and each of the second conductive plugs is located on a top surface of the first electrode layer or the second electrode layer; the first device layer is located on top surfaces of the first and second conductive plugs.
Optionally, the first conductive plug and the second conductive plug are located on the top surface of the first device layer; the first interconnection layer or the second interconnection layer is positioned on the top surface of each first conductive plug; the first electrode layer or the second electrode layer is located on the top surface of each second conductive plug.
Optionally, the first device layer includes: a plurality of third electrode layers and a plurality of fourth electrode layers which are arranged in parallel along the first direction, wherein the fourth electrode layers are positioned between the adjacent third electrode layers; a third interconnect layer connecting a number of the third electrode layers and a fourth interconnect layer connecting a number of the fourth electrode layers; the first conductive plug is connected to the third interconnect layer or the fourth interconnect layer, and the second conductive plug is connected to the third electrode layer or the fourth electrode layer.
Optionally, the first device layer further includes: a second dielectric layer, the third electrode layer, the fourth electrode layer, the third interconnect layer, and the fourth interconnect layer being located within the second dielectric layer.
Optionally, the substrate includes: the device comprises a substrate and a second device layer positioned on the substrate.
Correspondingly, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a plurality of first electrode layers and a plurality of second electrode layers which are arranged in parallel along a first direction on the substrate, wherein the second electrode layers are positioned between the adjacent first electrode layers; forming a first interconnection layer and a second interconnection layer on the substrate, wherein the first interconnection layer is connected with a plurality of the first electrode layers, and the second interconnection layer is connected with a plurality of the second electrode layers; forming a plurality of first conductive plugs and a plurality of second conductive plugs on the substrate, wherein each first conductive plug is connected with the first interconnection layer or the second interconnection layer, and each second conductive plug is connected with the first electrode layer or the second electrode layer.
Optionally, the width of the first electrode layer along the second direction is 20nm to 500 nm; the width of the second electrode layer along a second direction is 30 nm-800 nm, and the first direction is perpendicular to the second direction.
Optionally, a distance between the first electrode layer and the second electrode layer is 20nm to 200nm, and the distance direction is along the first direction.
Optionally, the number of the first conductive plugs is 2-20; the number of the second conductive plugs is 2-10.
Optionally, the method further includes: and forming a first dielectric layer on the substrate, wherein the first electrode layer, the second electrode layer, the first interconnection layer and the second interconnection layer are positioned in the first dielectric layer.
Optionally, the method further includes: and forming an interlayer dielectric layer on the substrate, wherein the first conductive plug and the second conductive plug are positioned in the interlayer dielectric layer.
Optionally, the method further includes: and forming a first device layer on the substrate, wherein the first device layer is connected with the first conductive plug and the second conductive plug.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the structure of the technical scheme of the invention, the first conductive plug is connected with the first interconnection layer or the second interconnection layer, and the second conductive plug is connected with the first electrode layer or the second electrode layer, so that the number of the whole conductive plugs is increased, the contact resistance among the first interconnection layer, the second interconnection layer, the first electrode layer and the second electrode layer and other device structures is reduced, the quality factor of a capacitor is improved, and the performance of a finally formed semiconductor structure is further improved; in addition, because the second conductive plug is connected with the first electrode layer or the second electrode layer, extra space is not required, so that the integration level of the finally formed semiconductor structure is improved, and meanwhile, the additional arrangement of a conductive structure is not required, and the parasitic capacitance is reduced.
Furthermore, the number of the first conductive plugs is 2-20; the number of the second conductive plugs is 2-10. The number of the first conductive plugs and the second conductive plugs in the range can effectively reduce contact resistance, and can also effectively control parasitic capacitance generated among the conductive plugs, so that the performance of a finally formed semiconductor structure is prevented from being influenced excessively.
In the forming method of the technical scheme of the invention, the first conductive plug is connected with the first interconnection layer or the second interconnection layer, and the second conductive plug is connected with the first electrode layer or the second electrode layer, so that the number of the whole conductive plugs is increased, the contact resistance among the first interconnection layer, the second interconnection layer, the first electrode layer and the second electrode layer and other device structures is reduced, the quality factor of a capacitor is improved, and the performance of a finally formed semiconductor structure is further improved; in addition, because the second conductive plug is connected with the first electrode layer or the second electrode layer, extra space is not required, so that the integration level of the finally formed semiconductor structure is improved, and meanwhile, the additional arrangement of a conductive structure is not required, and the parasitic capacitance is reduced.
Furthermore, the number of the first conductive plugs is 2-20; the number of the second conductive plugs is 2-10. The number of the first conductive plugs and the second conductive plugs in the range can effectively reduce contact resistance, and can also effectively control parasitic capacitance generated among the conductive plugs, so that the performance of a finally formed semiconductor structure is prevented from being influenced excessively.
Drawings
FIGS. 1 and 2 are schematic structural diagrams of a semiconductor structure;
FIGS. 3 and 4 are schematic structural views of another semiconductor structure;
fig. 5 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the performance of the MOM capacitor in the prior art still remains to be improved. The following detailed description will be made in conjunction with the accompanying drawings.
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
Referring to fig. 1 and 2, fig. 1 is a top view of a semiconductor structure with a first dielectric layer and an interlayer dielectric layer omitted, and fig. 2 is a cross-sectional view taken along line a-a of fig. 1, including: a substrate 100; a plurality of first electrode layers 101 and a plurality of second electrode layers 102 located on the substrate 100 and arranged in parallel along a first direction X, wherein the second electrode layers 102 are located between adjacent first electrode layers 101; a first interconnection layer 103 and a second interconnection layer 104 on the substrate 100, wherein the first interconnection layer 103 is connected with a plurality of the first electrode layers 101, and the second interconnection layer 104 is connected with a plurality of the second electrode layers 102; a plurality of first conductive plugs 105 located on the substrate 100, the first conductive plugs 105 being connected to the first interconnect layer 103 or the second interconnect layer 104.
In the above embodiment, the number of the first conductive plugs 105 is limited, which results in a large resistance of the contact between the first interconnection layer 103, the second interconnection layer 104, the first electrode layer 101, and the second electrode layer 102 and other device structures. Since the quality factor Q of the finally formed MOM capacitor is inversely proportional to the contact resistance R, when the contact resistance is large, the quality factor of the finally formed MOM capacitor is reduced, and the performance of the finally formed semiconductor structure is affected.
In order to solve the above problems, a semiconductor structure is also provided in the prior art, which will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3 and 4, fig. 3 is a top view of a semiconductor structure with a first dielectric layer and an interlayer dielectric layer omitted, and fig. 4 is a cross-sectional view taken along line B-B of fig. 3, including: a substrate 200; a plurality of first electrode layers 201 and a plurality of second electrode layers 202 which are located on the substrate 200 and arranged in parallel along a first direction X, wherein the second electrode layers 202 are located between adjacent first electrode layers 201; a first interconnection layer 203 and a second interconnection layer 204 located on the substrate 200, the first interconnection layer 203 connecting a plurality of the first electrode layers 201, the second interconnection layer 204 connecting a plurality of the second electrode layers 202; a third interconnect layer 205 and a fourth interconnect layer 206 on the substrate 200, the third interconnect layer 205 being connected to the first interconnect layer 203, the fourth interconnect layer 206 being connected to the second interconnect layer 204; a plurality of first conductive plugs 207 and second conductive plugs 208 located on the substrate 200, the first conductive plugs 207 being connected to the first interconnect layer 203 or the second interconnect layer 204, and the second conductive plugs 208 being connected to the third interconnect layer 205 or the fourth interconnect layer 206.
In the above embodiment, the second conductive plug 208, the third interconnect layer 205, and the fourth interconnect layer 206 are added to reduce the contact resistance between the first interconnect layer 203, the second interconnect layer 204, the third interconnect layer 205, the fourth interconnect layer 206, the first electrode layer 201, and the second electrode layer 202 and other device structures, but the integration level of the finally formed semiconductor structure is reduced because the added third interconnect layer 205 and the added fourth interconnect layer 206 require an additional space-occupying structure.
On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein the first conductive plug is connected with the first interconnection layer or the second interconnection layer, and the second conductive plug is connected with the first electrode layer or the second electrode layer, so that the number of the whole conductive plugs is increased, the contact resistance among the first interconnection layer, the second interconnection layer, the first electrode layer and the second electrode layer and other device structures is reduced, the quality factor of a capacitor is improved, and the performance of the finally formed semiconductor structure is further improved; in addition, because the second conductive plug is connected with the first electrode layer or the second electrode layer, extra space is not required, so that the integration level of the finally formed semiconductor structure is improved, and meanwhile, the additional arrangement of a conductive structure is not required, and the parasitic capacitance is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 5, a substrate is provided.
In this embodiment, the substrate includes: a substrate 200, and a second device layer 201 on the substrate 200.
The base 200 is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, a glass substrate, or a III-V compound substrate such as gallium nitride or gallium arsenide, or the like. In this embodiment, the base 200 is a silicon substrate.
The second device layer 201 includes: a semiconductor device forming a surface of the substrate 200, an electrical interconnection structure (not shown) for electrically connecting the semiconductor device, and an insulating layer for electrically isolating the semiconductor device and the electrical interconnection structure. The semiconductor device includes a CMOS device including a transistor, a memory, a capacitor, a resistor, or the like. The material of the electrical interconnection structure is metal, and the metal comprises one or more of copper, tungsten, aluminum, silver, titanium, tantalum, titanium nitride and tantalum nitride; the insulating layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material or ultralow-K dielectric material.
Forming a plurality of first electrode layers and a plurality of second electrode layers which are arranged in parallel along a first direction on the substrate, wherein the second electrode layers are positioned between the adjacent first electrode layers; forming a first interconnection layer and a second interconnection layer on the substrate, wherein the first interconnection layer is connected with a plurality of the first electrode layers, and the second interconnection layer is connected with a plurality of the second electrode layers; and forming a first dielectric layer on the substrate, wherein the first electrode layer, the second electrode layer, the first interconnection layer and the second interconnection layer are positioned in the first dielectric layer. Please refer to fig. 6 to 8 for a specific forming process.
Referring to fig. 6 and 7, fig. 6 is a top view of a semiconductor structure, and fig. 7 is a cross-sectional view taken along line C-C of fig. 6; forming a first conductive film (not shown) on the surface of the substrate; forming a first patterned layer (not shown) on the first conductive film, the first patterned layer exposing a portion of the first conductive film; and etching the first conductive film by using the first patterning layer as a mask until the top surface of the substrate is exposed, thereby forming a plurality of first electrode layers 202 and a plurality of second electrode layers 203, and a first interconnection layer 204 and a second interconnection layer 205 which are arranged in parallel along a first direction.
In this embodiment, the capacitor structure formed by the first electrode layer 202, the second electrode layer 203, the first interconnection layer 204 and the second interconnection layer 205 is in a parallel state of a plurality of capacitors, so that the capacity of the final capacitor structure is increased, thereby meeting the requirement of electrical structure.
In this embodiment, the number of the first electrode layers 202 and the second electrode layers 203 is 2 respectively. In other embodiments, the number of the first electrode layer and the second electrode layer may be more than 2.
The forming process of the first conductive film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, a physical vapor deposition process is used for forming the first conductive film.
The first conductive film is made of one or more of aluminum, titanium, tantalum, titanium nitride and tantalum nitride; in this embodiment, aluminum is used as a material of the first conductive film.
The widths of the first electrode layer 202 and the second electrode layer 203 determine the area of the capacitor formed by the first electrode layer 202 and the second electrode layer 203, and the larger the area, the larger the capacitance of the capacitor. In this embodiment, the width of the first electrode layer 202 along the second direction Y is 20nm to 500 nm; the width of the second electrode layer 203 along a second direction Y is 30nm to 800nm, and the first direction X is perpendicular to the second direction Y.
The capacitance value is also related to the distance between the first electrode layer 202 and the second electrode layer 203, the larger the distance, the larger the capacitance of the capacitor. In this embodiment, the distance between the first electrode layer 202 and the second electrode layer 203 is 20nm to 200nm, and the distance direction is along the first direction X.
Referring to fig. 8, fig. 8 is the same as the view direction of fig. 7, after forming the first electrode layer 202, the second electrode layer 203, the first interconnection layer 204 and the second interconnection layer 205, an initial first dielectric layer (not shown) is formed on the substrate, the initial first electrode layer covers the first electrode layer 202, the second electrode layer 203, the first interconnection layer 204 and the second interconnection layer 205; the initial first dielectric layer is planarized until the top surfaces of the first electrode layer 202, the second electrode layer 203, the first interconnect layer 204, and the second interconnect layer 205 are exposed, forming the first dielectric layer 206.
The first dielectric layer 206 serves as a dielectric material of a capacitor between the first electrode layer 202 and the second electrode layer 203, and a capacitor structure is formed by the first dielectric layer 206, the first electrode layer 202 and the second electrode layer 203. In the present embodiment, the material of the first dielectric layer 206 is one or more of silicon nitride, silicon oxide, and silicon oxynitride. In other embodiments, the material of the first dielectric layer can also be a high-K dielectric material including HfO2、ZrO2、HfSiNO、Al2O3Or SbO.
The forming process of the initial first dielectric layer is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the formation process of the initial first dielectric layer adopts a chemical vapor deposition process.
The process of planarizing the initial first dielectric layer includes: a chemical mechanical polishing process, a wet etching process or a dry etching process; in this embodiment, the process of planarizing the initial first dielectric layer adopts a chemical mechanical polishing process.
In other embodiments, the first dielectric layer may be formed on the substrate first; forming a plurality of openings in the first dielectric layer after forming the first dielectric layer; and respectively forming the first electrode layer, the second electrode layer, the first interconnection layer and the second interconnection layer in the openings.
After the first electrode layer 202, the second electrode layer 203, the first interconnect layer 204, the second interconnect layer 205, and the first dielectric layer 206 are formed, the method further includes: forming a plurality of first conductive plugs and a plurality of second conductive plugs on the substrate, each of the first conductive plugs being connected to the first interconnection layer 204 or the second interconnection layer 205, and each of the second conductive plugs being connected to the first electrode layer 202 or the second electrode layer 203; and forming an interlayer dielectric layer on the substrate, wherein the first conductive plug and the second conductive plug are positioned in the interlayer dielectric layer. Please refer to fig. 9 to fig. 11 for a specific forming process.
Referring to fig. 9, the interlayer dielectric layer 207 is formed on the first electrode layer 202, the second electrode layer 203, the first interconnection layer 204, the second interconnection layer 205 and the first dielectric layer 206; forming a plurality of first plug openings 208 and a plurality of second plug openings 209 in the interlayer dielectric layer 207, wherein each first plug opening 208 exposes a top surface of the first interconnection layer 204 or the second interconnection layer 205, and each second plug opening 209 exposes a top surface of the first electrode layer 202 or the second electrode layer 203.
In this embodiment, the material of the interlayer dielectric layer 207 is one or more of silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material, or an ultra-low-K dielectric material. In this embodiment, the material of the interlayer dielectric layer 207 is silicon oxide.
In this embodiment, the method for forming the interlayer dielectric layer 207 includes: forming an initial interlayer dielectric layer (not shown) on the first electrode layer 202, the second electrode layer 203, the first interconnect layer 204, the second interconnect layer 205, and the first dielectric layer 206; and carrying out planarization treatment on the initial interlayer dielectric layer to form the interlayer dielectric layer 207.
In this embodiment, the forming process of the initial interlayer dielectric layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the formation process of the initial interlayer dielectric layer adopts a chemical vapor deposition process.
In this embodiment, the planarization process is a chemical mechanical polishing process.
In this embodiment, the method for forming the first plug openings 208 and the second plug openings 209 in the interlayer dielectric layer 207 includes: forming a second patterned layer (not shown) on the interlayer dielectric layer 207, wherein the second patterned layer exposes a portion of the interlayer dielectric layer 207; and etching the interlayer dielectric layer 207 by using the second patterning layer as a mask until the top surfaces of the first electrode layer 202, the second electrode layer 203, the first interconnection layer 204 and the second interconnection layer 205 are exposed, so as to form a plurality of first plug openings 208 and a plurality of second plug openings 209.
Referring to fig. 10 and 11, fig. 10 is a top view of a semiconductor structure with the first dielectric layer and the interlayer dielectric layer omitted, and fig. 11 is a cross-sectional view taken along line D-D of fig. 10; the first conductive plug 210 is formed in the first plug opening 208, and the second conductive plug 211 is formed in the second plug opening 209.
By connecting the first conductive plug 210 with the first interconnection layer 204 or the second interconnection layer 205, and connecting the second conductive plug 211 with the first electrode layer 202 or the second electrode layer 203, the number of the whole conductive plugs is increased, the contact resistance between the first interconnection layer 204, the second interconnection layer 205, the first electrode layer 202, the second electrode layer 203 and other device structures is reduced, the quality factor of the capacitor is improved, and the performance of the finally formed semiconductor structure is further improved; in addition, since the second conductive plug 211 is connected to the first electrode layer 202 or the second electrode layer 203, additional space is not required, so that the integration of the finally formed semiconductor structure is improved, and meanwhile, an additional conductive structure is not required, so that the parasitic capacitance is reduced.
In this embodiment, the number of the first conductive plugs 210 is 2 to 20; the number of the second conductive plugs 211 is 2-10. The number of the first conductive plugs 210 and the second conductive plugs 211 in the range can effectively reduce contact resistance, and can also effectively control parasitic capacitance generated between the conductive plugs, thereby avoiding excessive influence on the performance of a finally formed semiconductor structure.
Referring to fig. 12, after the first conductive plug 210 and the second conductive plug 211 are formed, a first device layer is formed on the substrate, and the first device layer is connected to the first conductive plug 210 and the second conductive plug 211.
In this embodiment, each of the first conductive plugs 210 is located on the top surface of the first interconnect layer 204 or the second interconnect layer 205, and each of the second conductive plugs 211 is located on the top surface of the first electrode layer 202 or the second electrode layer 203; the first device layer is located on top surfaces of the first conductive plugs 210 and the second conductive plugs 211.
In other embodiments, the first and second conductive plugs may also be located at the first device layer top surface; the first interconnection layer or the second interconnection layer is positioned on the top surface of each first conductive plug; the first electrode layer or the second electrode layer is located on the top surface of each second conductive plug.
In this embodiment, the first device layer includes: a plurality of third electrode layers 212 and a plurality of fourth electrode layers 213 arranged in parallel along the first direction X, wherein the fourth electrode layers 213 are located between adjacent third electrode layers 212; a third interconnect layer 214 and a fourth interconnect layer 215, said third interconnect layer 214 connecting a number of said third electrode layers 212, said fourth interconnect layer 215 connecting a number of said fourth electrode layers 213; the first conductive plug 210 is connected to the third interconnect layer 214 or the fourth interconnect layer 215, and the second conductive plug 211 is connected to the third electrode layer 212 or the fourth electrode layer 213.
In this embodiment, the first device layer further includes: a second dielectric layer 216, wherein the third electrode layer 212, the fourth electrode layer 213, the third interconnect layer 214, and the fourth interconnect layer 215 are disposed within the second dielectric layer 216.
In this embodiment, the formation process of the third electrode layer 212, the fourth electrode layer 213, the third interconnect layer 214, the fourth interconnect layer 215 and the second dielectric layer 216 in the first device layer is the same as the formation process of the first electrode layer 202, the second electrode layer 203, the first interconnect layer 204, the second interconnect layer 205 and the first dielectric layer 206, which can be specifically described with reference to fig. 6 to 8 and related descriptions.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 12, including: a substrate; a plurality of first electrode layers 202 and a plurality of second electrode layers 203 which are located on the substrate and arranged in parallel along a first direction X, wherein the second electrode layers 203 are located between adjacent first electrode layers 202; a first interconnection layer 204 and a second interconnection layer 205 located on the substrate, the first interconnection layer 204 connecting a number of the first electrode layers 202, the second interconnection layer 205 connecting a number of the second electrode layers 203; a plurality of first conductive plugs 210 and a plurality of second conductive plugs 211 located on the substrate, each of the first conductive plugs 210 being connected to the first interconnect layer 204 or the second interconnect layer 205, and each of the second conductive plugs 211 being connected to the first electrode layer 202 or the second electrode layer 203.
By connecting the first conductive plug 210 with the first interconnection layer 204 or the second interconnection layer 205, and connecting the second conductive plug 211 with the first electrode layer 202 or the second electrode layer 203, the number of the whole conductive plugs is increased, the contact resistance between the first interconnection layer 204, the second interconnection layer 205, the first electrode layer 202, the second electrode layer 203 and other device structures is reduced, the quality factor of the capacitor is improved, and the performance of the finally formed semiconductor structure is further improved; in addition, since the second conductive plug 211 is connected to the first electrode layer 202 or the second electrode layer 203, additional space is not required, so that the integration of the finally formed semiconductor structure is improved, and meanwhile, an additional conductive structure is not required, so that the parasitic capacitance is reduced.
In this embodiment, the width of the first electrode layer 202 along the second direction Y is 20nm to 500 nm; the width of the second electrode layer 203 along a second direction Y is 30nm to 800nm, and the first direction X is perpendicular to the second direction Y.
In this embodiment, the distance between the first electrode layer 202 and the second electrode layer 203 is 20nm to 200nm, and the distance direction is along the first direction X.
In this embodiment, the number of the first conductive plugs 210 is 2 to 20; the number of the second conductive plugs 211 is 2-10. The number of the first conductive plugs 210 and the second conductive plugs 211 in the range can effectively reduce contact resistance, and can also effectively control parasitic capacitance generated between the conductive plugs, thereby avoiding excessive influence on the performance of a finally formed semiconductor structure.
In this embodiment, the method further includes: a first dielectric layer 206 on the substrate, the first electrode layer 202, the second electrode layer 203, the first interconnect layer 204, and the second interconnect layer 205 being within the first dielectric layer 206.
In this embodiment, the method further includes: an interlayer dielectric layer 207 on the substrate, the first conductive plug 210 and the second conductive plug 211 being located within the interlayer dielectric layer 207.
In this embodiment, the method further includes: a first device layer on the substrate, the first device layer being connected to the first conductive plug 210 and the second conductive plug 211.
In this embodiment, each of the first conductive plugs 210 is located on the top surface of the first interconnect layer 204 or the second interconnect layer 205, and each of the second conductive plugs 211 is located on the top surface of the first electrode layer 202 or the second electrode layer 203; the first device layer is located on top surfaces of the first conductive plugs 210 and the second conductive plugs 211.
In other embodiments, the first and second conductive plugs may also be located at the first device layer top surface; the first interconnection layer or the second interconnection layer is positioned on the top surface of each first conductive plug; the first electrode layer or the second electrode layer is located on the top surface of each second conductive plug.
In this embodiment, the first device layer includes: a plurality of third electrode layers 212 and a plurality of fourth electrode layers 213 arranged in parallel along the first direction X, wherein the fourth electrode layers 213 are located between adjacent third electrode layers 212; a third interconnect layer 214 and a fourth interconnect layer 215, said third interconnect layer 214 connecting a number of said third electrode layers 212, said fourth interconnect layer 215 connecting a number of said fourth electrode layers 213; the first conductive plug 210 is connected to the third interconnect layer 212 or the fourth interconnect layer 213, and the second conductive plug 211 is connected to the third electrode layer 212 or the fourth electrode layer 213.
In this embodiment, the first device layer further includes: a second dielectric layer 216, wherein the third electrode layer 212, the fourth electrode layer 213, the third interconnect layer 214, and the fourth interconnect layer 215 are disposed within the second dielectric layer 216.
In this embodiment, the substrate includes: a substrate 200, and a second device layer 201 on the substrate 200.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
a substrate;
the first electrode layers and the second electrode layers are positioned on the substrate and arranged in parallel along a first direction, and the second electrode layers are positioned between the adjacent first electrode layers;
a first interconnect layer and a second interconnect layer on the substrate, the first interconnect layer connecting a number of the first electrode layers and the second interconnect layer connecting a number of the second electrode layers;
a plurality of first conductive plugs and a plurality of second conductive plugs on the substrate, each of the first conductive plugs being connected to the first interconnect layer or the second interconnect layer, each of the second conductive plugs being connected to the first electrode layer or the second electrode layer.
2. The semiconductor structure according to claim 1, wherein a width of the first electrode layer in the second direction is 20nm to 500 nm; the width of the second electrode layer along a second direction is 30 nm-800 nm, and the first direction is perpendicular to the second direction.
3. The semiconductor structure according to claim 1, wherein a pitch between the first electrode layer and the second electrode layer is 20nm to 200nm, and a direction of the pitch is along the first direction.
4. The semiconductor structure of claim 1, wherein the number of the first conductive plugs is 2 to 20; the number of the second conductive plugs is 2-10.
5. The semiconductor structure of claim 1, further comprising: a first dielectric layer on the substrate, the first electrode layer, the second electrode layer, the first interconnect layer, and the second interconnect layer being within the first dielectric layer.
6. The semiconductor structure of claim 1, further comprising: and the first conductive plug and the second conductive plug are positioned in the interlayer dielectric layer.
7. The semiconductor structure of claim 1, further comprising: a first device layer on the substrate, the first device layer being connected to the first and second conductive plugs.
8. The semiconductor structure of claim 7, wherein each of the first conductive plugs is located at a top surface of the first interconnect layer or the second interconnect layer, and each of the second conductive plugs is located at a top surface of the first electrode layer or the second electrode layer; the first device layer is located on top surfaces of the first and second conductive plugs.
9. The semiconductor structure of claim 7, wherein the first and second conductive plugs are located at the first device layer top surface; the first interconnection layer or the second interconnection layer is positioned on the top surface of each first conductive plug; the first electrode layer or the second electrode layer is located on the top surface of each second conductive plug.
10. The semiconductor structure of claim 7, wherein the first device layer comprises: a plurality of third electrode layers and a plurality of fourth electrode layers which are arranged in parallel along the first direction, wherein the fourth electrode layers are positioned between the adjacent third electrode layers; a third interconnect layer connecting a number of the third electrode layers and a fourth interconnect layer connecting a number of the fourth electrode layers; the first conductive plug is connected to the third interconnect layer or the fourth interconnect layer, and the second conductive plug is connected to the third electrode layer or the fourth electrode layer.
11. The semiconductor structure of claim 10, wherein the first device layer further comprises: a second dielectric layer, the third electrode layer, the fourth electrode layer, the third interconnect layer, and the fourth interconnect layer being located within the second dielectric layer.
12. The semiconductor structure of claim 1, wherein the substrate comprises: the device comprises a substrate and a second device layer positioned on the substrate.
13. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of first electrode layers and a plurality of second electrode layers which are arranged in parallel along a first direction on the substrate, wherein the second electrode layers are positioned between the adjacent first electrode layers;
forming a first interconnection layer and a second interconnection layer on the substrate, wherein the first interconnection layer is connected with a plurality of the first electrode layers, and the second interconnection layer is connected with a plurality of the second electrode layers;
forming a plurality of first conductive plugs and a plurality of second conductive plugs on the substrate, wherein each first conductive plug is connected with the first interconnection layer or the second interconnection layer, and each second conductive plug is connected with the first electrode layer or the second electrode layer.
14. The method for forming a semiconductor structure according to claim 13, wherein a width of the first electrode layer in the second direction is 20nm to 500 nm; the width of the second electrode layer along a second direction is 30 nm-800 nm, and the first direction is perpendicular to the second direction.
15. The method of forming a semiconductor structure according to claim 13, wherein a pitch between the first electrode layer and the second electrode layer is 20nm to 200nm, and the pitch direction is along the first direction.
16. The method for forming a semiconductor structure according to claim 13, wherein the number of the first conductive plugs is 2 to 20; the number of the second conductive plugs is 2-10.
17. The method of forming a semiconductor structure of claim 13, further comprising: and forming a first dielectric layer on the substrate, wherein the first electrode layer, the second electrode layer, the first interconnection layer and the second interconnection layer are positioned in the first dielectric layer.
18. The method of forming a semiconductor structure of claim 13, further comprising: and forming an interlayer dielectric layer on the substrate, wherein the first conductive plug and the second conductive plug are positioned in the interlayer dielectric layer.
19. The method of forming a semiconductor structure of claim 13, further comprising: and forming a first device layer on the substrate, wherein the first device layer is connected with the first conductive plug and the second conductive plug.
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