CN113808529A - 像素电路及其外部补偿方法 - Google Patents

像素电路及其外部补偿方法 Download PDF

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CN113808529A
CN113808529A CN202111145282.0A CN202111145282A CN113808529A CN 113808529 A CN113808529 A CN 113808529A CN 202111145282 A CN202111145282 A CN 202111145282A CN 113808529 A CN113808529 A CN 113808529A
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potential
time
driving transistor
source electrode
real
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CN113808529B (zh
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窦维
黄泰钧
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to PCT/CN2021/123022 priority patent/WO2023050462A1/zh
Priority to US17/610,715 priority patent/US20240054949A1/en
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开了一种像素电路及其外部补偿方法，该外部补偿方法通过n次迭代侦测驱动晶体管的实时源极电位，以人为可以设定的单次迭代侦测时间来限制每次迭代侦测驱动晶体管的实时源极电位所用的时间，直至驱动晶体管的实时源极电位等于目标源极电位，可以提高驱动晶体管的阈值电压侦测效率。

Description

像素电路及其外部补偿方法
技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及其外部补偿方法。
背景技术
传统像素电路中驱动晶体管的阈值电压(Vth)侦测，通常给定驱动晶体管一个大于Vth的初始栅源电压(Vgs)，然后利用源跟随的方式，保持驱动晶体管的栅极电压不变，抬升驱动晶体管的源极电压至Vgs＝Vth，此时流过驱动晶体管的电流大小趋近于零，在此状态下，采样驱动晶体管的源极电压，进而计算得到Vth，再叠加得到的Vth至显示时的数据电压上，实现对Vth差异的补偿，消除由Vth差异导致的亮度显示不均匀。
但是，随着侦测中Vgs的减小以及侦测线路的寄生电容远大于单个像素电路的存储电容，驱动晶体管的源极电压抬升也越来越慢，如此，驱动晶体管的Vth差异侦测需要很长的时间。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
发明内容
本申请提供一种像素电路及其外部补偿方法，以缓解驱动晶体管的阈值电压侦测效率较低的技术问题。
第一方面，本申请提供一种像素电路的外部补偿方法，其包括：确定像素电路中驱动晶体管的目标源极电位以及单次迭代侦测时间；n次迭代侦测驱动晶体管的实时源极电位，直至驱动晶体管的实时源极电位等于目标源极电位，n为正整数；基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压；根据第n-1次补偿电压对驱动晶体管进行补偿。
在其中一些实施方式中，基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压的步骤包括：基于目标源极电位与第n-1次迭代侦测到的实时源极电位的差值，确定第n-1次类阈值电压；基于初始类阈值电压至第n-1次类阈值电压的累加之和，得到第n-1次补偿电压。
在其中一些实施方式中，若第n次迭代侦测中驱动晶体管的实时源极电位等于目标源极电位，则第n+1次数据信号的电位与第n次数据信号的电位相同。
在其中一些实施方式中，第n+1次及以后的预充电阶段、迭代侦测阶段中数据信号的电位均与第n次数据信号的电位相同。
在其中一些实施方式中，外部补偿方法还包括：确定驱动晶体管的初始栅极电位、驱动晶体管的初始源极电位；配置初始栅极电位与初始源极电位的差值大于驱动晶体管的阈值电压。
在其中一些实施方式中，外部补偿方法还包括：确定驱动晶体管的初始栅极电位、驱动晶体管的初始源极电位；配置目标源极电位与初始源极电位的差值大于零。
在其中一些实施方式中，目标源极电位大于或者等于0V，且小于或者等于16V。
在其中一些实施方式中，单次迭代侦测时间大于或者等于0毫秒，且小于或者等于29毫秒。
在其中一些实施方式中，单次迭代侦测时间大于或者等于0.5毫秒，且小于或者等于20毫秒。
第二方面，本申请提供一种像素电路，其包括驱动晶体管和外部补偿模块，外部补偿模块与驱动晶体管电性连接，用于确定驱动晶体管的初始栅极电位、驱动晶体管的初始源极电位、驱动晶体管的目标源极电位以及单次迭代侦测时间，其中，同一单次迭代侦测时间内，驱动晶体管的栅极电位与数据信号的电位相同；n次迭代侦测驱动晶体管的实时源极电位，直至驱动晶体管的实时源极电位等于目标源极电位，n为正整数；基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压；叠加第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，第n次数据信号为第n次迭代侦测中的数据信号。
本申请提供的像素电路及其外部补偿方法，通过n次迭代侦测驱动晶体管的实时源极电位，以人为可以设定的单次迭代侦测时间来限制每次迭代侦测驱动晶体管的实时源极电位所用的时间，直至驱动晶体管的实时源极电位等于目标源极电位，可以提高驱动晶体管的阈值电压侦测效率；再叠加第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，可以提高驱动晶体管的阈值电压补偿效率，进而提高了像素电路的亮度显示均匀性。
附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的外部补偿方法的流程示意图。
图2为本申请实施例提供的像素电路的电路原理图。
图3为图2所示像素电路的时序示意图。
图4为本申请实施例提供的实时源极电位的电流特性示意图。
图5为本申请实施例提供的实时源极电位随时间变化的示意图。
图6为本申请实施例提供的初次侦测中不同驱动晶体管具有不同的阈值电压示意图。
图7为本申请实施例提供的随着迭代侦测次数的增加不同驱动晶体管具有一致的阈值电压示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1至图7，如图1所示，本实施例提供了一种像素电路的外部补偿方法，其包括以下步骤：
步骤S10：确定像素电路中驱动晶体管的目标源极电位以及单次迭代侦测时间。
步骤S20：n次迭代侦测驱动晶体管的实时源极电位，直至驱动晶体管的实时源极电位等于目标源极电位，n为正整数。
步骤S30：基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压。
步骤S40：根据第n-1次补偿电压对驱动晶体管进行补偿。
可以理解的是，本实施例提供的外部补偿方法，通过n次迭代侦测驱动晶体管的实时源极电位，以人为可以设定的单次迭代侦测时间来限制每次迭代侦测驱动晶体管的实时源极电位所用的时间，直至驱动晶体管的实时源极电位等于目标源极电位，可以提高驱动晶体管的阈值电压侦测效率；再叠加第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，可以提高驱动晶体管的阈值电压补偿效率，进而提高了像素电路的亮度显示均匀性。
如图2所示的像素电路中，驱动晶体管T1的漏极用于接入电源正信号ELVDD，驱动晶体管T1的栅极与存储电容Cst的一端、写入晶体管T2的源极/漏极中的一个电性连接，写入晶体管T2的源极/漏极中的另一个用于接入数据信号DATA，写入晶体管T2的栅极用于接入扫描信号SCAN，驱动晶体管T1的源极与感测晶体管T3的源极/漏极中的一个、存储电容Cst的另一端以及发光器件D1的阳极电性连接，发光器件D1的阴极用于连接电源负信号ELVSS，感测晶体管T3的栅极用于接入感测信号SENSE，感测晶体管T3的源极/漏极中的另一个与感测线SL电性连接，感测线SL与控制开关K1的一端、控制开关K2的一端电性连接，控制开关K1的另一端与模数转换器10的输入端电性连接，模数转换器10的输出端与控制器20的输入端电性连接，控制器20的输出端与数模转换器30的输入端电性连接，数模转换器30的输出端用于输出对应的数据信号DATA，控制开关K1的控制端用于接入采样控制信号SAMP，控制开关K2的另一端用于接入参考信号VREF，控制开关K2的控制端用于接入控制信号SPRE。其中，感测线SL存在寄生电容C1，寄生电容C1的电容量远大于存储电容Cst的电容量。
其中，外部补偿模块可以包括模数转换器10、控制器20以及数模转换器30，外部补偿模块还可以包括控制开关K1和控制开关K2，外部补偿模块可以以集成电路或者芯片的形式呈现，如此可以减小外部补偿模块的面积或者体积，减少其占用空间。
其中，发光器件D1可以但不限于OLED，也可以为Mini-LED，还可以为Micro-LED。
外部补偿模块可以用于确定驱动晶体管的初始栅极电位、驱动晶体管的初始源极电位、驱动晶体管的目标源极电位以及单次迭代侦测时间，其中，同一单次迭代侦测时间内，驱动晶体管的栅极电位与数据信号的电位相同；n次迭代侦测驱动晶体管的实时源极电位，直至驱动晶体管的实时源极电位等于目标源极电位，n为正整数；基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压；叠加第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，第n次数据信号为第n次迭代侦测中的数据信号。
可以理解的是，本实施例提供的外部补偿模块，通过n次迭代侦测驱动晶体管的实时源极电位，以人为可以设定的单次迭代侦测时间来限制每次迭代侦测驱动晶体管的实时源极电位所用的时间，直至驱动晶体管的实时源极电位等于目标源极电位，可以提高驱动晶体管的阈值电压侦测效率；再叠加第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，可以提高驱动晶体管的阈值电压补偿效率，进而提高了像素电路的亮度显示均匀性。
如图3所示，本申请提供的外部补偿方法可以包括多次迭代侦测过程，例如，第一次迭代侦测过程Fb0、第二次迭代侦测过程Fb1至第n次迭代侦测过程Fbn-1，每个迭代侦测过程可以包括以下几个阶段：
Pre-charge(预充阶段)：扫描信号SCAN、感测信号SENSE以及控制信号SPRE均为高电位，写入晶体管T2、感测晶体管T3以及控制开关K2均导通；写入数据信号的电位至驱动晶体管的栅极电位Vg，写入参考信号VREF的电位至驱动晶体管的实时源极电位Vs，其中Vg-Vs>Vth，Vth为驱动晶体管的阈值电压，能够保证驱动晶体管可以导通。
Sensing(侦测阶段)：写入晶体管T2、感测晶体管T3维持打开状态，Vg＝VDATA；控制信号Spre为低电位，控制开关K2断开，此时，感测线SL处于浮空(Floating)状态，流经驱动晶体管T1、感测晶体管T3的发光电流可以充电感测线SL的寄生电容C1，对应地，驱动晶体管的实时源极电位Vs抬升。
Sampling(采样阶段)：当侦测阶段的时间SENSE-TIME达到设定的单次迭代侦测时间t时，采样控制信号SAMP导通控制开关K1，模数转换器10采样驱动晶体管的实时源极电位Vs。
其中，在本申请中，由于单次迭代侦测时间t可以自由设定，因此，单次迭代侦测时间t大于或者等于0毫秒，且小于或者等于29毫秒的情况下，其已经小于常规的30毫秒侦测时间，提高了驱动晶体管T1的阈值电压侦测效率。
具体地，单次迭代侦测时间t也可以大于或者等于0.5毫秒，且小于或者等于20毫秒，可以进一步提高驱动晶体管T1的阈值电压侦测效率。例如，单次迭代侦测时间t可以为0.8毫秒、1毫秒、0.8毫秒、1.2毫秒、1.5毫秒、0.8毫秒、2毫秒、4.5毫秒、6毫秒、8毫秒、10毫秒等等符合范围的自然数毫秒。
如下所示的表1为每次迭代侦测中各电位的变化情况：
n VDATA Vs VTHS △V
Fb0 VDATA0＝Vg0 Vs0 VTHS0＝Vtrg-Vs0 △V0＝VTHS0
Fb1 VDATA1＝VDATA0+△V0 Vs1 VTHS1＝Vtrg-Vs1 △V1＝VTHS0+VTHS1
Fb2 VDATA2＝VDATA1+△V1 Vs2 VTHS2＝Vtrg-Vs2 △V2＝VTHS0+VTHS1+VTHS2
... ... ... ... ...
Fbn VDATAn＝VDATAn-1+△Vn-1 Vsn VTHSn＝Vtrg-Vsn △Vn＝VTHS0+VTHS1+VTHS2+...+VTHSn
其中，n为迭代侦测次数，VDATA为数据信号的电位，Vs为驱动晶体管T1的实时源极电位，VTHS为驱动晶体管T1的类阈值电压，△V为补偿电压，Vtrg为目标源极电位。其中，△Vn为第n次补偿电压，△Vn-1为第n-1次补偿电压。
第一次迭代侦测过程Fb0的侦测阶段中，驱动晶体管T1的第1次栅极电位Vg0为第1次数据信号的电位VDATA0，对应获取到的第1次迭代侦测到的实时源极电位为Vs0。
第二次迭代侦测过程Fb1的侦测阶段中，驱动晶体管T1的第2次栅极电位Vg1为第2次数据信号的电位VDATA1，对应获取到的第2次迭代侦测到的实时源极电位为Vs1。其中，Vs1大于Vs0，VDATA1大于VDATA0。
第三次迭代侦测过程Fb2的侦测阶段中，驱动晶体管T1的第3次栅极电位Vg2为第3次数据信号的电位VDATA2，对应获取到的第3次迭代侦测到的实时源极电位为Vs2。其中，Vs2大于Vs1，VDATA2大于VDATA1。
依次类推，第n次迭代侦测过程Fbn的侦测阶段中，驱动晶体管T1的第n次栅极电位Vgn为第n次数据信号的电位VDATAn，对应获取到的第n次迭代侦测到的实时源极电位为Vsn。
如此反复，直至驱动晶体管T1的实时源极电位Vs抬升至目标源极电位Vtrg，此时，计算得到VTHSn＝0V，继续迭代侦测，驱动晶体管T1的栅极电位Vg不再改变，那么此时VTHS0+VTHS1+VTHS2+...+VTHSn即为△Vn，不同像素电路中驱动晶体管的补偿电压之间的差异即为不同驱动晶体管之间的阈值电压差异，叠加各驱动晶体管对应的补偿电压△Vn或者△Vn-1至对应的数据信号，即可消除不同驱动晶体管之间的阈值电压差异导致的亮度显示不均匀性。
如图4所示的阴影面积可以表征驱动晶体管T1的实时源极电位Vs的抬升大小，随着时间T的增加，流经驱动晶体管T1的电流i的减小，例如，时间t1对应的电流i大于时间t2对应的电流i，时间t2对应的电流i大于时间tn对应的电流i，直至在时间的无限远处，电流i趋近于0，驱动晶体管T1的实时源极电位Vs趋向于稳定。
如图5所示，随着时间T的增加，驱动晶体管T1的实时源极电位Vs0、Vs1以及Vsn逐渐抬高直至达到目标源极电位；在此过程中，驱动晶体管T1的栅极电位Vg1、Vgn也在逐渐增加。
如图6所示，第一次的单次迭代侦测时间SENSE-TIME中，由于各驱动晶体管的阈值电压不一致，导致侦测到的驱动晶体管的实时源极电位也不相同，例如，驱动晶体管TFT1的实时源极电位高于驱动晶体管TFT2的实时源极电位，驱动晶体管TFT2的实时源极电位高于驱动晶体管TFT3的实时源极电位，驱动晶体管TFT3的实时源极电位高于驱动晶体管TFT4的实时源极电位，所以，需要进行一次或者多次的迭代侦测才能够将各驱动晶体管的阈值电压差异侦测完全。
如图7所示，随着迭代侦测的次数增加，各驱动晶体管的实时源极电位逐渐趋向于同一目标源极电位，此时，得到的各补偿电压可以充分体现各驱动晶体管的阈值电压差异，以此补偿电压去补偿对应像素电路接入的数据信号的电位，可以消除不同驱动晶体管之间存在的阈值电压差异，实现显示面板的亮度显示均匀性。
具体地，例如，同一显示面板包括第一子像素和第二子像素，第一子像素包括第一驱动晶体管，第一驱动晶体管的阈值电压为第一阈值电压Vth1，第二子像素包括第二驱动晶体管，第二驱动晶体管的阈值电压为第二阈值电压Vth2。经过多次迭代侦测后，直至第一驱动晶体管的实时源极电位、第二驱动晶体管的实时源极电位均抬升至目标源极电位，得到第一驱动晶体管对应的补偿电压△V1、第二驱动晶体管对应的补偿电压△V2，此时，补偿电压△V1与补偿电压△V2之间的差值即为第一阈值电压Vth1与第二阈值电压Vth2之间的差值。
然后根据如下公式一所示的发光电流公式：
Ids＝μ*W*Cox*(Vgs-Vth)2/2L (一)
其中，Ids为流经驱动晶体管的发光电流，μ为驱动晶体管的迁移率，W为驱动晶体管的沟道宽度，L为驱动晶体管的沟道长度，Cox为介电常数，Vgs为驱动晶体管的栅极-源极电压差，Vth为驱动晶体管的阈值电压，可以得到如下所示的第一驱动晶体管的发光电流Ids1：
Ids1＝μ*W*Cox*(Vg+ΔV1-Vs-Vth1)2/2L (二)
同理，可以得到如下所示的第二驱动晶体管的发光电流Ids2：
Ids2＝μ*W*Cox*(Vg+ΔV2-Vs-Vth2)2/2L (三)
基于公式二和公式三可知：第一驱动晶体管的栅极电位Vg、第一驱动晶体管的实时源极电位Vs分别与第二驱动晶体管的栅极电位Vg、第二驱动晶体管的实时源极电位Vs对应一致，所以，当△V1-△V2＝Vth1-Vth2时，即△V1-Vth1＝△V2-Vth2，此时，第一驱动晶体管的发光电流Ids1与第二驱动晶体管的发光电流Ids2相同，则第一子像素的显示亮度与第二子像素的显示亮度相同，同理，多个子像素的显示亮度同样可以通过本申请提供的方案补偿至同一显示亮度。
在其中一个实施例中，目标源极电位大于或者等于0V，且小于或者等于16V。例如，目标源极电位也可以为5V、8V、12V或者15V等。其中，随着目标源极电位的增加，寄生电容C1的充电速率更快，如此可以减少单次迭代侦测时间。
在其中一个实施例中，基于目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压的步骤包括：基于目标源极电位与第n-1次迭代侦测到的实时源极电位的差值，确定第n-1次类阈值电压；基于初始类阈值电压至第n-1次类阈值电压的累加之和，得到第n-1次补偿电压。
在其中一个实施例中，若第n次迭代侦测中驱动晶体管的实时源极电位等于目标源极电位，则第n+1次数据信号的电位与第n次数据信号的电位相同。
在其中一个实施例中，第n+1次及以后的预充电阶段、迭代侦测阶段中数据信号的电位均与第n次数据信号的电位相同。
在其中一个实施例中，外部补偿方法还包括：确定所述驱动晶体管的初始栅极电位、所述驱动晶体管的初始源极电位；配置初始栅极电位与初始源极电位的差值大于驱动晶体管的阈值电压。初始栅极电位可以为第1次迭代侦测中的栅极电位，初始源极电位可以为第1次迭代侦测中的实时源极电位。
在其中一个实施例中，外部补偿方法还包括：确定所述驱动晶体管的初始栅极电位、所述驱动晶体管的初始源极电位；配置目标源极电位与初始源极电位的差值大于零。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的像素电路及其外部补偿方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (10)

1.一种像素电路的外部补偿方法，其特征在于，包括：
确定所述像素电路中驱动晶体管的目标源极电位以及单次迭代侦测时间；
n次迭代侦测所述驱动晶体管的实时源极电位，直至所述驱动晶体管的实时源极电位等于所述目标源极电位，n为正整数；
根据所述目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压；
根据所述第n-1次补偿电压对所述驱动晶体管进行补偿。
2.根据权利要求1所述的外部补偿方法，其特征在于，所述基于所述目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压的步骤，包括：
根据所述目标源极电位与第n-1次迭代侦测到的实时源极电位的差值，确定第n-1次类阈值电压；
根据初始类阈值电压至所述第n-1次类阈值电压的累加之和，得到所述第n-1次补偿电压。
3.根据权利要求2所述的外部补偿方法，其特征在于，若第n次迭代侦测中所述驱动晶体管的实时源极电位等于所述目标源极电位，则第n+1次数据信号的电位与所述第n次数据信号的电位相同。
4.根据权利要求3所述的外部补偿方法，其特征在于，第n+1次及以后的预充电阶段、迭代侦测阶段中数据信号的电位均与所述第n次数据信号的电位相同。
5.根据权利要求1所述的外部补偿方法，其特征在于，所述外部补偿方法还包括：
确定所述驱动晶体管的初始栅极电位、所述驱动晶体管的初始源极电位；
配置所述初始栅极电位与所述初始源极电位的差值大于所述驱动晶体管的阈值电压。
6.根据权利要求1所述的外部补偿方法，其特征在于，所述外部补偿方法还包括：
确定所述驱动晶体管的初始栅极电位、所述驱动晶体管的初始源极电位；
配置所述目标源极电位与所述初始源极电位的差值大于零。
7.根据权利要求6所述的外部补偿方法，其特征在于，所述目标源极电位大于或者等于0V，且小于或者等于16V。
8.根据权利要求1至7任一项所述的外部补偿方法，其特征在于，所述单次迭代侦测时间大于或者等于0毫秒，且小于或者等于29毫秒。
9.根据权利要求8所述的外部补偿方法，其特征在于，所述单次迭代侦测时间大于或者等于0.5毫秒，且小于或者等于20毫秒。
10.一种像素电路，其特征在于，包括：
驱动晶体管；和
外部补偿模块，与所述驱动晶体管电性连接，用于确定所述驱动晶体管的初始栅极电位、所述驱动晶体管的初始源极电位、所述驱动晶体管的目标源极电位以及单次迭代侦测时间，其中，同一所述单次迭代侦测时间内，所述驱动晶体管的栅极电位与数据信号的电位相同；n次迭代侦测所述驱动晶体管的实时源极电位，直至所述驱动晶体管的实时源极电位等于所述目标源极电位，n为正整数；基于所述目标源极电位、第1次至第n-1次迭代侦测到的实时源极电位，确定第n-1次补偿电压；叠加所述第n-1次补偿电压至第n-1次数据信号的电位以生成第n次数据信号，第n次数据信号为第n次迭代侦测中的数据信号。
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