CN113807046B - Test excitation optimization regression verification method, system and medium - Google Patents
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Abstract
The invention discloses a test excitation optimization regression verification method, a system and a medium, wherein the method comprises the steps of respectively calculating test excitation index sets of all test excitation of each functional point set and functional point indexes of each functional point set aiming at regression test sets of chip design; descending the functional point sets according to the functional point indexes; sequencing all test excitation of each functional point set according to the test excitation indexes in the test excitation index set; and selecting test excitation from the function point set after sequencing optimization by adopting a preset scheduling strategy, and generating a new test excitation sequence until the function point set after sequencing optimization is empty. The invention can realize the optimization of regression test excitation sets of complex chips such as many-core processors and high-order routing chips, realize the optimization targets of defect detection rate and functional point coverage rate, and can improve the regression test efficiency.
Description
Technical Field
The invention relates to the field of computer aided design, in particular to a test excitation optimization regression verification method, a test excitation optimization regression verification system and a test excitation optimization regression verification medium, which are used for optimizing regression test excitation sets of complex chip designs such as many-core processors and high-order routing chips.
Background
With the technical development of integrated circuit realization, the development, upgrading and updating of serial chips are faster. In any stage of chip development, only the defects of the circuit are modified, and regression testing is used as an important means of chip verification and is frequently performed in the chip design process to ensure that the modification of the chip does not influence the original functions of the chip and introduce new errors. The huge test case set makes the running of regression testing very expensive. How to improve the efficiency of regression testing is an important issue.
The functional regression verification set of the complex chip design is the most complex, the most time-consuming and resource-consuming, the regression test set comprises test excitation of thousands of functional points, the regression test set is generally divided into a plurality of functional point test sets, the same functional point set is divided according to similarity of functions or parts, the number of defects found in the test process is up to hundreds, thousands and tens of thousands, when the design is improved or upgraded, the regression test set needs to be rerun, whether new problems are introduced is found, defects are found in time to be key points of regression tests, and the regression verification needs to be covered by all the functional points. Therefore, how to realize the optimization of regression testing stimulus sets of agile design of complex chips such as many-core processors and high-order routing chips has become a technical problem to be solved.
Disclosure of Invention
The invention aims to solve the technical problems: aiming at the problems in the prior art, the invention provides a test excitation optimization regression verification method, a system and a medium, which can realize the optimization of regression test excitation sets designed by complex chips such as many-core processors and high-order routing chips, realize the optimization targets of defect detection rate and functional point coverage rate and improve the efficiency of regression test.
In order to solve the technical problems, the invention adopts the following technical scheme:
a test stimulus optimization regression verification method, comprising:
1) Aiming at regression test sets of chip design, respectively calculating test excitation index sets of all test excitation of each functional point set and functional point indexes of each functional point set;
2) Descending the functional point sets according to the functional point indexes; sequencing all test excitation of each functional point set according to the test excitation indexes in the test excitation index set;
3) And selecting test excitation from the function point set after sequencing optimization by adopting a preset scheduling strategy, and generating a new test excitation sequence until the function point set after sequencing optimization is empty.
Optionally, the function point index in step 1) refers to an error detection rate and a function point coverage rate of the function point set; in step 2), sorting the function point sets according to the descending order of the function point indexes means sorting according to the priority order of the error detection rate and the function point coverage rate.
Optionally, the test excitation index set in step 1) includes an error detection rate, a functional point coverage rate and an approximation degree of the test excitation; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the error detection rate, the coverage rate of the functional points and the approximation degree.
Optionally, the test excitation index set in step 1) includes a run time, a functional point coverage, and an approximation of the test excitation; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the running time, the coverage rate of the functional points and the approximation degree.
Optionally, the calculation function expression of the error detection rate of the function point set is:
In the above formula, E RATEc represents the error detection rate of the function point set c, M is the number of test excitation included in the function point set c, r represents the number of design defects found by the test excitation i, and S represents the number of design defects found by the regression test set;
the calculated functional expression of the error detection rate of the test stimulus is:
ERATEi＝r/S，
In the above formula, E RATEi represents the error detection rate of the test excitation i, r represents the number of design defects found by the test excitation i, and S represents the number of design defects found by the regression test set;
the coverage rate of the functional points of the test excitation is cov [ i, j ] to represent the coverage rate of the functional points of the test excitation i to the functional j, if the test excitation i covers the functional j, the value of cov [ i, j ] is 1, and if the test excitation i does not cover the functional j, the value of cov [ i, j ] is 0;
The function coverage rate of the function points of the function point set is calculated by the following expression:
In the above expression, COVERc denotes the coverage rate of the function point set c, max denotes the maximum value, N is the number of function points, w j is the weight of the jth function point, cov [ j ] is the coverage rate of the jth function point, and there are:
cov[j]＝|(cov[i,j])，for，i＝1,2,…,M，
In the above formula, |represents OR operation, M is the test excitation number of the function point set c;
the expression of the calculation function of the approximation degree is as follows:
In the above equation, dist (i, k) represents the approximation of test stimulus i and test stimulus k, cov [ i, j ] represents whether test stimulus i covers function j, cov [ k, j ] represents whether test stimulus k covers function j, N is the number of functional points for exclusive OR operation.
Optionally, the chip design in the step 1) refers to a multi-core microprocessor implementing a directory cache protocol, and the types of each functional point set of the regression testing set include: cache conversion operation for specific addresses, directory protocol test, random cache replacement, random address, random access granularity test, random storage type test, random access, IO consistency hybrid test, test piece network, access between core and L2cache, access and error interrupt processing.
Alternatively, the ordering in step 2) refers to a descending order ordering.
Optionally, the scheduling policy preset in step 3) refers to round robin scheduling.
In addition, the invention also provides a test stimulus optimization regression verification system, which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the test stimulus optimization regression verification method.
Furthermore, the present invention provides a computer readable storage medium having stored therein a computer program programmed or configured to perform the test incentive optimization regression verification method.
Compared with the prior art, the invention has the following advantages: the method comprises the steps of respectively calculating a test excitation index set of all test excitation of each functional point set and functional point indexes of each functional point set aiming at a regression test set of chip design; descending the functional point sets according to the functional point indexes; sequencing all test excitation of each functional point set according to the test excitation indexes in the test excitation index set; and selecting test excitation from the function point set after sequencing optimization by adopting a preset scheduling strategy, and generating a new test excitation sequence until the function point set after sequencing optimization is empty. The invention can realize the optimization of regression testing excitation sets of complex chips such as many-core processors and high-order routing chip designs, realize the optimization targets of defect detection rate and functional point coverage rate, and can improve the regression testing efficiency. The invention prioritizes test excitation based on multi-objective optimization, has good test effectiveness, and obtains good regression test efficiency in practical engineering application.
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FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
FIG. 2 is a detailed flow chart of the method according to the embodiment of the invention.
Detailed Description
Embodiment one:
as shown in fig. 1 and 2, the test excitation optimization regression verification method of the present embodiment includes:
1) Aiming at regression test sets of chip design, respectively calculating test excitation index sets of all test excitation of each functional point set and functional point indexes of each functional point set;
2) Descending the functional point sets according to the functional point indexes; sequencing all test excitation of each functional point set according to the test excitation indexes in the test excitation index set;
3) And selecting test excitation from the function point set after sequencing optimization by adopting a preset scheduling strategy, and generating a new test excitation sequence until the function point set after sequencing optimization is empty.
Regression test sets of complex chip designs include test stimuli covering thousands of functional points, and are generally divided into classes of functional point test sets, the same functional point set being partitioned by functional similarity or component. In this embodiment, the function point index in step 1) refers to the error detection rate and the function point coverage rate of the function point set; in step 2), sorting the function point sets according to the descending order of the function point indexes means sorting according to the priority order of the error detection rate and the function point coverage rate.
In this embodiment, the test excitation index set in step 1) includes an error detection rate, a coverage rate of functional points, and an approximation degree of test excitation; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the error detection rate, the coverage rate of the functional points and the approximation degree.
In this embodiment, the expression of the function of calculating the error detection rate of the function point set is:
In the above formula, E RATEc represents the error detection rate of the function point set c, M is the number of test excitation included in the function point set c, r represents the number of design defects found by the test excitation i, and S represents the number of design defects found by the regression test set;
the calculated functional expression of the error detection rate of the test stimulus is:
ERATEi＝r/S，
In the above formula, E RATEi represents the error detection rate of the test excitation i, r represents the number of design defects found by the test excitation i, and S represents the number of design defects found by the regression test set; in the verification process of chip design, the probability of each test excitation operation finding out the design defect is recorded, the probability of the function point set finding out the design defect can be applied to prediction error reporting of regression test, the number of the design defects found by a certain function point set C test excitation i is r, the total number of the design defects found by the regression test set C is S, the error detection RATE E_RATE i = r/S of the test excitation i is that: M is the number of test stimuli comprised by the set of function points C.
The coverage rate of the functional points of the test excitation is cov [ i, j ] to represent the coverage rate of the functional points of the test excitation i to the functional j, if the test excitation i covers the functional j, the value of cov [ i, j ] is 1, and if the test excitation i does not cover the functional j, the value of cov [ i, j ] is 0; can be expressed as:
The function coverage rate of the function points of the function point set is calculated by the following expression:
In the above expression, COVERc denotes the coverage rate of the function point set c, max denotes the maximum value, N is the number of function points, w j is the weight of the jth function point, cov [ j ] is the coverage rate of the jth function point, and there are:
cov[j]＝|(cov[i,j])，for，i＝1,2,…,M，
In the above formula, |represents OR operation, M is the test excitation number of the function point set c; wherein the value of the weight w j may be adjusted according to the design feature being tested, for example: when a certain function point j is deleted or skipped, the function point weight of the weight w j may be set to 0. The system verilog language introduced by the IEEE standard defines coverage groups (coverage groups) and coverage properties (coverage properties) specifically for statistics of functional coverage. The mainstream EDA simulation tools also support this syntactic structure, automatically collecting and generating coverage reports. In the method, a DPI direct programming interface (DPI, direct Programming Interface) is built in a SystemVerilog language, in dynamic simulation verification, a program of the SystemVerilog and a test case written in C/C++ can be combined by using the DPI direct programming interface, the test case and the program of the SystemVerilog can be mutually called through the operation of import (import)/export (export), and the method of related coverage rate in the SystemVerilog language can also be called in the test case of C/C++ to realize the definition of a functional coverage group and collect coverage rate information of functional points in the simulation process.
In this embodiment, the expression of the approximation calculation function is:
In the above equation, dist (i, k) represents the approximation of test stimulus i and test stimulus k, cov [ i, j ] represents whether test stimulus i covers function j, cov [ k, j ] represents whether test stimulus k covers function j, N is the number of functional points for exclusive OR operation.
In this embodiment, the sorting in step 2) refers to a descending sorting. Step 2) comprises: first, the priority ranking of the set of function points of all types. The priority ordering rule of the function point sets is ordered according to the magnitude of the error detection rate of each type of function point set, and if the error detection rate is the same, the function point sets are ordered according to the magnitude of the function point coverage rate of the function point sets. Secondly, sequencing test excitation in the functional point set according to the magnitude of the error detection rate, if the error detection rate of the test excitation is zero, prioritizing according to the maximum value of the coverage rate of the functional points, if the error detection rate of several test excitation is the same as the coverage rate of the functional points, randomly selecting one test excitation, and then sequencing according to the rule that the smaller the functional similarity is, prioritizing.
In this embodiment, the preset scheduling policy in step 3) refers to round robin scheduling, that is, a round robin manner is adopted to sequentially select test incentives from a ordered set of function points, and an optimized regression test sequence is generated: selecting test excitation from the ordered functional point sets in a round-robin manner, adding an optimized test sequence, and selecting test excitation from the next functional point set until all the test excitation is extracted, wherein a certain type of functional point set is empty, so as to obtain a final regression test sequence. The regression test is very important in the verification of chip design, and the regression test ensures that the error detection rate of the test case set is maximized, so that the test case with strong error detection capability is executed preferentially in the continuous integrated development environment, the error is fed back quickly, and the efficiency of developers is improved. Meanwhile, the correct completion and safety of the functions are ensured, and certain changes of the circuit, such as design codes, configuration files or device structures of the circuit, are ensured not to influence the original circuit with correct functions, so that new errors are introduced.
In this embodiment, the chip design in step 1) refers to a multi-core microprocessor that implements a directory cache protocol, and the types of each functional point set of the regression test set include: cache conversion operation for specific addresses, directory protocol test, random cache replacement, random address, random access granularity test, random storage type test, random access, IO consistency hybrid test, test piece network, access between core and L2cache, access and error interrupt processing. Regression test sets of complex chip designs include test stimuli covering thousands of functional points, and are generally divided into classes of functional point test sets, the same functional point set being partitioned by functional similarity or component. For example, the directory component implementing the directory cache protocol is one of the most critical components of the multi-core microprocessor, and the regression verification is also the most complex, time-consuming and resource, and the regression test set includes test stimuli covering two thousands of function points, and can be divided into six types of function point test sets: the method comprises the steps of performing cache conversion operation, directory protocol test, random cache replacement, random address, random access granularity test, random storage type test, random access, IO consistency hybrid test, network on test piece, core and L2cache, access between accesses and error interrupt processing on a specific address, dividing the same functional point set according to the similarity of functions, and detecting more than three hundred errors by test, wherein when improvement or upgrading is designed, a regression test set needs to be rerun, whether a new problem is introduced is detected, defects are key points of the regression test, and regression verification needs to be covered by all functional points. The directory protocol verification period is long in time consumption, and the research on how to efficiently improve the regression testing efficiency has important theoretical significance and great practical value.
In summary, in the test excitation optimization regression verification method of the embodiment, in the verification process of the chip design, the coverage information of each test excitation collection function point is calculated, and the design defect found by each test excitation operation is recorded. According to the coverage rate of the test stimulus, counting the coverage rate of the functional points of each type of functional point set; calculating the similarity of test excitation included by all the functional point sets; counting the error detection rate of each type of function point set; the priority of all types of function point sets is ordered according to the error detection rate of each type of function point set; sequencing the test excitation in each functional point set according to the error detection rate of each test excitation, if the error detection rate of the test excitation is zero, prioritizing according to the maximum value of the functional coverage rate of the test excitation, if the error detection rate of several test excitation is the same as the functional coverage rate, randomly selecting one test excitation, and then sequencing according to the rule that the smaller the functional similarity is, the more preferentially sequencing is; the invention can realize the optimization of regression testing excitation sets of complex chips such as many-core processors and high-order routing chip designs, realize the optimization targets of defect detection rate and functional point coverage rate, and can improve the regression testing efficiency. The invention prioritizes test excitation based on multi-objective optimization, has good test effectiveness, and obtains good regression test efficiency in practical engineering application.
In addition, the embodiment also provides a test stimulus optimization regression verification system, which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the test stimulus optimization regression verification method.
Furthermore, the present embodiment provides a computer-readable storage medium having stored therein a computer program programmed or configured to perform the aforementioned test incentive optimization regression verification method.
Embodiment two:
the present embodiment is basically the same as the first embodiment, and the main differences are: the index error detection rate in the test excitation index set is replaced with the run time. The test case priority ranking method based on the running time and the functional coverage rate is used for optimizing targets, and can be applied to regression tests sensitive to time, such as realizing regression verification in limited time, and the ranked test excitation sequence deletes test excitation with low priority.
In this embodiment, the test excitation index set in step 1) includes the running time, the coverage rate of the functional points, and the approximation degree of the test excitation; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the running time, the coverage rate of the functional points and the approximation degree. Sequencing by runtime refers to the runtime occupancy rate sequencing of the set of function points C. The running time of the test stimulus i of a certain functional point set C is R, the running total time of the regression test set C is S, the running time occupation ratio R_RATE i =r/S of the test stimulus i, and the calculation function expression of the running time occupation ratio of the functional point set C is as follows:
where M is the number of test stimuli included in the set of function points C.
In addition, the embodiment also provides a test stimulus optimization regression verification system, which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the test stimulus optimization regression verification method.
Furthermore, the present embodiment provides a computer-readable storage medium having stored therein a computer program programmed or configured to perform the aforementioned test incentive optimization regression verification method.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (9)
1. A test stimulus optimization regression verification method, comprising:
1) Aiming at regression test sets of chip design, respectively calculating test excitation index sets of all test excitation of each functional point set and functional point indexes of each functional point set;
2) Descending the functional point sets according to the functional point indexes; sequencing all test excitation of each functional point set according to the test excitation indexes in the test excitation index set;
3) Selecting test excitation from the function point set after sequencing optimization by adopting a preset scheduling strategy, and generating a new test excitation sequence until the function point set after sequencing optimization is empty;
The function point index in the step 1) refers to the error detection rate and the function point coverage rate of the function point set; the calculation function expression of the error detection rate of the function point set is as follows:
，
In the above-mentioned method, the step of, Representing the error detection rate of the set of function points c,/>Including for the set of functional points c the number of test stimuli,/>Representing the number of design defects found by test stimulus i,/>Representing the number of design defects found by the regression testing set; the function coverage rate of the function points of the function point set is calculated by the following expression:
,
In the above-mentioned method, the step of, Function point coverage rate of the function point set c is represented, max is represented as a maximum value,/>For the number of functional points,/>Is the weight of the j-th functional point,/>Coverage rate for the j-th functional point is as follows:
，
In the above-mentioned method, the step of, Representing or operation,/>The number of test stimuli for function point set c;
In step 2), sorting the function point sets according to the descending order of the function point indexes means sorting according to the priority order of the error detection rate and the function point coverage rate.
2. The test excitation optimization regression verification method according to claim 1, wherein the test excitation index set in step 1) includes an error detection rate, a function point coverage rate, and an approximation degree of the test excitation; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the error detection rate, the coverage rate of the functional points and the approximation degree.
3. The test stimulus optimization regression verification method of claim 1, wherein the test stimulus index set of step 1) includes run time, functional point coverage and proximity of the test stimulus; the step 2) of sorting according to the test excitation indexes in the test excitation index set refers to sorting according to the priority order of the running time, the coverage rate of the functional points and the approximation degree.
4. A test stimulus optimization regression verification method according to claim 2 or 3, wherein the calculation function expression of the error detection rate of the test stimulus is:
，
In the above-mentioned method, the step of, Representing the error detection rate of test stimulus i,/>Representing the number of design defects found by test stimulus i,/>Representing the number of design defects found by the regression testing set;
Functional point coverage of the test stimulus Representing the functional point coverage of test stimulus i over function j, if test stimulus i covers function j/>Take a value of 1, if test stimulus i does not cover function j, then/>The value is 0;
the expression of the calculation function of the approximation degree is as follows:
,
In the above-mentioned method, the step of, Representing the approximation of test stimulus i and test stimulus k,/>Indicating whether test stimulus i covers function j,/>Indicating whether the test stimulus k covers the function j,/>For exclusive OR operation,/>Is the number of function points.
5. The test excitation optimization regression verification method according to claim 4, wherein the chip design in step 1) refers to a multi-core microprocessor implementing a directory cache protocol, and the types of the functional point sets of the regression test set include: the method comprises the following steps of cache conversion operation of addresses, directory protocol test, random cache replacement, random address, random access granularity test, random storage type test, random access, IO consistency hybrid test, test piece network on chip, access between a core and an L2cache and error interrupt processing.
6. The test stimulus optimization regression verification method of claim 5 wherein the ordering in step 2) is a descending order ordering.
7. The test incentive optimization regression verification method of claim 6, wherein the scheduling policy preset in step 3) is finger rotation scheduling.
8. A test stimulus optimization regression verification system comprising a microprocessor and a memory interconnected, characterized in that the microprocessor is programmed or configured to perform the steps of the test stimulus optimization regression verification method of any one of claims 1 to 7.
9. A computer readable storage medium having stored therein a computer program programmed or configured to perform the test incentive optimization regression verification method of any one of claims 1-7.
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| CN117768356B (en) * | 2024-02-21 | 2024-04-19 | 北京壁仞科技开发有限公司 | Prediction method and device, electronic equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0412611D0 (en) * | 2004-06-05 | 2004-07-07 | Ibm | Probabilistic regression suites for functional verification |
| CN105260534A (en) * | 2015-10-10 | 2016-01-20 | 浪潮(北京)电子信息产业有限公司 | Method and system for maintaining regression test cases for verifying ultra-large scale chip |
| CN112069081A (en) * | 2020-09-24 | 2020-12-11 | 中国人民解放军国防科技大学 | Genetic algorithm-based directory controller test excitation generation method |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8930912B2 (en) * | 2008-12-16 | 2015-01-06 | Cadence Design Systems, Inc. | Method and system for performing software verification |
-
2021
- 2021-10-09 CN CN202111178143.8A patent/CN113807046B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0412611D0 (en) * | 2004-06-05 | 2004-07-07 | Ibm | Probabilistic regression suites for functional verification |
| CN105260534A (en) * | 2015-10-10 | 2016-01-20 | 浪潮(北京)电子信息产业有限公司 | Method and system for maintaining regression test cases for verifying ultra-large scale chip |
| CN112069081A (en) * | 2020-09-24 | 2020-12-11 | 中国人民解放军国防科技大学 | Genetic algorithm-based directory controller test excitation generation method |
| CN112199291A (en) * | 2020-10-16 | 2021-01-08 | 天津飞腾信息技术有限公司 | Multi-core processor Cache consistency simulation verification method and verification device |
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