CN113805942A

CN113805942A - Processor core, processor and instruction processing method

Info

Publication number: CN113805942A
Application number: CN202110966962.2A
Authority: CN
Inventors: 薛雄伟
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2021-08-23
Filing date: 2021-08-23
Publication date: 2021-12-17

Abstract

The application discloses a processor core, a processor and an instruction processing method. The processor core includes: the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code; a decode unit to decode the instruction; and the execution unit is used for executing the instruction according to the decoding result of the decoding unit, wherein the decoding unit converts the first operation code based on at least one logic module to obtain a second operation code and decodes the second operation code, and each logic module receives the first operation code and provides at least one bit of data in the second operation code. In a plurality of different processor cores, different first operation codes and logic modules can be used for obtaining the same second operation code, so that the data confidentiality is greatly improved, and the data is prevented from being decompiled.

Description

Processor core, processor and instruction processing method

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a processor core, a processor, and an instruction processing method.

Background

A Central Processing Unit (CPU) is one of the main devices in a computer, and is used for performing tasks such as data Processing, computer instruction Processing, and program Processing. The CPU architecture is a specification to which the CPU complies, and in a general CPU architecture, execution of an instruction generally includes processes of fetch (fetch), Decode (Decode), Execute (Execute), and Write back (Write back).

The existing CPU architecture still needs to be improved to further improve its security.

Disclosure of Invention

The present disclosure is directed to a processor core, a processor and an instruction processing method.

According to a first aspect of the present invention, there is provided a processor core comprising: the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code; a decode unit to decode the instruction; and the execution unit is used for executing the instruction according to the decoding result of the decoding unit, wherein the decoding unit converts the first operation code based on at least one logic module to obtain a second operation code and decodes the second operation code, and each logic module receives the first operation code and provides at least one bit of data in the second operation code.

Optionally, each of the logic modules includes a plurality of logic gates, and the plurality of logic gates included in each of the logic modules are configured to have a connection relationship that is not identical, so that the first operation code corresponds to the at least one bit of data in the second operation code.

Optionally, each of the logic modules includes: a first module comprising at least one first logic gate and at least one buffer gate in a same number as the first logic gate, each first logic gate receiving at least one bit of data in the first opcode and providing first intermediate data, each buffer gate for receiving the at least one bit of data in the first opcode and providing second intermediate data, wherein the first logic gate and the second logic gate receiving the same at least one data in the first opcode form a combinational logic gate.

Optionally, each of the logic modules further includes: a second module comprising at least one second logic gate, each said second logic gate being connected to each said combinational logic gate and selectively receiving one of said first intermediate data and said second intermediate data provided by each said combinational logic gate, each said second logic gate providing a third intermediate data.

Optionally, each of the logic modules further includes: a third module comprising at least one third logic gate, each third logic gate coupled to an output of each second logic gate to provide one bit of data in the second opcode.

Optionally, the first logic gate is a not gate, the second logic gate is an and gate, and the third logic gate is an or gate.

Optionally, the number of the first logic gates corresponds to the number of bits of the first operation code.

Optionally, the decoding unit includes a plurality of the logic modules, the number of the first logic gate, the second logic gate, and the third logic gate included in each of the logic modules is a fixed value, and the connection relationships among the first logic gate, the buffer gate, the second logic gate, and the third logic gate included in each of the logic modules are not completely the same.

Optionally, the decoding unit includes one logic module, the number of the third logic gates included in the logic module is the same as the number of bits of the second operation code, an output of each third logic gate corresponds to one bit of data in the second operation code, and connection relationships between each third logic gate and the first logic gate and the second logic gate are not completely the same.

According to a second aspect of the invention, there is provided a processor comprising: a processor core as described above.

According to a third aspect of the present invention, there is provided an instruction processing method comprising: acquiring an instruction, wherein the instruction at least comprises a first operation code; decoding the instruction; and executing the instruction according to a decoding result of the decoding unit, wherein the step of decoding the instruction at least comprises the following steps of: the first opcode is converted based on at least one logic module to obtain a second opcode and the second opcode is decoded, each logic module configured such that the first opcode corresponds to at least one bit of data in the second opcode.

By adopting the technical scheme of the application, different coding modes can be customized in different devices, the decompiling of the instructions can be avoided, and the confidentiality and the safety of the computer are greatly improved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a computer system according to an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a processor core, according to an embodiment of the present disclosure;

FIG. 3 illustrates a schematic diagram of one exemplary logic module in accordance with embodiments of the present disclosure;

FIG. 4 shows a flow diagram of an instruction processing method according to an embodiment of the disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

It should be understood that, in the embodiments of the present application, a and B are connected, which means that a and B may be connected in series or in parallel, or a and B may pass through other devices, and the embodiments of the present application are not limited thereto.

A Central Processing Unit (CPU) is one of the main devices in a computer, and is used for performing tasks such as data Processing, computer instruction Processing, and program Processing. The CPU architecture is a specification to which the CPU complies, and in a general CPU architecture, an execution instruction generally includes processes of fetch (fetch), Decode (Decode), Execute (Execute), and Write back (Write back). Specifically, fetching is a process of fetching an instruction from a memory to an instruction register, decoding is a process of parsing the instruction into information that can be executed by a computer execution logic unit, executing is a process of loading the information acquired in the decoding stage to the execution logic unit for execution, and writing back is a process of putting back the processing result data of the execution stage to a place (for example, a certain memory module) designated by the instruction.

The instructions executed by the CPU generally include an opcode portion, an operand portion, and the like, where the opcode portion is used to express operations of the instruction that need to be performed, such as addition, subtraction, data movement, and the like, and the length of the opcode portion in the instruction is fixed, that is, the number of bits (bits) of the opcode portion is the same for different instructions. In the related art CPU implementation logic, the operation code part is generally processed by a decoding module (e.g., a decoder) to convert the operation code into a selection signal of the arithmetic logic unit of the processor, so as to implement the control from the operation code to the arithmetic processing unit.

In the related art, for the decoding modules of computers with the same architecture (for example, x86 architecture, ARM architecture, etc.), the encoding manner of the opcodes of the instruction set that can be analyzed is fixed, that is, only one type of opcode corresponds to one type of function instruction, and cannot be changed. For example, if the opcode of the add instruction is binary 0110 and the opcode of the subtract instruction is 1001 for a CPU of a certain architecture, then all machines using the CPU will perform the operations of adding the instruction receiving the binary 0110 opcode and subtracting the instruction receiving the binary 1001 opcode, which is fixed. This results in a computer software binary in which all the instructions and code correspondences are open, and thus the binary is easily decompiled, i.e., reverse engineered. By reverse engineering, a competitor or hacker can gain the internal logic of the software, thereby performing plagiarism, surpassing even hacking. Even though privacy is improved in some related art CPU architectures, which typically employ an improved way of software programming, there is still a risk of decompilation.

The inventors of the present application have found the above-mentioned problems of the computer and have provided a further improved processor core, processor, and instruction processing method.

The processor core, the processor and the instruction processing method provided by the application can be applied to various CPU architectures, such as an X86 architecture, an ARM architecture and the like, and can basically realize that each computer executes different operation code encoding modes. Taking the addition operation as an example, the opcode may be binary 0110, 1001, or 1100, as long as the opcodes satisfying different instructions are not duplicated.

Embodiments of a processor core, a processor, and an instruction processing method provided in the present application will be described below with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a computer system according to an embodiment of the present disclosure.

The computer system comprises, for example, a processor 10 and a memory 20, which are connected via a data bus between the processor 10 and the memory 20. Processor 10 includes a processor core 100, and processor core 100 is a core component for computing, receiving instructions, and processing data, the instructions being stored in memory 20, for example. Processor core 100 includes an instruction fetch unit 110, a decode unit 120, and an execution unit 130.

Instruction fetch unit 110 is configured to receive an instruction, which includes, for example, an operand and a first opcode. Decode unit 120 is used to decode instructions. The execution unit 130 is used for executing instructions according to the decoding result of the decoding unit 120.

In the embodiment of the present disclosure, the "first operation code" included in the instruction adopts a specially-made encoding manner of the present disclosure, the decoding unit 120 converts the specially-made "first operation code" into a "second operation code", and the "second operation code" adopts a conventional operation code encoding manner, thereby improving the security and confidentiality of the computer system. Further, each of the first operation code and the second operation code in the embodiment of the present disclosure has a one-to-one correspondence, and the connection relationship between the logic gates included in the logic module in the decoding unit 120 can characterize the correspondence relationship between the first operation code and the second operation code, and the circuit connection of the hardware further enhances the security and confidentiality of the computer system compared with the software programming.

In other embodiments, similarly, the connection relationship between the logic gates included in the logic modules in the decoding unit 120 may also characterize the specific encoding manner of the related operands. For example, during the manufacturing process of the processor core, the connection relation between the logic gates included in the logic module can represent the corresponding relation between the second operand in the conventional encoding mode and the first operand in the characteristic encoding mode, and during the later decoding process, the instruction including the first operand is received, and the first operand in the instruction is converted into the second operand, so that the confidentiality of the computer system can be further improved.

The present disclosure provides a processor 10 that is suitable for use in a variety of processor architectures, such as the X86 architecture, the ARM architecture, and the like, and has good security and safety. In the manufacturing process of the processor, different connection relations are written into logic gates contained in a plurality of logic modules of the processor by using fuses in the programming channels, and after the connection relations among the logic gates are written, the fuses are blown. The processor includes, for example, the processor core 100 shown in fig. 2 or a device for executing the instruction processing method shown in fig. 4, and details of the processor core 100 and the instruction processing method are not described herein again.

It should be understood that in other embodiments of the present disclosure, some of the components shown in fig. 1 may be omitted or the connections between the components may be implemented in different architectures, and some hardware and/or software modules not shown in fig. 1 may also be included, for example, components such as an instruction prefetch module may also be included, and two or more components shown in fig. 1 may also be combined into one component on a software architecture and/or a hardware architecture.

FIG. 2 shows a schematic diagram of a processor core, according to an embodiment of the present disclosure; FIG. 3 illustrates a schematic diagram of one exemplary logic module in accordance with embodiments of the present disclosure. For clarity, only a schematic diagram of the decode unit 120 in the processor core is shown in fig. 2.

In the disclosed embodiments, processor core 100 is configured to receive an instruction, decode the instruction, and execute the instruction according to the decoded result. Specifically, in the process of decoding the first operation code included in the instruction, the second operation code is obtained according to the first operation code, and the second operation code is decoded. The first operation code adopts a special coding mode in the disclosure, the second operation code adopts a conventional operation code coding mode, each first operation code corresponds to each second operation code, and the corresponding relation of the first operation code and the second operation code is stored in the connection relation between the logic gates contained in the logic module. For the same second opcode, the first opcode corresponding to the same second opcode in each processor core 100 is unique, for example, the conventional second opcode representing an add instruction is 0110, the first opcode corresponding to the second opcode 0110 in the first processor core provided by the present application is 1100, the first opcode corresponding to the second opcode 0110 in the second processor core provided by the present application is 1010, the first opcode corresponding to the second opcode 0110 in the third processor core provided by the present application is 1001, and so on, the first opcode corresponding to the second opcode 0110 in each processor core is different.

The following takes the processor core 100 shown in fig. 2 as an example to describe in detail a specific implementation of the processor core according to the embodiment of the present disclosure.

The processor core 100 includes a logic module 121 and a decoding module 122, where the logic module 121 is configured to receive a first operation code and convert the first operation code based on a connection relationship between logic gates included in at least one logic module to obtain a second operation code; and the decoding module 122 is configured to perform decoding processing on the second operation code. In each logic module 121, the connection relationship between the logic gates included therein represents the corresponding relationship between at least one bit of data in the first operation code and the second operation code. The method and the device utilize the connection relation between the logic gates contained in at least one logic module to represent the corresponding relation between at least one bit of data in the first operation code and the second operation code, so that the same second operation code can correspond to a plurality of different combinations of the first operation code and the logic module, thereby realizing different coding modes customized in different processor cores 100 and greatly improving the confidentiality and the safety of a computer.

In this embodiment, the logic module 121 includes a plurality of logic gates, and the plurality of logic gates included in each logic module are configured to have a connection relationship that is not identical, so that the first operation code corresponds to at least one bit of data in the second operation code.

As an example, please refer to fig. 3, each logic module 121 includes at least a first module 121a, and the first module 121a includes at least one first logic gate NOT, and each first logic gate NOT receives at least one bit of data in the first opcode and provides the first intermediate data.

In this example, the first block 121a further comprises at least one buffer gate BG in the same number as the first logic gates NOT, each buffer gate BG being adapted to receive at least one bit of data of the first opcode AND to provide the second intermediate data, wherein the first logic gates NOT AND the second logic gates AND receiving the same at least one bit of data of the first opcode form a combinational logic gate.

Optionally, each logic block 121 further includes a second block 121b, AND the second block 121b includes at least one second logic gate AND, each second logic gate AND is connected to each combinational logic gate AND selects one of the first intermediate data AND the second intermediate data provided by each combinational logic gate, AND each second logic gate AND provides one third intermediate data.

Optionally, each logic module 121 further comprises a third module 121c comprising at least one third logic gate OR, each third logic gate OR being connected to an output of each second logic gate AND to provide one bit of data in the second opcode.

In this example, the first logic gate NOT is a NOT gate, the second logic gate AND is an AND gate, AND the third logic gate OR is an OR gate. The number of first logic gates NOT corresponds to the number of bits of the first opcode.

In the example shown in fig. 3, the logic module 121 includes 4 first logic gates NOT, 4 buffer gates BG, 6 AND gates AND4 OR gates OR, AND the connection relationship between the logic gates can be referred to as an illustration, the logic module 121 only selects the output of one OR gate OR as the output of the logic module 121, AND takes the output as one bit of data in the second opcode (for example, the first bit of data in the second opcode).

For clarity of description, in the following description, the 4 first logic gates NOT from top to bottom in fig. 3 are respectively denoted as NOT1, NOT2, NOT3 AND NOT4, the 4 buffer gates BG from top to bottom are respectively denoted as BG1, BG2, BG3 AND BG4, the 6 AND gates AND from left to right are respectively denoted as AND1, AND2, AND3, AND4, AND5 AND6, AND the 4 OR gates OR from top to bottom are respectively denoted as OR1, OR2, OR3 AND OR 4. Then, in the example shown in fig. 3, NOT1, NOT2, NOT3, and NOT4 receive a non-repeating one bit of the 4-bit data of the first opcode and output data NOT-operated on the received data, respectively; BG1, BG2, BG3, BG4 respectively receive a non-repeating one bit of the 4-bit data of the first opcode and output the same data as the received data; the AND1 receives the outputs of NOT1, NOT2, NOT3 AND NOT4, when the outputs of NOT1, NOT2, NOT3 AND NOT4 are all 1, the AND1 outputs 1, otherwise, the AND1 outputs 0; the AND2 receives the outputs of NOT1, NOT2, BG3 AND BG4, when the outputs of NOT1, NOT2, BG3 AND BG4 are all 1, the AND2 outputs 1, otherwise the AND2 outputs 0; the AND3 receives the outputs of NOT1, BG2, NOT3 AND NOT4, when the outputs of NOT1, BG2, NOT3 AND NOT4 are all 1, the AND3 outputs 1, otherwise the AND3 outputs 0; the input ends of AND4, AND5 AND AND6 are suspended; the OR1 receives the outputs of the AND1, the AND2 AND the AND3, when any one of the AND1, the AND2 AND the AND3 outputs 1, the OR1 outputs 1, otherwise the OR1 outputs 0; the input ends of OR2, OR3 and OR4 are suspended.

The truth table for the logic cell shown in fig. 3 is shown in table 1.

Table 1:

in still other examples, the logic module 121 may comprise only some logic gates that are really electrically connected, for example only 4 first logic gates NOT, 4 buffer gates BG, 3 AND gates AND1 OR gate OR.

In some other examples, the first intermediate data, the second intermediate data, and the third intermediate data may each be at least one bit of data in the second opcode. For example, referring to fig. 3, the output of NOT3 in the first module 121a is taken as the first bit of data in the second opcode; the output of BG4 in the first module 121a is taken as the second bit of data in the second opcode; the output of NOT1 in the first module 121a is taken as the third bit of data in the second opcode; the output of the BG2 in the first module 121a is taken as the fourth bit of data in the second opcode. Alternatively, the output of the AND1 in the second block 121b is taken as the first bit of data in the second opcode; the output of the AND1 in the second block 121b is taken as the second data in the second opcode; the output of the AND1 in the second block 121b is taken as the third bit of data in the second opcode; the output of the AND1 in the second block 121b is taken as the fourth bit of data in the second opcode. It should be appreciated that to further enhance the security and safety of the system, more modules comprising a plurality of logic gates may be further provided in the logic module, for example, a fourth module (not shown) may be provided at the output of the third module 121c, and the fourth module may comprise one or more identical or different logic gates, and the output of each logic gate outputs one bit of data in the second operation code.

As another example, the logic module 121 provided in the embodiment of the present disclosure is configured to be programmable, the connection relationship between the logic gates included in each logic module is written into the logic module 121 via the fuse, and after the connection relationship between the logic gates included in each logic module is completely written into the logic module 121, the fuse is blown. Furthermore, the fuse is unrecoverable after being fused, so that after the programming of the connection relationship between the logic gates included in each logic module is completed, the connection relationship cannot be accessed by any other method of the system except the decoding unit 120 in the processor core 100, and the confidentiality and the safety of the device are further improved.

In this example, optionally, the decoding unit 120 includes a plurality of logic modules 121, the number of the first logic gate NOT, the second logic gate AND the third logic gate OR included in each logic module 121 is a fixed value, AND the connection relationship among the first logic gate NOT, the buffer gate BG, the second logic gate AND the third logic gate OR included in each logic module 121 is NOT exactly the same, so that the correspondence between the first opcode represented by the connection relationship among the logic gates included in each logic module 121 AND at least one bit of data of the second opcode is NOT exactly the same.

In an alternative example, the decoding unit 120 includes only one logic module 121, the logic module 121 includes the same number of third logic gates as the second operation code, and the output of each third logic gate corresponds to one bit of data in the second operation code, so that the third module 121c can output the complete second operation code. The scheme can give consideration to the performances of confidentiality, safety, circuit integration level, circuit power consumption and the like.

For example, referring to fig. 3, the input terminals of AND4, AND5, AND6 are selectively connected to one OR more of NOT1, NOT2, NOT3, NOT4, BG1, BG2, BG3, BG4, respectively, AND the input terminals of OR2, OR3, OR4 are selectively connected to one OR more of AND1, AND2, AND3, AND4, AND5, AND6, respectively, so that the output terminals of OR1, OR2, OR3, OR4 can provide the first bit data, the second bit data, the third bit data, AND the fourth bit data in the second operation code, respectively, that is, the connection relationship between the respective logic gates in the logic module 121 represents the corresponding relationship between the first operation code AND all the bit data in the second operation code.

In some other embodiments, the logic module 121 includes logic gates connected to each other in a predetermined combination, where the number of types of the predetermined combination is related to the number of bits of the second operation code, the number of types of the second operation code, and a corresponding relationship between the first operation code and at least one bit of data in the second operation code. In the plurality of processor cores provided by the embodiment of the disclosure, the connection relationship between the logic gates included in at least one logic module included in each processor core is selected from a non-repeating one of the predetermined combinations, so that when the plurality of processor cores acquire the same second operation code, they receive different first operation codes; and/or when multiple processor cores receive the same first opcode, they obtain a different second opcode.

Taking RISC-V32 instruction set as an example, the number of bits of the operation code (equivalent to the second operation code mentioned in the present disclosure) of the instruction is 7 bits, that is, the instruction set theoretically supports 128 kinds of operation codes, and then in the processor core 100 provided in the present disclosure, if 128 kinds of second operation codes are used and the connection relationship between the logic gates included in the logic modules represents the corresponding relationship between the first operation code and the one-bit data in the second operation code, the predetermined combination table in the present disclosure will have 128 factorial seed combinations, which reaches the order of 125 of 10, and the cracking difficulty is quite large, and basically, the encoding modes of each processor core 100 are all different.

Optionally, the number of the logic modules 121 is related to the number of bits of the second operation code and a corresponding relationship between at least one bit of data in the first operation code and the second operation code, and when a connection relationship between logic gates included in the logic modules 121 represents a corresponding relationship between one bit of data in the first operation code and the second operation code, the number of the logic modules 121 is the same as the number of bits of the first operation code or the second operation code. For example, if the number of bits of the second operation code is 4 bits, and the first operation code corresponds to one bit of data in the second operation code, the number of the logic modules 121 is also 4; if the number of bits of the second operation code is 4 bits and the first operation code corresponds to two bits of data in the second operation code, the number of the logic modules 121 is 2. Optionally, the logic module 121 may represent a corresponding relationship between all bit data in the first operation code and the second operation code, and only one logic module 121 needs to be used in this scheme.

The processor core of the embodiment of the disclosure represents the corresponding relationship between at least one bit of data in the first operation code and the second operation code by using the connection relationship between the logic gates included in at least one logic module, so that the random encoding of the computer instructions can be realized in different processor cores, the confidentiality and the safety of the computer are greatly improved, and the decompilation of the computer is avoided. Furthermore, the safety problem of computer software is solved by using a hardware scheme, the uniqueness of the circuit board can be ensured, the same technical effect as the embodiment of the disclosure cannot be achieved even if the circuit board is copied, the safety of the computer can be further ensured, and the copyright of the circuit can be effectively protected.

Some examples of the processor core of the embodiments of the present disclosure are described above, however, the embodiments of the present disclosure are not limited thereto, and there may be other extensions and variations.

For example, the processor core 100 may be a discrete device, may also be a circuit unit, and may also be a module in a computer. In other implementations, the aforementioned processor core 100 may be packaged in a device.

FIG. 4 shows a flow diagram of an instruction processing method according to an embodiment of the disclosure. The instruction processing method includes steps S1 to S3.

In step S1, an instruction is received, the instruction including at least a first opcode. In this step, optionally, after receiving the computer instruction, the computer instruction is divided into an operand and a first opcode.

In step S2, the first opcode is converted to obtain a second opcode based on at least one logic module, each logic module configured such that the first opcode corresponds to at least one bit of data in the second opcode, and the second opcode is decoded.

The instruction processing method of the embodiment of the disclosure uses the connection relationship between the logic gates included in at least one logic module to represent the corresponding relationship between at least one bit of data in the first operation code and the second operation code, so that the random encoding of the computer instruction can be realized in different devices for executing the instruction processing method, the confidentiality and the safety of the computer are greatly improved, and the decompilation of the computer is avoided.

And then, decoding the second operation code. Since the first operation code customized by the present disclosure has been converted into the second operation code of the conventional encoding manner, the second operation code can be decoded in the conventional manner, and the present disclosure does not limit the decoding manner of the second operation code.

In step S3, the instruction is executed according to the decoding result.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the disclosed embodiments, as described above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, to thereby enable others skilled in the art to best utilize the disclosure and various modifications as are suited to the particular use contemplated. The present disclosure is to be limited only by the claims and their full scope and equivalents.

Claims

1. A processor core, comprising:

the instruction fetching unit is used for obtaining an instruction, and the instruction at least comprises a first operation code;

a decode unit to decode the instruction; and

an execution unit to execute the instruction according to a decoding result of the decoding unit,

the decoding unit converts the first operation code based on at least one logic module to obtain a second operation code, and decodes the second operation code, wherein each logic module receives the first operation code and provides at least one bit of data in the second operation code.

2. The processor core of claim 1, wherein each of the logic modules comprises a plurality of logic gates, and wherein the plurality of logic gates of each of the logic modules are configured to have non-identical connections such that the first opcode corresponds to the at least one bit of data in the second opcode.

3. The processor core of claim 1 or2, wherein each of the logic modules comprises:

a first module comprising at least one first logic gate and at least one buffer gate in a same number as the first logic gate, each first logic gate receiving at least one bit of data in the first opcode and providing first intermediate data, each buffer gate for receiving the at least one bit of data in the first opcode and providing second intermediate data,

wherein the first logic gate and the second logic gate that receive the same at least one datum in the first opcode form a combinational logic gate.

4. The processor core of claim 3, wherein each of the logic modules further comprises:

a second module comprising at least one second logic gate, each said second logic gate being connected to each said combinational logic gate and selectively receiving one of said first intermediate data and said second intermediate data provided by each said combinational logic gate, each said second logic gate providing a third intermediate data.

5. The processor core of claim 4, wherein each of the logic modules further comprises:

a third module comprising at least one third logic gate, each third logic gate coupled to an output of each second logic gate to provide one bit of data in the second opcode.

6. The processor core of claim 5, wherein the first logic gate is a not gate, the second logic gate is an and gate, and the third logic gate is an or gate.

7. The processor core of claim 3, wherein the number of the first logic gates corresponds to a number of bits of the first opcode.

8. The processor core of claim 5, wherein the decoding unit comprises a plurality of the logic modules, the number of the first logic gate, the second logic gate and the third logic gate included in each of the logic modules is a fixed value, and the connection relationship among the first logic gate, the buffer gate, the second logic gate and the third logic gate included in each of the logic modules is not exactly the same.

9. The processor core of claim 5, wherein the decoding unit comprises one of the logic modules, the logic module comprises the same number of third logic gates as the second operation code, the output of each of the third logic gates corresponds to one bit of data in the second operation code, and the connection relationship between each of the third logic gates and the first logic gate and the second logic gate is not completely the same.

10. A processor, comprising:

the processor core of any one of claims 1 to 9.

11. An instruction processing method, comprising:

acquiring an instruction, wherein the instruction at least comprises a first operation code;

converting the first operation code based on at least one logic module to obtain a second operation code, and decoding the second operation code; and

the instruction is executed according to the result of the decoding,

wherein each of the logic modules is configured such that the first opcode corresponds to at least one bit of data in the second opcode.