CN102449969A - Circuits for soft logical functions - Google Patents

Abstract

A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. In an application of soft logic gates, a memory includes a group of electrical storage elements, each electrical storage elements carrying a respective storage values; a group of conversion elements, each conversion element being coupled to a respective electrical storage element for selectively converting the corresponding storage value to a current signal; and a current combination element for combining the current signals to form an output signal.

Description

The circuit that is used for the soft logic function

The cross reference of related application

The application advocates the U.S. Provisional Application sequence number the 61/156th that on March 2nd, 2009 proposed; The name that proposes in No. 794 and on March 2nd, 2009 is called the U.S. Provisional Patent Application sequence number the 61/156th of " Circuits for Soft Logical Functions "; No. 735 rights and interests, the two content is included in this paper with way of reference.

The name that proposes in the application and on March 2nd, 2009 is called the U.S. Provisional Patent Application sequence number the 61/156th of " Signal Mapping "; The name that proposed on January 11st, No. 721 1 is called the U.S. Provisional Patent Application sequence number the 61/293rd of " Belief Propagation Processor "; It is relevant that the name that proposes in No. 999 and on March 2nd, 2009 is called No. the 61/156th, 721, the U.S. Provisional Patent Application sequence number of " Belief Propagation Processor ".The content of above-mentioned application is included in this paper with way of reference.

Also to be called No. the 61/156th, 735, the U.S. Provisional Patent Application sequence number of " Circuits for Soft Logical Functions " relevant with the name that proposed on March 2nd, 2009 for the application, and its content is included in this paper with way of reference.

Technical field

This specification relates to the statistical disposition circuit, comprises the circuit of for example carrying out soft logic function (soft logical function).

Background technology

Statistical inference (statistical inference) utilizes statistics to make the deduction based on incomplete or coarse information.In need the application of information extraction from the observation of the data that suffer distortion with certain mode, it can be useful.For example, in communication system, the data of sending via the communication channel form of radio signal (for example with) can the distortion owing to noise, interference and/or reflection.When receiving these radio signals, receiver statistical inference technology capable of using obtains and handles soft (probabilistic) information, so that from these distorted signals, recover original transmission signal.

In some is implemented, can in analog domain, implement soft information processing, for example, through using the simulation statistical disposition continuous time circuit of carrying out the soft logic function such as soft being equal to (soft Equals) and soft XOR (soft XOR).In some example, utilize traditional translinear circuit (for example, adder and multiplier) to construct such analog circuit, in said traditional translinear circuit, the probability distribution of representing by current signal can be in linear domain addition and/or multiply each other.In these translinear circuits some are configured through the transistorized index I-V characteristic of utilizing particular type, and said transistor is for example for working in mos field effect transistor (MOSFET) or the bipolar junction transistor (BJT) in the sub-threshold region.

Summary of the invention

In one aspect; Substantially; A kind of soft logic of implementing is handled the interconnection that the circuit of network comprises the simulation process element, and said simulation process element comprises soft logic door (soft logic gates), and said soft logic door comprises one or more soft IF-AND-ONLY-IF gate (soft Equals gates).Each soft IF-AND-ONLY-IF gate comprises a plurality of circuit parts, and each part comprises: input part, said input part are configured to accept the voltage signal of soft logic amount and represent; And conversion portion, be configured to the voltage of accepting is represented that the corresponding current signal that converts this soft logic amount to representes.Each soft IF-AND-ONLY-IF gate further comprises: the signal combination part, be couple to the said conversion portion of said a plurality of circuit parts and be configured to form the said soft logic amount represented with said current signal and signal indication; And efferent, be used to provide the signal that partly forms by this signal combination.

Each side can comprise one or more in the following characteristic.

Said voltage signal represent respectively to comprise corresponding probable value basically based on to numerical representation.

Said voltage signal represent respectively to comprise likelihood ratio basically based on to numerical representation.

In each circuit part, said input part is configured on many signal line, receive the differential voltage signal indication of said soft logic amount.

Every signal line is couple to the corresponding crystal pipe that is configured to in the said conversion portion of superthreshold pattern work, and these transistors provide and the proportional basically differential current of soft logic amount with the differential voltage signal indication that receives.

In each circuit part, provide these transistors of said differential current be couple to the Current Regulation element with regulate these electric currents of providing by these transistors with.

Each transistor is couple to this Current Regulation element via resistive element.

These resistive elements are controlled, to influence the input-output characteristic of this soft IF-AND-ONLY-IF gate.

This input-output characteristic comprises linear characteristic.

Each resistive element comprises the MOS transistor that is configured to effect in three polar regions (triode region).

Said signal combination partly comprises signal conductor, and said signal conductor couples the said conversion portion of said conversion portion and provide the combination differential current signal of the differential current sum that is substantially equal to be provided by these conversion portions.

Said signal combination partly comprises the current-voltage conversion element, and, said soft logic amount and signal indication comprise differential voltage and represent.

Said signal combination part further comprises common source and common grid amplifier (cascode) part, and said common source and common grid amplifier partly is coupled between the signal conductor and this current-voltage conversion element that said conversion portion is coupled.

In each circuit part, said input is configured to the M system voltage signal of reception soft logic amount on many signal line to be represented, the distribution on a plurality of classes of said soft logic amount representative.

Said soft logic is handled network implementation factor graph (factor graph).

Said soft logic door further comprises one or more soft XOR gate, and each soft XOR gate is couple to one or more in these soft IF-AND-ONLY-IF gates.

On the other hand, substantially, a kind of soft logic of implementing is handled the interconnection that the circuit of network comprises the simulation process element, and said simulation process element comprises the soft logic door, and said soft logic door comprises one or more soft logic door.Each soft logic door comprises: a plurality of circuit parts, and each part comprises input part, said input part is configured to accept the voltage signal of soft logic amount and representes; And conversion portion, be configured to use the voltage of acceptance to represent to form the current signal that depends on this soft logic amount.In at least the first circuit part of said a plurality of circuit parts, this conversion portion is configured to change the voltage of said acceptance and representes to represent with the corresponding current signal that this soft logic amount is provided.In the part of second circuit at least of said a plurality of circuit parts, this conversion portion is configured to the voltage of said acceptance is represented to represent to combine to provide current signal to represent with the current signal that is provided by another circuit part in these circuit parts.This soft logic door further comprises the signal combination part, and this conversion portion that said signal combination partly is couple to one or more circuit part in the said circuit part is represented with the current signal of the output that forms this soft logic door.

Each side can comprise one or more in the following characteristic.

Said voltage signal represent respectively to comprise corresponding probable value basically based on to numerical representation.

Said voltage signal represent respectively to comprise likelihood ratio basically based on to numerical representation.

The output of said soft logic door comprises the logical function of soft logic amount.Said logical function is selected from the group that is made up of " with (AND) " function, " or (OR) " function, " with non-(NAND) " function and distance function.

In these soft logic doors at least one is configured to implement to be selected from the door of the group that is made up of soft AND gate, soft OR-gate, soft NOT-AND gate and soft partial sum gate.

In these soft logic doors at least one can be configured to implement to be selected from the door by at least two groups that constitute in soft AND gate, soft OR-gate, soft NOT-AND gate and the soft partial sum gate.

In each circuit part, said input part is configured on many signal line, receive the differential voltage signal indication of said soft logic amount.

Every signal line is couple to the corresponding crystal pipe that is configured to in the said conversion portion of superthreshold pattern work.

The transistor of said first circuit part is configured to provide and the proportional basically differential current of soft logic amount with the differential voltage signal indication that receives.

The transistor of said second circuit part is configured to provide the proportional basically differential current of product with the amount of representing with the soft logic amount of the differential voltage signal indication that receives with by the current signal that said another circuit part in the said circuit part provides.

Said signal combination partly is configured to form and the proportional basically current signal of product of the soft logic amount accepted representes that this gate is implemented soft distance function thus.

Each conversion portion comprises differential amplifier.

In these differential amplifiers at least some respectively comprise configurable resistive element, the characteristic of said configurable this differential amplifier of resistive element control.

This circuit further comprises a plurality of memory components (memory elements), and said a plurality of memory components provide by the voltage signal of the soft logic amount of at least some acceptance in the said soft logic door to be represented.

On the other hand, substantially, a kind of memory (memory) comprises a plurality of electric memory elements (electrical storage elements), and each electric memory element carries storing value separately.Said memory further comprises: a plurality of conversion elements, each conversion element are couple to separately electric memory element optionally to convert corresponding storing value to current signal.The currents combination element is used for these current signal combinations to form the output signal.

Each side can comprise one or more in the following characteristic.

Each conversion element comprises current converter and switch element (switching element).

This switch element is configured to by selecting signal activation.

Said memory further comprises control circuit, is used for producing said selection signal according to input.

This input comprises will be by the appointment of the subclass of the electric memory element of access.

Said a plurality of electric memory element comprises a plurality of charge storage cells that respectively carry electric charge.

Each charge storage cell comprises capacity cell.

Each conversion element comprises based on transistorized circuit element, is used for optionally charge conversion separately being become corresponding current signal.

Said output signal provides the successive value coding of the combination of said current signal.

The combination of the selected storing value of said output signal representative.

Said output signal comprises by the differential current encoded signals.

Substantially, others relate to memory, and said memory comprises: one group of electricity memory element, and each electric memory element carries storing value separately; One group of conversion element, each conversion element are couple to separately electric memory element to be used for optionally converting corresponding storing value to current signal; And the currents combination element, be used to make up said current signal to form the output signal.

Embodiment can comprise one or more in the following characteristic.

Each conversion element can comprise current converter and switch element.Said switch element can be configured to by selecting signal activation.This memory can further comprise control circuit, and said control circuit is used for producing this selection signal according to input.In some instances, this input comprises will be by the appointment of the subclass of the electric memory element of access.

This organizes electric memory element can comprise a plurality of charge storage cells, and said a plurality of charge storage cells respectively carry electric charge.Each charge storage cell can comprise capacity cell (for example, pair of electrical container).Each conversion element can comprise based on transistorized circuit element (for example, differential amplifier), is used for optionally charge conversion separately being become corresponding current signal.

The output signal of this memory can provide the successive value coding of the combination of these current signals.In some instances, it represents the combination of selected storing value.In some instances, this output signal comprises by the differential current encoded signals.

From following description and accessory rights requirement, further feature of the present invention and advantage are clearly.

Description of drawings

Fig. 1 is the schematic circuit of an embodiment of soft IF-AND-ONLY-IF gate.

Fig. 2 is the schematic circuit of second embodiment of soft IF-AND-ONLY-IF gate.

Fig. 3 is the schematic circuit of the 3rd embodiment of soft IF-AND-ONLY-IF gate.

Fig. 4 is the schematic circuit of the 4th embodiment of soft IF-AND-ONLY-IF gate.

Fig. 5 is the schematic circuit of the 5th embodiment of soft IF-AND-ONLY-IF gate.

Fig. 6 is the schematic circuit of an embodiment of soft XOR gate.

Fig. 7 is the block diagram of memory.

Fig. 8 is the schematic circuit of an embodiment of the memory of Fig. 7.

Fig. 9 is the figure of embodiment of the soft door of other type.

Embodiment

Enforcement with simulation (for example is used for; Basically continuous) the network of treatment element of logical function of the value represented of form can for example be used for various probabilistic, statistical or based on (belief based) processing method of reliability; In this manual for purposes of discussion; These processing methods are called as the soft logic processing method, and wherein represented value is called as the soft logic amount.In the calculating that relates to such value, these analogues value can be represented probability or relevant amount, such as likelihood, likelihood ratio, reliability or median.It can be useful in plurality of applications that soft logic is handled; Said application comprises that for example implementing reliability propagates (its a kind of form is called as " with long-pending (sum-product) " algorithm sometimes); Said reliability is propagated through going up transmission and work at probability graph model (for example, factor graph) as the message of analog quantity.

Being used for circuit that continuous time, soft logic was handled can use simulated assembly and be fabricated.In some instances; In such circuit; Probability distribution is by curtage (that is the proportional basically relation between probability of use and voltage and/or the current value) expression that can in linear domain, be processed through the addition in the network that is implemented on the simulation process element and/or multiply operation.Following description is paid close attention to and is suitable for forming the simulation process element that soft logic is handled the node in the network; For example, each implements soft logic operation, comprise softly be equal to, soft XOR, soft and and soft or; (being referred to as " soft logic door " or " soft door "); They are accepted the expression form of an analog representation (for example, with) of a plurality of soft probability and result's expression are exported as soft probability (for example, with identical or different expression).

In some instances, in log-domain or some other continuously and dull substantially transform domain and in the linear domain, the quantity of handling based on probability possibly be useful.For example, these analog signal input and output of these circuit elements are represented corresponding to the log-likelihood ratio (LLR) of probability distribution approx.Other compression of probability and/or S type conversion (sigmoidal transformation) also can be used.

In some instances, as following discussion, the soft logic amount is represented as uses a plurality of analog signals; For example; Be expressed as differential current or the differential voltage of using the signal link that leads to each amount, perhaps in some instances, use than two more links of signal link.

Following description provides some examples of the soft door circuit that utilizes the method and be configured.

1 soft IF-AND-ONLY-IF gate

1.1 have the soft IF-AND-ONLY-IF gate of the variable of binary value

In the circuit of the complete numeral of handling binary data, the input and output of gate are 0 or 1.Through analog logic door (or soft door), these input and output represent that probability or likelihood and scope can be between 0% and 100%, constraints for the probability that might export amount to 100%.

In certain embodiments, the soft IF-AND-ONLY-IF gate of ternary is carried out with minor function:

Wherein x and y are input variable, and Z is an output variable, and γ is for making the normalization factor of P (Z=0)+P (Z=1)=1.Here, each variable is got two probable values, and promptly 0 and 1, and the probability distribution of each variable (such as variable x) is by for example P (x=0), P (x=1) expression.In some instances, these two input variable x and y can represent two independently observers, and wherein each produces the estimation to output variable Z.

In some instances, the soft door in the factor graph is two-way.More particularly, guiding gets into or is actually two-way away from the edge of this soft door, and 3 unidirectional soft doors capable of using implement to surpass the two-way soft door of 3 variablees, and each door is accepted two input variables to produce output variable.

A kind of execution mode of above-mentioned soft IF-AND-ONLY-IF gate utilizes the transconductance linearity multiplier, and wherein, the probability distribution of these input variables is exported P (Z=0) and P (Z=1) as the current encoded signal multiplication in this circuit to form.

The another kind of execution mode of this soft IF-AND-ONLY-IF gate utilizes the electric current summation in log-likelihood ratio (LLR) scheme.More specifically, given equality (1a) with (1b), can obtain:

$\frac{P(Z=0)}{P(Z=1)}=\frac{P(x=0)\·P(y=0)}{P(x=1)\·P(y=0)}---\left(2\right)$

Equality (2) is transformed into this log-domain, provides following:

$\log \left(\frac{P(Z=0)}{P(Z=1)}\right)=\log \left(\frac{P(x=0)\·P(y=0)}{P(x=1)\·P(y=0)}\right)=\log \left(\frac{P(x=0)}{P(x=1)}\right)+\log \left(\frac{P(y=0)}{P(y=1)}\right)---\left(3\right)$

Through using " LLR " to represent the log-likelihood ratio of binary variable, such as being used for variable x's ${\mathrm{LLR}}_x=\mathrm{Log}\left(\frac{P(x=0)}{P(x=1)}\right),$ Equality (3) can be rewritten as:

LLR _Z＝LLR _x+LLR _y (4)

In other words, can be through obtaining the LLR addition of input variable x and y the LLR of output variable Z.

Consider now under more general situation, be the output variable Z of condition with the individual independent observation person of N (N>=2), each generation wherein is expressed as p for the estimation of P (Z=0) ₁..., p _NProviding under the condition of following observation,

$\frac{P(Z=0)}{P(Z=1)}=\frac{p_1{p}_{2}L{p}_N}{(1-p_1)(1-p_2)L(1-p_N)}---\left(5a\right)$

The LLR of variable Z can be obtained to be:

$\log \left(\frac{P(Z=0)}{P(Z=1)}\right)=\log \left(\frac{p_1{p}_{2}L{p}_N}{(1-p_1)(1-p_2)L(1-p_N)}\right)$

$=\log \left(\frac{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA0000102988130000011.png,HDA0000102988130000091.png"\; state="\{\{state\}\}">p</figure-callout>}}_1}{1-p_1}\right)+\log \left(\frac{{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="DEST\_PATH\_HDA0000110803130000011.png"\; state="\{\{state\}\}">p</figure-callout>}}_2}{1-p_2}\right)+L+\log \left(\frac{p_N}{1-p_N}\right)---\left(5b\right)$

It is roughly

${\mathrm{LLR}}_Z=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}\log \left(\frac{p_i}{1-p_i}\right)=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{\mathrm{LLR}}_i---\left(6\right)$

In other words, can carry out the LLR that addition obtains output variable Z through single LLR with these observers.This add circuit capable of using and by being implemented, in this add circuit, (perhaps approximate) input LLR and output LLR are represented in the circuit input and output respectively.

Fig. 1 shows and can be operating as an example that utilizes current summation to carry out the circuit structure 100 of the soft equivalent function of four variablees (i.e. three inputs).Notice that in the application based on factor graph, the soft IF-AND-ONLY-IF gate of four variablees will be referred to calculate whole four variablees, each variable uses other three variablees.These four calculating can be implemented in 4 circuit of one group respectively, and each circuit is accepted three variablees to produce the 4th variable.The example of explanation is implemented in these four circuit below.Other three circuit similar techniques capable of using but change input and output variable and being configured.

Here, circuit 100 comprise three differential to (pair) circuit 110,120 and 130, wherein each is accepted separately input signal (with the form of differential voltage) to form and input proportional basically signal (with the form of differential current).For example, in circuit 110, differential voltage signal delta v1 (is v ₁ ⁺-v ₁ ^-) be provided input as circuit 110, to produce and the proportional basically differential current signal Δ of Δ v1 i ₁(be i ₁ ⁺-i ₁ ^-).Then, all three circuit 110,120 are produced circuit output Δ I mutually with 130 current signal _OUT∝ (Δ v ₁+ Δ v ₂+ Δ v ₃).

In this circuit 100, each in said three input differential voltage signals can be represented the input LLR that (for example, its amplitude is scaled) is single.As a result, this output Δ I _OUTCan represent to export LLR, this output LLR is these three input LLR sums, shown in equality (6).

Notice that when being configured to accept all to have the input and output of LLR form, circuit 100 is effective as the soft IF-AND-ONLY-IF gate that needn't multiply each other through the electric current summation and operates.This can provide some advantages of the conventional softer IF-AND-ONLY-IF gate that is superior to utilizing the configuration of transconductance linearity method.For example, the fan-in that this method allow to increase (fan-in promptly is used for the number of the input of gate) and the essential supply voltage V that increases _DDOr the number of the element that will in this circuit, use (for example, transistor).By contrast, the soft IF-AND-ONLY-IF gate of some transconductance linearity possibly need the designer with 1) with transistorized voltage superposition get up or 2) utilize current mirror to carry out overlapping so that increase fan-in.Under this first kind of situation, transistorized number required in this transconductance linearity method increases soon than this method.Under this second kind of situation, current mirror can become the bottleneck of speed, for example, and as because during little electric current that their electric capacity causes.

Another advantage of this method relates to the simplicity of Hardware configuration, because electric current summation is actually the most cheap and one of available simulated operation accurately.Because soft IF-AND-ONLY-IF gate generally is used in the statistical disposition (for example, based on the processing of factor graph), so the efficient design of soft IF-AND-ONLY-IF gate makes it possible to improve overall circuit efficient.

The actual transfer function that the 3rd advantage is this soft IF-AND-ONLY-IF gate closely is similar to the mathematical transfer function that designed (be LLR with), because according to the current law (KCL) of Kirckoff, and in this circuit, the ground addition of electric current substantial linear.

Fig. 2 shows another example that can operate with the circuit structure 200 of carrying out the soft equivalent function of four variablees.At this, substitute output differential current signal Δ I _OUT, circuit 200 uses a pair of ohmic load R to form the differential voltage signal delta V of expression output LLR _OUTThese three input LLR are once more respectively by differential voltage signal delta v ₁, Δ v ₂With Δ v ₃Expression.

Fig. 3 shows the 3rd example that can operate with the circuit structure 300 of carrying out the soft equivalent function of four variablees.At this, circuit 300 is accepted three differential voltage signals of three inputs of expression LLR, to produce the output differential voltage signal of expression output LLR.In some applications, use cathode construction 340 can improve aspect some of circuit performance, isolate and increase circuit bandwidth such as improving input-output at lead-out terminal.

Notice that Fig. 1 is the sketch map of the circuit (the use simulated assembly is configured) that is operable as soft IF-AND-ONLY-IF gate to Fig. 3.Various alternative circuit design are possible, for example comprise having the circuit that is similar to above-mentioned structure but has extra active and/or non-active circuit element (such as resistor and transistor).

Fig. 4 for example shows the distortion of the circuit structure 100 shown in Fig. 1.In this example, each in these differential pair circuit (for example circuit 410) comprises and is couple to transistor T respectively ₁And T ₂A pair of fixed resistor R ₁And R ₂In some applications, the existence of the resistor in the said differential pair circuit has improved the linearity of circuit transfer function.Such variant can be applicable to the circuit structure shown in Fig. 2 and Fig. 3 similarly.

Fig. 5 shows another example that can operate with the circuit 500 of carrying out the soft equivalent function of four variablees.At this, each in these differential pair circuit (for example circuit 510) comprises a pair of configurable resistive element, such as being couple to transistor T respectively ₁And T ₂R ₁And R ₂These configurable resistive elements can be passive type resistor (for example, variable resistance), perhaps can be acting active element as resistor basically as alternative.An example of the active element that is suitable for using herein is as the acting MOS transistor that in this three polar region, is biased of resistor.In some instances, said configurable resistive element R ₁And R ₂Can have the variable I-V characteristic that can receive external signal control, this external signal for example is the signal that is provided by controller 540.In some applications, the configurability of these resistive elements can be adjusted effective transfer function of this differential pair circuit and/or entire circuit 500 as required.

Other example of some of soft IF-AND-ONLY-IF gate is described in the name that proposed on March 2nd, 2009 and is called in the U.S. Provisional Patent Application sequence number 61/156,735 of " Circuit for Soft Logical Functions ".

1.2 have the soft IF-AND-ONLY-IF gate of the variable of M hex value

Although above description shows the soft IF-AND-ONLY-IF gate of the variable of handling binary value, these general technologies can easily expand to the processing of M system variable (that is, can have the variable that quantity is m probable value, wherein m＞2).An example of the circuit that can be used as the soft IF-AND-ONLY-IF gate operation of handling m system variable is described for purposes of illustration, tout court.

Suppose a desirable m probable value, promptly 1 ..., the stochastic variable Z of m.Can use N independent observation person to obtain to have the probability of the Z of each value in these values, each among said N independent observation person provides the estimation of these values.For example, i observer provides and is represented as p _i(Z=1), p _i(Z=2) ..., p _i(Z=N) probability distribution.

Can obtain variable Z and be 1 probability:

P(Z＝1)＝γ·p ₁(Z＝1)p ₂(Z＝1)Lp _N(Z＝1)(7)

Similar for P (Z=2), or the like,

Wherein γ is a normalization factor, expression

$\mathrm{\&gamma;}=\frac{1}{\underset{k=1}{\overset{m}{\mathrm{\&Sigma;}}}{p}_1(Z=k)p_2(Z=k)L{p}_N(Z=k)}---\left(8\right).$

The probability (for example P (Z=m)) of a variable of selection as a reference.For any k value (1≤k＜m) wherein, so P (Z=k) can obtain about the log-likelihood of P (Z=m) as follows:

${\mathrm{LLR}}_{Z_k}=\log \left(\frac{P(Z=k)}{P(Z=m)}\right)=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}\log \left(\frac{p_i(Z=k)}{p_i(Z=m)}\right)=\underset{i=1}{\overset{N}{\mathrm{\&Sigma;}}}{\mathrm{LLR}}_{i,k}---\left(9\right)$

LLRz wherein _kThe variable Z that expression has value k is about the LLR with reference to m, LLR _{I, k}I the observer that expression has value k is about the LLR with reference to m.Note, be similar to equality (6), equality (9) can be implemented through summation, for example, uses to be similar to Fig. 1 and to obtain quantity to the circuit of the example of Fig. 5 and be each the LLRz in m-1 the k value _k

2 soft XOR gates

2.1 have the soft XOR gate of the variable of binary value

In certain embodiments, the binary system XOR gate in the circuit of complete numeral is carried out the function of mould 2 complementation additions.In this analog domain, the soft XOR gate of ternary can be carried out with minor function:

Wherein x and y are input variable, and z is an output variable.At this, each variable is got two probable values, and promptly 0 and 1.The soft XOR function of this ternary also can be represented as Z=x ⊕ y.

Can use following technology in the LLR scheme, to implement by equality (10a) and the soft XOR gate of (10b) describing.

LLR at given variable x is

Condition under, the as many as tanh (LLR of the differential probability of this variable (being P (x=0)-P (x=1)) _x/ 2), as follows:

$\tanh ({\mathrm{LLR}}_x/2)=\frac{e^{{\mathrm{LLR}}_x/2}-e^{-{\mathrm{LLR}}_s/2}}{e^{{\mathrm{LLR}}_x/2}+e^{-{\mathrm{LLR}}_s/2}}$

$=\frac{1-e^{-{\mathrm{LLR}}_s}}{1+e^{{-\mathrm{LLR}}_s}}$

$=\frac{1-\frac{P(x=1)}{P(x=0)}}{1+\frac{P(x=1)}{P(x=0)}}---\left(11\right)$

$=\frac{P(x=0)-P(x=1)}{P(x=0)+P(x=1)}$

$=P(x=0)-P(x=1)$

Similarly, for variable y, can obtain

tanh(LLR _y/2)＝P(y＝0)-P(y＝1)(12)，

And, can obtain for variable Z

tanh(LLR _Z/2)＝P(Z＝0)-P(Z＝1)(13)

Note, equality capable of using (10a) with (10b) as follows with tanh (LLRz/2) rewriting:

tanh(LLR _Z/2)＝P(Z＝0)-P(Z＝1)

＝(P(x＝0)·P(y＝0)+P(x＝1)·P(y＝1))-(P(x＝0)·P(y＝1)+P(x＝1)·P(y＝0)) (14)

＝(P(x＝0)-P(x＝1))·(P(y＝0)-P(y＝1))

Through applicable equations (11) and (12), it further produces

tanh(LLR _Z/2)＝tanh(LLR _x/2)·tanh(LLR _y/2)(15)

Thereby, at given LLR _xWith LLR _yUnder the condition as the input of arriving soft XOR gate, output LLR _zCan be obtained to do

LLR _Z＝2·tanh ^-1((tanh(LLR _x/2)·tanh(LLR _x/2))(16)

This has described the soft XOR function of theoretic ternary in the LLR territory.

Fig. 6 shows an example can operating with the circuit 700 of the theoretic soft XOR function shown in the approximated equation (16).At this, door 700 accepts two differential input signal Δ x and Δ y (all having voltage form) exports differential wave Δ I to produce _OUT(having current forms).Structurally, this door 700 comprises two importations.First importation comprises differential amplifier 710, and it accepts first differential voltage input Δ x to form differential current signal Δ i ₁(be i ₁ ⁺-i ₁ ^-), Δ i ₁Tanh (or the S type) function of approximate this first input, i.e. Δ i ₁∝ tanh (Δ x).Second importation comprises pair of differential amplifier 720 and 730, and wherein each is accepted second differential voltage input Δ y.This output to differential amplifier is connected to and makes the differential output Δ I of this circuit 700 _OUT(be i ₂ ⁺-i ₂ ^-) tanh (or the S type) function of approximate second input, i.e. Δ i _OUT∝ tanh (Δ y).Notice that each in the transistor in second importation also receives the differential current i that is produced by differential amplifier 710 at its source terminal ₁ ⁺, i ₁ ^-In separately one.Thereby, the differential output Δ I of circuit 700 _OUTAlso by Δ i ₁Convergent-divergent, it is given,

Δi _OUT∝tanh(Δx)·tanh(Δy)(17)。

For the input and output of the typical operation scope that falls into circuit 700, can be similar to tanh by the approximate linear function that increases pro rata of output and input ^-1Function.In other words, tanh ^-1(v) ≈ kv.Thereby, door output Δ I _OUTAlso can be regarded as as follows:

Δi _OUT∝tanh ^-1(tanh(Δx)·tanh(Δy))(18)

Note the similitude of equality (18) and equality (16).In fact, represent (for example, being provided as amplitude in proportion to) LLR respectively as the differential input Δ x and the Δ y of circuit 700 _x/ 2 and LLR _y/ 2 o'clock, the differential output Δ I of this circuit 700 _OUTApproximate this LLR _z, this LLR _zBe LLR by equality (16) definition _x/ 2 and LLR _y/ 2 soft XOR gate function.In other words, the actual transfer function of circuit 700 is similar to theoretical soft XOR function in the LLR territory.

In some cases, the similarity of side circuit tansfer function and theoretical soft XOR function can be enhanced (for example through the resistive element in the control circuit).For example, each in the differential amplifier in the circuit 710,720 and 730 comprise a pair of variable/controllable electrical resistance element is (such as R ₁And R ₂), the resistivity of this variable/controllable electrical resistance element possibly influence the transfer function of differential amplifier.Through changing the resistivity of selected or all resistive elements, the side circuit transfer function can be configured to being similar to closely the theoretic soft XOR function in the LLR territory.

For differential amplifier 710; When R → 0; Its transfer function shows as the S type function; And when R became

greater than this differential amplifier, the transfer function of this differential amplifier 710 becomes basically had (capped) of upper limit linear function.In some applications, adjust single resistive element (such as R ₁And R ₂) resistivity be useful with the transfer function of the expectation that realizes being used for specific differential amplifier.In some applications, so that it also is useful that circuit 700 can provide the transfer function of combination, the transfer function of this combination is being similar to more closely the soft XOR gate of theory in the LLR territory more than the resistive element in the differential amplifier in control.These resistive elements in this gate circuit can be taked various forms, comprise for example passive resistor and the transistor with some configuration that can be used as resistor.

Note, be similar to soft IF-AND-ONLY-IF gate, the mode that the soft XOR gate of describing among this paper also can plurality of optional be selected is configured.An example is the variant of circuit 700, and it exports signal through utilizing a pair of resistance load generating differential voltage output signal at lead-out terminal place but not produce differential current.

Foregoing description has been explained the circuit of a circuit element that is operable as the soft XOR gate of ternary that is implemented in the LLR territory.In some instances, the set that is equal on can function of the bigger soft XOR gate of N variable (N＞3) and being implemented based on the little soft XOR gate of ternary as described below.

Suppose x ₁, x ₂..., x _N-1Be that number is N-1 independent observation person, each predictor x _NValue.The soft XOR gate of N variable is carried out mould 2 complementation phase add operations to this N variable, as follows:

x _N＝x ₁⊕x ₂⊕...⊕x _N-1(19)

Through introducing one group of new variable y ₂..., y _N-1, equality (19) can be represented by each one group of new equality that only relates to three variablees:

y ₂＝x ₁⊕x ₂

y ₃＝y ₂⊕x ₃

y ₄＝y ₃⊕x ₄

.

.

.

y _N-1=y _N-2⊕ x _N-1, y wherein _N-1=x _N(20)

In Hardware configuration, this means that the soft XOR gate of N variable can be broken down into the chain of nucleus module (or tree), each nucleus module is based on the soft XOR of ternary that two input signals produce the output signal.When in the LLR territory, implementing, can use the soft XOR gate of a series of three inputs shown in Fig. 6 to construct the soft XOR of N variable.For example, based on equality (15), can obtain

$\tanh ({\mathrm{LLR}}_{x_N}/2)=\tanh ({\mathrm{LLR}}_{x_1}/2)\&CenterDot;\tanh ({\mathrm{LLR}}_{x_2}/2)\&CenterDot;L\&CenterDot;\tanh ({\mathrm{LLR}}_{x_{N-1}}/2)---\left(21\right)$

The soft XOR of N variable can be configured to generate expression LLRx through N-1 importation connected with cascade system _NThe output differential wave, wherein the corresponding input of expression LLRx is accepted in each importation _i(the differential voltage input of 1≤i＜N).Make in this way, can be through the soft XOR gate of extra ternary being introduced in the soft XOR circuit and increase the fan-in of soft XOR circuit efficiently.

The soft door of 3 other types

These above-mentioned methods and technology are not limited to soft being equal to and soft XOR gate, and can easily expand to the operation of other type, such as soft " or (OR) " and soft " with (AND) ".Can describe some examples of ternary soft door operation through following equality, following equality has been explained and has been accepted as the X of two input variables and Y with the circuit element of generation as the ternary soft door of the Z of output variable:

In some applications, the various types of soft doors of above-mentioned technical configuration capable of using.Fig. 9 illustrates the figure that can be reconfigured with the core circuit of implementing different soft doors.For example, this circuit comprises four output leads, and the product that every output lead has corresponding to a pair of input (is X ⁺Y ^-, X ⁺Y ⁺, X ^-Y ⁺, X ^-Y ^-) electric current.Can obtain the output of soft door through the suitable set of array output lead-in wire.For example, can pass through X ⁺Y ^-, X ^-Y ⁺, X ^-Y ^-Lead-in wire couples together and forms the Z of NAND gate ⁺, and can pass through this X ⁺Y ⁺Lead-in wire forms the Z of NAND gate ^-Can use other soft door of similar approach configuration.

4 use

4.1 analog memory

An application of soft door described herein relates to storage, for example is used for taking out storing value from analog memory.In certain embodiments, in reading the analog storage apparatus with storage stack unit, it possibly be useful that the value of the taking-up of the selected subclass of memory cell is carried out soft IF-AND-ONLY-IF gate operation.Of preamble, a kind of mode of carrying out soft IF-AND-ONLY-IF gate is the electric current summation that utilizes in the LLR territory.In this memory application, the current signal of the storing value of the selected set that this can be through being formed for representing memory cell and then these current signals summations are accomplished this point to produce output (this output can further be offered soft XOR gate and be used for error correction).

Fig. 7 shows an example of the storage arrangement 900 that couples with the soft IF-AND-ONLY-IF gate that is used to take out storing value.This storage arrangement 900 comprises one group of memory element such as 910A-C, and each in said one group of memory element is configured to carry storing value separately.These memory elements can be the energy storage elements (for example electromagnetic component) of capacitive element (for example, capacitor) or other type.Each memory element can be configured to memory cell.In some applications, these memory cell stores analogues value, these analogues value are illustrated in the message of dealing between the soft logic door of a part of propagate calculating as reliability.The application's further discussion is provided at the U.S. Provisional Patent Application sequence number the 61/293rd that the name that proposed on January 11st, 2010 is called " Belief Propagation Processor "; The name that proposes in No. 999 and on March 2nd, 2009 is called in No. the 61/156th, 721, the U.S. Provisional Patent Application sequence number of " Belief Propagation Processor ".

In order to take out the storing value in selected memory element 910, conversion element 920 is configured to convert corresponding storing value into current signal.Then; The current signal of representing the storing value of selected memory element (for example passes through currents combination circuit 930; The circuit that comprises common bus) be combined (for example, by sue for peace) export signal to produce, this output signal is that selected storing value soft is equal to output basically.

In some instances, each in the conversion element 920 comprise transducer 920 (for example, be used for charge-voltage converting become current signal based on transistorized transducer) and be used for current signal is couple to the switch 924 of currents combination circuit 930.Each switch 924 can further be configured to response external control, the selection signal that provides of controller 940 for example, and its appointment will be by the physical address of the subclass of the memory element 910 of access in each read operation.

In some instances; Controller 940 can be configured in each read operation, receive the appointment to the selected subclass of memory element; Current signal to produce the selection signal that activates respective switch, to make the storing value of representing selected memory element stands soft equality operation.In some instances; Storage arrangement can be arranged to the subclass of memory cell; For example, each subclass is arranged in different physical regions and is couple to common bus separately, and this common bus can be carried out this soft equality operation to the readout of the said subclass of memory cell.The subclass that perhaps in other words, need be fed to the memory cell of same soft IF-AND-ONLY-IF gate will be coupled to shared hardware (for example, common bus).Under these circumstances, controller 940 can have the subclass identifier, and said subclass identifier points to the predefined scope of physical address of respective subset that input is provided to the memory cell of public soft IF-AND-ONLY-IF gate in each read operation.

Note; In some legacy memory frameworks; Each memory value need be removed and be sent to then independently IF-AND-ONLY-IF gate on the independent output line of this memory, opposite with described legacy memory framework, in the method; The storing value that the input stage of soft IF-AND-ONLY-IF gate is merged in this memory with the subclass that allows memory cell is removed via shared nextport hardware component NextPort (for example, common bus).For example; Substitute to have and be couple to 8 memory cells respectively in order to send 8 single lines that need be fed to the current signal in the eight input IF-AND-ONLY-IF gates; Current signal from these 8 memory cells can be summed on the single line; This single line carries out soft being equal to these storing values effectively, to produce an output signal that will in circuit (for example, soft XOR gate) subsequently, be processed.Because the electric current from many lines can be combined into a line, because will drive less line, so storage access will consume less power.

Fig. 8 shows the detailed circuit diagram of an example of memory cell 900.In this example, each memory element 1010A comprises the pair of electrical container of carrying by the storing value of differential voltage (or electric charge) expression.Conversion element 1020A comprises the differential amplifier that switchably is couple to current source 1050.In order to read storing value, " read select signal " activates this switch 1024A so that current source 1050A is couple to this differential amplifier, and this differential amplifier will represent that then the differential voltage of this storing value converts differential current signal Δ i to ₁This differential current signal is provided to the currents combination circuit to generate output with other differential current signal combination (for example, summation), and this output is the soft equivalent function of selected storing value basically.

4.2 error correction decoder

Another Application relates to soft error correction decoding, and wherein, soft door described herein can be used to carry out the function of the numeric door of in digital decoder, using being carried out mirror image.Some examples of soft door in the error correction decoding are described in the United States Patent (USP) provisional application sequence number 61/156 that name is called " Signal Mapping "; 721 with the name be called in the U.S. Provisional Patent Application sequence number 61/293,999 of " Belief Propagation Processor ".The content of above-mentioned application is included this paper in way of reference.

The embodiment of 5 replaceabilities

In this described, circuit example was shown as the input and output signal that is configured to handle differential form.Notice that the circuit of handling single-ended signal also is possible.In some applications, it possibly be useful in circuit design, adopting differential wave for single-ended signal.The advantage of differential wave can comprise circuit operation for example than great dynamic range and higher noise immunity to interference (such as common mode inhibition).For example, if steady noise is introduced in two lines of differential input (or output), then can design the gate circuit that to ignore this constant add factor and will only respond poor (single order) between the signal on these two lines.

In some applications, use identical expression (for example, LLR representes) for each the input and output in the soft inference processor (for example, soft decoder) and needn't between difference is represented, figure signal be useful.During other was used at some, gate circuit also possibly taked a kind of expression (for example, with linear probability) to its input, and produces its output with another expression (for example, with LLR).(for example based on bigraph (bipartite graph); Soft IF-AND-ONLY-IF gate always presents soft XOR gate and vice versa) in some decoders of being configured; When being transformed to another kind of expression from a kind of expression (for example; From probability transformation is LLR) soft IF-AND-ONLY-IF gate when carrying out soft XOR gate (or other the constraint door) coupling of inverse transformation (for example, being transformed to probability) from LLR, these decoders will still be carried out the correct sequence of operation.This needs only the expression that unanimity is arranged at the every bit place of this figure also applicable to other inference processor and other soft door except soft IF-AND-ONLY-IF gate and soft XOR gate based on factor graph except decoder.

Other non-ideal characteristic that non-linear and these circuit that are associated with the circuit of presenting these soft doors are arranged in certain embodiments.As a result, the expression at each input/output terminal place can be that LLR representes just.For example, in the input (for example) of decoder, the modification slightly that can use LLR to represent by the signal of demapper circuitry generation.For example, through the irrational characteristic of compensating circuit to a certain extent, can carry out the nonlinear slightly mapping from LLR to the voltage signal better.

Above-mentioned soft door can be used on during statistical inference that informational needs wherein extracts from the observation of the data that distort with certain mode uses.Its therein information because incomplete data set and also possibly be useful in the uncertain application.Its differential therein informational needs by in the application of weighting, for example, as in medical diagnosis, also possibly be useful through its correlation or statistical significance.

The purpose of description that should be appreciated that the front is explanation rather than limits scope of the present invention that scope of the present invention is limited the scope of accompanying claims.In the scope of other embodiment claim below.

Claims (42)

1. implement the circuit that soft logic is handled network for one kind, said circuit comprises the interconnection of simulation process element, and said simulation process element comprises the soft logic door, and said soft logic door comprises one or more soft IF-AND-ONLY-IF gate, and each soft IF-AND-ONLY-IF gate comprises:

A plurality of circuit parts, each circuit part comprises

Input part, the voltage signal that is configured to accept the soft logic amount represent, and

Conversion portion is configured to the voltage of accepting is represented that the corresponding current signal that converts this soft logic amount to representes;

The signal combination part, be couple to the said conversion portion of said a plurality of circuit parts and be configured to form the said soft logic amount represented with said current signal and signal indication;

Efferent is used to provide the signal that is partly formed by this signal combination.

2. circuit as claimed in claim 1, wherein, said voltage signal represent respectively to comprise corresponding probable value basically based on to numerical representation.

3. circuit as claimed in claim 1, wherein, said voltage signal represent respectively to comprise likelihood ratio basically based on to numerical representation.

4. circuit as claimed in claim 1, wherein, in each circuit part, said input part is configured on many signal line, receive the differential voltage signal indication of said soft logic amount.

5. circuit as claimed in claim 4; Wherein, Every signal line is couple to the corresponding crystal pipe that is configured to in the said conversion portion of superthreshold pattern work, and these transistors provide and the proportional basically differential current of soft logic amount with the differential voltage signal indication that receives.

6. circuit as claimed in claim 5, wherein, in each circuit part, provide the transistor of said differential current be couple to the Current Regulation element with regulate the electric current that provides by these transistors with.

7. circuit as claimed in claim 6, wherein, each transistor is couple to the Current Regulation element via resistive element.

8. circuit as claimed in claim 7, wherein, said resistive element is controlled, to influence the input-output characteristic of this soft IF-AND-ONLY-IF gate.

9. circuit as claimed in claim 8, wherein, this input-output characteristic comprises linear characteristic.

10. circuit as claimed in claim 7, wherein, each resistive element comprises and is configured to the MOS transistor that in three polar regions, acts on.

11. circuit as claimed in claim 5; Wherein, Said signal combination partly comprises signal conductor, and said signal conductor couples the said conversion portion of said conversion portion and provide the combination differential current signal of the differential current sum that is substantially equal to be provided by these conversion portions.

12. circuit as claimed in claim 11, wherein, said signal combination partly comprises the current-voltage conversion element, and, said soft logic amount and signal indication comprise differential voltage and represent.

13. circuit as claimed in claim 12; Wherein, Said signal combination part further comprises the common source and common grid amplifier part, and said common source and common grid amplifier partly is coupled between the signal conductor and this current-voltage conversion element that said conversion portion is coupled.

14. circuit as claimed in claim 1, wherein, in each circuit part, said input is configured to the M system voltage signal of reception soft logic amount on many signal line to be represented, the distribution on a plurality of classes of said soft logic amount representative.

15. circuit as claimed in claim 1, wherein, said soft logic is handled the network implementation factor graph.

16. circuit as claimed in claim 1, wherein, said soft logic door further comprises one or more soft XOR gate, and each soft XOR gate is couple to one or more in the said soft IF-AND-ONLY-IF gate.

17. implement the circuit that soft logic is handled network for one kind, said circuit comprises the interconnection of simulation process element, said simulation process element comprises the soft logic door, and said soft logic door comprises one or more soft logic door, and each soft logic door comprises:

A plurality of circuit parts, each circuit part comprises

Input part, the voltage signal that is configured to accept the soft logic amount represent, and

Conversion portion is configured to use the voltage of acceptance to represent to form the current signal that depends on this soft logic amount;

Wherein, at least the first circuit part of said a plurality of circuit parts, this conversion portion is configured to change the voltage of being accepted and representes to represent with the corresponding current signal that this soft logic amount is provided; And

In the part of second circuit at least of said a plurality of circuit parts, this conversion portion is configured to the voltage of being accepted is represented to represent to combine to provide current signal to represent with the current signal that is provided by another circuit part in these circuit parts; And

This soft logic door further comprises the signal combination part, and the said conversion portion that said signal combination partly is couple to one or more circuit part in the said circuit part is represented with the current signal of the output that forms this soft logic door.

18. circuit as claimed in claim 17, wherein, said voltage signal represent respectively to comprise corresponding probable value basically based on to numerical representation.

19. circuit as claimed in claim 17, wherein, said voltage signal represent respectively to comprise likelihood ratio basically based on to numerical representation.

20. circuit as claimed in claim 17, wherein, the output of said soft logic door comprises the logical function of soft logic amount.

21. circuit as claimed in claim 20, wherein, said logical function is selected from the group that is made up of and function or function, NAND function and XOR function.

22. circuit as claimed in claim 17, wherein, at least one in the said soft logic door is configured to implement to be selected from the door by soft and door, the soft or group that door, soft NAND gate and soft XOR gate constitute.

23. circuit as claimed in claim 17, wherein, at least one in these soft logic doors can be configured to implement to be selected from the door by at least two groups that constitute in soft and door, soft or door, soft NAND gate and the soft XOR gate.

24. circuit as claimed in claim 17, wherein, in each circuit part, said input part is configured on many signal line, receive the differential voltage signal indication of said soft logic amount.

25. circuit as claimed in claim 24, wherein, every signal line is couple to the corresponding crystal pipe that is configured to in the said conversion portion of superthreshold pattern work.

26. circuit as claimed in claim 24, wherein, the transistor of said first circuit part is configured to provide and the proportional basically differential current of soft logic amount with the differential voltage signal indication that receives.

27. circuit as claimed in claim 26; Wherein, the transistor of said second circuit part is configured to provide the proportional basically differential current of product with the amount of representing with the soft logic amount of the differential voltage signal indication that receives with by the current signal that said another circuit part in the said circuit part provides.

28. circuit as claimed in claim 27, wherein, said signal combination partly is configured to form and the proportional basically current signal of product of the soft logic amount accepted representes that this gate is implemented soft XOR function thus.

29. circuit as claimed in claim 17, wherein, said conversion portion respectively comprises differential amplifier.

30. circuit as claimed in claim 29, wherein, at least some in the said differential amplifier respectively comprise the resistive element that can dispose, the characteristic of said this differential amplifier of resistive element control that can dispose.

31. circuit as claimed in claim 17 further comprises a plurality of memory components, said a plurality of memory components provide by the voltage signal of at least some the soft logic amounts accepted in the said soft logic door to be represented.

32. a memory comprises:

A plurality of electric memory elements, each electric memory element carries storing value separately;

A plurality of conversion elements, each conversion element are couple to separately electric memory element optionally to convert corresponding storing value to current signal; And

The currents combination element is used for said current signal combination to form the output signal.

33. memory as claimed in claim 32, wherein, each conversion element comprises current converter and switch element.

34. memory as claimed in claim 33, wherein, said switch element is configured to by selecting signal activation.

35. memory as claimed in claim 34 further comprises control circuit, said control circuit is used for producing this selection signal according to input.

36. memory as claimed in claim 35, wherein, this input comprises will be by the appointment of the subclass of the electric memory element of access.

37. memory as claimed in claim 32, wherein, said a plurality of electric memory elements comprise a plurality of charge storage cells, and said a plurality of charge storage cells respectively carry electric charge.

38. memory as claimed in claim 37, wherein, each charge storage cell comprises capacity cell.

39. memory as claimed in claim 37, wherein, each conversion element comprises based on transistorized circuit element, is used for optionally charge conversion separately being become corresponding current signal.

40. memory as claimed in claim 32, wherein, this output signal provides the successive value coding of the combination of said current signal.

41. memory as claimed in claim 32, wherein, the combination of the selected storing value of this output signal representative.

42. memory as claimed in claim 32, wherein, this output signal comprises by the differential current encoded signals.

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