CN113794374A - Mixed-mode boost converter suitable for battery voltage supply - Google Patents

Mixed-mode boost converter suitable for battery voltage supply Download PDF

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CN113794374A
CN113794374A CN202111138723.4A CN202111138723A CN113794374A CN 113794374 A CN113794374 A CN 113794374A CN 202111138723 A CN202111138723 A CN 202111138723A CN 113794374 A CN113794374 A CN 113794374A
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output
module
input
capacitor
inverter
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CN113794374B (en
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甄少伟
赵冰清
熊海亮
谢泽亚
杨芮
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a mixed-mode boost converter suitable for supplying voltage to a battery. The hybrid boost converter combines the switch capacitor voltage converter and the switch inductor voltage converter, reduces the voltage swing of a switch node and the average current of an inductor through the flying capacitor, thereby reducing the switch loss and the inductor DCR loss of a power switch tube, simultaneously increasing the duty ratio of a control signal, realizing the voltage conversion ratio more than 2, and being suitable for the application of portable equipment under high frequency.

Description

Mixed-mode boost converter suitable for battery voltage supply
Technical Field
The invention belongs to the field of integrated circuits and the technical field of switching power supplies, and particularly relates to a mixed-mode boost converter suitable for supplying voltage to a battery.
Background
Boost converters are used more and more widely as important components of power management modules. With the development of scientific technology and the generation of a large number of low-power-consumption and high-performance portable applications, the performance requirements for the boost converter are higher and higher, and especially the boost converter with high energy Conversion efficiency and high voltage Conversion Ratio (CR) becomes a key point of wide attention. A Conventional DC-DC Boost Converter (CBC) has a large switching stress of a power transistor, and thus generates a large switching loss during a switching operation, which makes it difficult to achieve high energy conversion efficiency. In addition, conduction loss caused by Direct Current Resistance (DCR) is particularly significant in CBC, and particularly when the output Current is large, the DCR loss of the inductor becomes a main part of energy loss of the DC-DC converter, so that the energy conversion efficiency of the CBC is greatly reduced. This problem is particularly pronounced in portable devices with stringent requirements for power consumption, where large DCR losses also cause difficulties in heat dissipation.
On the other hand, in some applications requiring a high voltage conversion ratio, a larger control signal duty cycle is required. Generating an excessive control signal duty cycle is a significant challenge for the control signal generation circuit. Due to the limitation of the problems of time delay of a peripheral control circuit and a driving circuit and the like, the duty ratio of a large control signal is difficult to realize, so that the further improvement of the voltage conversion ratio is limited, and the application of CBC under high frequency is also limited. In order to realize application under high-voltage difference boosting and high frequency, a higher CR boost converter is needed to realize the reduction of the requirement on the duty ratio of a control signal under the condition of the same voltage conversion ratio as that of CBC, so that the complexity and the design difficulty of a control circuit are reduced, and the area cost and the labor cost of a chip are further saved.
Disclosure of Invention
The invention aims to provide a hybrid boost converter suitable for portable equipment and battery voltage supply, which can reduce the DCR loss of an inductor and the switching loss of a power switching tube, improve the energy conversion efficiency and realize a voltage conversion ratio more than 2.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a mixed-mode boost converter suitable for supplying voltage to battery is composed of the first NMOS transistor MN1,A second NMOS transistor MN2, a third NMOS transistor MN3, and a flying capacitor CFInductor L and first output capacitor COLoad resistance ROOperational amplifier, PMOS switch tube, PMOS adjusting tube, first resistor R1, second resistor R2, first bootstrap capacitor CBoot1A second bootstrap capacitor CBoot2Voltage source VREFA diode, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a first potential translation module LS1, a second potential translation module LS2, a third potential translation module LS3, a first PMOS transistor MSP1, a second PMOS transistor MSP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NAND gate NAND1, a second NAND gate 2, a first DELAY module DELAY1, a second DELAY module DELAY2, a third DELAY module DELAY3 and a fourth DELAY module DELAY 4;
wherein, the source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor CFA gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 outputted by the first driving module DRV1, a drain of the first NMOS transistor MN1 is an output terminal of the boost converter, and is connected to the output capacitor COAnd a load resistance ROA first output capacitor COAnd a load resistance ROThe other ends of the two are grounded; the source of the second NMOS transistor MN2 is connected to the input voltage VINMeanwhile, the gate of the second NMOS transistor MN2 is connected to the second driving signal output by the second driving module DRV 2; the source of the third NMOS transistor MN3 is grounded, the gate is connected to the third driving signal outputted by the third driving module DRV3, and the drain of the third NMOS transistor MN3 is connected to the other end of the inductor L and the flying capacitor CFThe other end of (a);
the inverting input terminal of the operational amplifier is connected to a voltage source VREFThe non-inverting input end of the operational amplifier is connected with one end of a first resistor R1 and one end of a second resistor R2, and the output of the operational amplifier is connected to the grid electrode of the PMOS adjusting tube; the source of the PMOS adjusting tube is connected with the cathode of the diode, the drain of the PMOS adjusting tube is connected with the other end of the first resistor R1 and the second resistorTwo bootstrap capacitors CBoot2And to the power supply terminal of the second driver module DRV 2; the other end of the second resistor R2 and a second bootstrap capacitor CBoot2And the other end of (V) and a voltage source VREFNegative poles of the two-phase current transformer are connected with an input voltage VIN；
The power supply terminal of the first driving module DRV1 is connected to the first bootstrap capacitor CBoot1The ground end of the first driving module DRV1 is connected with the source electrode of a first NMOS transistor MN1, the input end of the first driving module DRV1 is connected with the output of the first potential translation module LS1, and the output of the first driving module DRV1 is connected with the grid electrode of a first NMOS transistor MN 1;
the power supply of the second driving module DRV2 is connected with the second bootstrap capacitor CBoot2The ground terminal is connected to the input voltage VINThe input end of the second driving module DRV2 is connected to the output of the second level shift module LS2, and the output of the second driving module DRV2 is connected to the gate of the second NMOS transistor MN 2;
the power supply terminal of the third driving module DRV3 is connected to the voltage VDRThe ground terminal is grounded, wherein VDRIs the driving voltage of the switching tube, when VINWhen less than 5V, VDR＝VIN(ii) a When V isINWhen greater than 5V, V DR5V; the input end of the third driving module DRV3 is connected to the output end of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN 3;
the input supply terminal of the first level shift module LS1 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the first level shift module LS1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first level shift module LS1 is connected with the output end of the seventh inverter INV7, and the output end of the first level shift module LS1 is connected with the input end of the first driving module DRV 1;
the input supply terminal of the second level shift module LS2 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the second driving module DRV1, and the output ground end of the second level shift module LS2 is connected with the input voltage VINThe input end of the second level shift module LS2 is connected to the output end of the second inverter, and the output end of the second level shift module LS2The terminal is connected to the input terminal of the second driving module DRV 2;
the input supply terminal of the third level shift module LS3 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the third potential translation module LS3 is connected with the source electrode of the first NMOS transistor MN1, the input end of the third potential translation module LS3 is connected with the output end of the third inverter INV3, and the output end of the third potential translation module LS3 is connected with the gate electrode of the first PMOS transistor MSP 1;
a first bootstrap capacitor CBoot1The upper polar plate is connected with a power supply end of the first driving module DRV1, and the lower polar plate is connected with a source electrode of a first NMOS transistor MN 1;
second bootstrap capacitor CBoot2The upper plate is connected to the power supply terminal of the second driving module DRV1, the lower plate and the input voltage VINConnecting;
the source electrode of the PMOS switching tube is connected with the power supply end of the first driving module DRV1, the grid electrode of the PMOS switching tube is connected to the output of the third potential translation module LS3, and the drain electrode of the PMOS switching tube is connected with the power supply end of the second driving module DRV 1; the anode of the diode is connected with the source electrode of a first NMOS transistor MN1, and the cathode of the diode is connected with the source electrode of a second PMOS transistor MSP 2;
one input end of the first NAND gate NAND1 is connected with the PWM signal, the other input end thereof is connected with the output end of the first inverter INV1, the output end of the first NAND gate NAND1 is connected with the input end of the first DELAY module DELAY1, and the input end of the first inverter INV1 is connected with the output end of the seventh inverter INV 7; the output end of the first DELAY module DELAY1 is connected with one end of a first capacitor C1 and the input end of a second DELAY module DELAY2, and the other end of the first capacitor C1 is grounded; the output end of the second DELAY module DELAY2 is connected to one end of the second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with one input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected with the output end of the fourth inverter INV4, and the input end of the fourth inverter INV4 is connected with the PWM signal; the output end of the second NAND gate NAND2 is connected with the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of the third DELAY module DELAY3, the output end of the third DELAY module DELAY3 is connected with one end of the third capacitor C2 and the input end of the fourth DELAY module DELAY4, and the other end of the third capacitor C3 is grounded; the output end of the fourth DELAY module DELAY4 is connected to one end of the fourth capacitor C4 and the input end of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; an output of the sixth inverter INV6 is connected to an input of the seventh inverter INV 7.
The invention has the advantages that the hybrid boost converter is combined with the switch capacitor voltage converter and the switch inductor voltage converter through the flying capacitor CFThe average current of the inductor and the voltage swing of a switch node are reduced, so that the loss of the inductor DCR and the switching loss of a power switch tube are reduced, the duty ratio of a control signal is increased, a high voltage conversion ratio is realized, and the method is suitable for application under high voltage conversion ratio and high frequency.
Drawings
FIG. 1 is a power stage topology for a hybrid boost converter in accordance with the present invention;
FIG. 2 is a circuit diagram of a hybrid boost converter power stage topology in accordance with the present invention;
FIG. 3 is a waveform diagram illustrating the operation of the power stage topology of the hybrid boost converter in accordance with the present invention;
FIG. 4 is a circuit diagram of an embodiment of the present invention;
FIG. 5 is a timing logic diagram of an embodiment of the present invention;
FIG. 6 is a graph comparing efficiency curves of an embodiment of the present invention and a conventional boost converter.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
for convenience of description, the hybrid boost converter of the present invention is divided into three parts, a power stage topology, a bootstrap driver circuit module, and a dead-zone generation circuit. The power stage topology comprises three power switching tubes S1, S2 and S3 and a flying capacitor CFAn inductor L, an output capacitor COAnd a load resistor ROAs in fig. 1. The power switch tube can adopt an NMOS tube or a PMOS tube. Using NMOS tube asFor example, the first NMOS transistor MN1 is a switch S1, the second NMOS transistor MN2 is a switch S2, and the third NMOS transistor MN3 is a switch S3, as shown in fig. 2. The source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor CFHas a gate connected to the driving signal TG1 and a drain connected to the output capacitor COAnd a load resistance RO. The source of the second NMOS transistor MN2 is connected to the input, and is also connected to one end of the inductor L, and the gate is connected to the driving signal TG 2. The source of the third NMOS transistor MN3 is grounded, the gate is connected to the driving signal BG1, the drain is connected to the other end of the inductor L and the capacitor CFAnd the other end of the same. Output capacitor COAnd a load resistance ROThe other ends of the two are all grounded.
The bootstrap driving circuit module shown in fig. 3 includes three driving modules DRV1, DRV2, DRV3, three Level Shift modules (Level Shift) LS1, LS2, LS3, and two bootstrap capacitors CBoot1、CBoot2The power supply comprises a switch PMOS tube MSP1, a PMOS adjusting tube MSP2, a diode D1, an operational amplifier A1, feedback resistors R1 and R2 and a voltage source VREF1. The power supply terminal BST1 of the first driving module DRV1 is connected to the bootstrap capacitor CBoot1The ground terminal is connected with the first switch node SW1, the input terminal is connected with the output of the first Level Shift module LS1, and the output terminal is connected to the grid TG1 of the first NMOS transistor MN 1. The power supply terminal BST2 of the second driving module DRV2 is connected to the bootstrap capacitor CBoot2Ground terminal connected to input voltage VINThe input end of the second Level Shift module LS2 is connected to the output end of the second Level Shift module LS2, and the output end of the second Level Shift module LS2 is connected to the gate TG2 of the second NMOS transistor MN 2. The power supply terminal of the third driver module DRV3 is connected to the output voltage V of the LDO moduleDRGround terminal is grounded, wherein VDRIs the driving voltage of the switching tube, when VINWhen less than 5V, VDR＝VIN(ii) a When V isINWhen greater than 5V, V DR5V. The input end of the DRV3 is connected to the output signal PWM1 of the dead-time generation circuit module, and the output is connected to the gate BG1 of the third NMOS transistor MN 3. The input power supply end of the first Level Shift module LS1 is connected with VDRAn input ground terminal is grounded, an output power supply terminal is connected with the BST1, an output ground terminal is connected with the first switch node SW1, an input terminal is connected with an output signal NPWM1 of the dead zone generating circuit, and an output terminal is connected with an output of the first driving module DRV1And (4) entering the terminal. The input power supply end of the second Level Shift module LS2 is connected with VDRThe input ground terminal is grounded, the output power supply terminal is connected with BST2, and the output ground terminal is connected with an input voltage VINThe input end of the dead zone generating circuit is connected with the output signal PWM1 of the dead zone generating circuit, and the output end of the dead zone generating circuit is connected with the input end of the second driving module DRV 2. The input power supply end of the third Level Shift module LS3 is connected with VDRThe input ground end is grounded, the output power supply end is connected with the BST1, the output ground end is connected with the first switch node SW1, the input end is connected with the output signal PWM2 of the dead zone generating circuit, and the output end is connected with the first bootstrap capacitor C of the grid GP1 of the first PMOS tube MSP1Boot1The upper plate is connected to BST1, and the lower plate is connected to a first switching node SW 1. Second bootstrap capacitor CBoot2The upper plate is connected to BST2, the lower plate and the input voltage VINAre connected. The source electrode of the first PMOS transistor MSP1 is connected with BST1, the grid electrode GP1 is connected with the output of the third Level Shift module LS3, and the drain electrode is connected with BST 2. The anode of the diode D1 is connected to the first switching node SW1, and the cathode is connected to the source of the second PMOS transistor MSP 2. The gate of the second PMOS transistor MSP2 is connected to the output terminal of the operational amplifier a1, and the drain is connected to the BST 2. The non-inverting input terminal of the operational amplifier A1 is connected to one terminal of the resistors R1 and R2, and the inverting input terminal is connected to the voltage source VREF1The positive electrode of (1). The other end of the resistor R1 is connected to BST2, and the other end of the resistor R2 is connected to the input voltage VIN. Voltage source VREF1Negative pole of (2) is connected with input voltage VIN。
The dead time generation circuit comprises seven inverters INV1, INV2, INV3, INV4, INV5, INV6 and INV7, two NAND gates NAND1 and NAND2, four DELAY modules DELAY1, DELAY2, DELAY3 and DELAY4 and four capacitors C1, C2, C3 and C4, as shown in FIG. 4. An input of the first inverter INV1 is connected to an output of the seventh inverter INV7, and an output terminal is connected to an input of the first NAND gate NAND 1. The second inverter INV2 has an input connected to the output of the second DELAY module DELAY2 and the capacitor C2, and an output connected to the input of the third inverter INV3 as the output signal PWM 1. The input of the third inverter INV3 is connected to the output of the second inverter INV2, and the output is connected to the input of the second NAND gate NAND2 as the output signal PWM 2. The input end of the fourth inverter INV4 is connected to the input signal PWM _ IN, and the output end is connected to the other input end of the second NAND gate NAND 2. An input of the fifth inverter INV5 is connected to the output of the second NAND gate NAND2, and an output thereof is connected to an input of the third DELAY module DELAY 3. An input terminal of the sixth inverter INV6 is connected to the output of the fourth DELAY module DELAY4 and the capacitor C4, and an output terminal thereof is connected to an input terminal of the seventh inverter INV7 as the output signal NPWM 2. The input end of the seventh inverter INV7 is connected to the output end of the sixth inverter INV6, and the output end is the output signal NPWM 1. The input of the first DELAY block DELAY1 is connected to the output of the first NAND gate NAND1, and the output is connected to the input of the second DELAY block DELAY2 and the capacitor C1. An output of the second DELAY module DELAY2 is connected to an input terminal of the second inverter INV2 and one terminal of the capacitor C2. An input terminal of the third DELAY block DELAY3 is connected to an output terminal of the fifth inverter INV5, and an output terminal thereof is connected to an input terminal of the fourth DELAY block DELAY4 and the capacitor C3. An output of the fourth DELAY module DELAY4 is connected to an output terminal of the sixth inverter INV6 and the capacitor C4. The other ends of the capacitors C1, C2, C3 and C4 are all grounded.
FIG. 2 is a circuit diagram of a power stage topology of a hybrid boost converter according to the present invention, which includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, an inductor L, and a flying capacitor CFAn output capacitor COAnd a load resistor RO. The L current can not suddenly change by using the inductance of the energy storage element and the capacitance CFThe characteristic that the voltage can not be suddenly changed realizes the boosting from the input to the output. From the characteristics of the capacitance, the flying capacitance C can be derivedFThe voltage at both ends is input voltage VINThe voltage conversion ratio of the boost converter can meet the requirement of voltage second balance of the inductor
Figure BDA0003282989500000061
Where D is the control signal duty cycle. At duty cycle 0<D<At 1 time, there is CR>2。
The power stage topology provided by the invention has two working states, when the state is 1, the first NMOS tube MN1 is switched off, the second NMOS tube MN2 and the third NMOS tube MN3 are switched on, and the voltage of a switch node SW1 is input voltage V at the momentINThe switch node SW2 has a voltage of 0 and the current is fed from the inputThe current flows through the inductor L and the third NMOS transistor MN3 and then is conducted to the ground, and meanwhile, the current flows through the second NMOS transistor MN2 and the flying capacitor CFAnd a third NMOS transistor MN3 to ground. In this state, the inductor L and the capacitor CFAfter parallel connection, the input voltage is charged at the same time, and the current of the inductor L is increased linearly at the moment. In the state 2, the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, the first NMOS transistor MN1 is turned on, and the voltage of the switch node SW1 is the output voltage VOUTThe voltage at the switch node SW2 is the difference V between the output voltage and the input voltageOUT-VINThe current flows from the input through the inductor L and the flying capacitor CFAnd a first NMOS transistor MN1 to an output capacitor COAnd a load resistance RO. In this state, the inductor L and the capacitor CFDischarged after being connected in series and is an output capacitor COAnd a load resistance ROWhen power is supplied, the current of the inductor L is linearly reduced.
The flying capacitor C is known from the two working states of the power stage topologyFThe inductor L charges and discharges simultaneously, and the flying capacitor bears part of current in the process of discharging the load, so that the average current of the inductor is greatly reduced, the loss of the DCR is reduced, and the energy conversion efficiency is improved. In addition, the voltage swing of the switch nodes SW1 and SW2 is lower than that of CBC, so that the voltage stress of the power switch tube is correspondingly reduced, the switching loss of the power switch tube is reduced, and the energy conversion efficiency is further improved.
Fig. 3 is a waveform diagram illustrating the operation of the power stage topology of the hybrid boost converter according to the present invention. When the power stage topology is operating in state 1, the voltage at the first switching node SW1 is VINThe voltage at the second switch node SW2 is 0, and the voltage across the inductor L is VINInductor L current rises linearly, capacitor CFThe current gradually decreases, and the output current IOUTIs 0. When the power stage topology is operating in state 2, the voltage at the first switching node SW1 is VOUTThe voltage of the second switch node SW2 is VOUT-VINThe voltage across the inductor L is 2VIN-VOUTThe current of the inductor L decreases linearly and the capacitance C decreases linearlyFCurrent is equal to inductance current, and output current IOUTEqual to inductor L current。
Fig. 4 is a circuit diagram of an embodiment of the invention, including a power stage topology and a bootstrap driver circuit module. The power stage topology circuit diagram is the circuit diagram shown in fig. 2, and includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, an inductor L, and a flying capacitor CFAn output capacitor COAnd a load resistor RO. The bootstrap drive circuit module comprises three drive modules DRV1, DRV2 and DRV3, three potential translation modules LS1, LS2 and LS3, and two bootstrap capacitors CBoot1、CBoot2The power supply comprises a switch PMOS tube MSP1, a PMOS adjusting tube MSP2, a diode D1, an operational amplifier A1, feedback resistors R1 and R1 and a voltage source VREF1. The dead time generation circuit comprises seven inverters INV1, INV2, INV3, INV4, INV5, INV6 and INV7, two NAND gates 1 and NAND2, four DELAY modules DELAY1, DELAY2, DELAY3 and DELAY4 and four capacitors C1, C2, C3 and C4.
Specifically, the dead zone generation circuit module delays the output signal PWM _ IN through two branches, and the first NAND gate NAND1 and the second NAND gate NAND2 are used to generate dead zone time between the output signals PWM1 and NPWM1, and between the output signals PWM2 and NPWM2, so as to prevent the power switching tubes IN the power stage topology from being turned on simultaneously when the operating states are switched.
Specifically, the bootstrap driving module has a second bootstrap capacitor CBoot2The voltage on the second PMOS tube MSP2, an operational amplifier A1, resistors R1 and R2 and a voltage source VREF1The negative feedback loop is formed to control the charging of the first switch node SW1 through the forward biased diode D1 when the first NMOS transistor MN1 is turned on. Second bootstrap capacitor CBoot2The voltage on the second NMOS transistor MN2 is used as a power supply of the second driving module DRV2 to drive the second NMOS transistor MN2 to perform bootstrap driving. A first bootstrap capacitor CBoot1Controlled by a first PMOS transistor MSP1, and is provided with a second bootstrap capacitor CBoot2Charging is carried out, the upper voltage of the first driving module DRV1 is used as the power voltage of the first driving module DRV1, and the first NMOS transistor MN1 is driven, so that the bootstrap driving of the first NMOS transistor MN1 is realized. The bootstrap drive circuit has two operating states that cooperate with the two operating states of the power stage topology.
When the input control signal PWM1 is high, the power stage topology and the bootstrap drive module both operate in state 1. Since the first NMOS transistor MN1 is turned off, the first driving module DRV1 does not operate, and the first PMOS transistor MSP1 is turned on, the second bootstrap capacitor CBoot2Discharging, and using the first PMOS transistor MSP1 as a first bootstrap capacitor CBoot1And simultaneously supplies power to the second driving module DRV 2. The voltage at the first switching node SW1 in state 1 is equal to the input voltage VINDiode D1 is reverse biased to turn off, so that the current on second PMOS transistor MSP2 is zero. At the same time, the input voltage VINThe third driving module DRV3 is powered to drive the third NMOS transistor MN 3.
When the input control signal PWM1 is low, the power stage topology and the bootstrap drive module are both operating in state 2. Since the second NMOS transistor MN2 and the third NMOS transistor MN3 are turned off, the second driving module DRV2 and the third driving module DRV3 do not work, the first PMOS transistor MSP1 is turned off, and the first bootstrap capacitor C is turned onBoot1Discharged as power for the first driver module DRV 1. The voltage at the first switch node SW1 is V in State 2OUTThe diode D1 is forward biased to conduct, the first switch node SW1 passes through the diode D1, the second PMOS transistor MSP2, the operational amplifier A1, the resistors R1 and R2, and the voltage source VREF1The negative feedback loop controls the second bootstrap capacitor CBoot2And (6) charging. Voltage source VREF1Should be of a value of
Figure BDA0003282989500000081
A negative feedback loop connects the second bootstrap capacitor CBoot2The voltage at both ends is stabilized at VDRAs the supply voltage of the second driving module DRV2, and a first bootstrap capacitor CBoot1The charging voltage of (1).
FIG. 5 is a sequential logic diagram of an embodiment of the present invention. When the PWM1 is at a high level, the hybrid boost converter operates in the state 1, and at this time, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first PMOS transistor MSP1 are turned on, and the first NMOS transistor MN1 and the diode D1 are turned off. In this state, the voltage at the first switch node SW1 is VINThe voltage of the second switch node SW2 is 0, and the voltage of BST1 is VIN+VDRBST2 has a voltage VIN+VDRTG1 has a voltage of VINTG2 has a voltage of BST2 and BG1 has a voltage of VDRThe voltage of GP1 is VIN. When the PWM1 is at a low level, the hybrid boost converter operates in the state 2, at this time, the second NMOS transistor MN2, the third NMOS transistor MN3, and the first PMOS transistor MSP1 are turned off, and the first NMOS transistor MN1, the diode D1, and the second PMOS transistor MSP2 are turned on. In this state, the voltage at the first switch node SW1 is VOUTThe voltage of the second switch node SW2 is VOUT-VINAt this time, the voltage of BST1 is VOUT+VDRBST2 has a voltage VIN+VDRThe voltage of TG1 is BST1, and the voltage of TG2 is VINBG1 has a voltage of 0, GP1 has a voltage of BST 1.
From the above detailed description, it can be seen that: the hybrid boost converter combines a switched capacitor converter and a switched inductor converter, with a flying capacitor CFThe voltage swing of the switch node and the average current of the inductor are reduced, so that the switching loss of the power switch tube and the DCR loss of the inductor are reduced, and the energy conversion efficiency is improved. The efficiency comparison between the hybrid boost converter of the present invention and the conventional DC-DC boost converter is shown in fig. 6. Within the battery voltage input range, the efficiency of the hybrid boost converter is obviously improved compared with the efficiency of a CBC converter, and the efficiency is greatly improved when the hybrid boost converter is in heavy load. Meanwhile, the duty ratio of the control signal is increased by the hybrid converter, the voltage conversion ratio larger than 2 can be realized, and the hybrid converter is suitable for portable equipment and application under high frequency.

Claims (1)

1. A mixed mode boost converter suitable for battery voltage supply is characterized by comprising a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a flying capacitor CFInductor L and first output capacitor COLoad resistance ROOperational amplifier, PMOS switch tube, PMOS adjusting tube, first resistor R1, second resistor R2, first bootstrap capacitor CBoot1A second bootstrap capacitor CBoot2Voltage source VREFA diode, a first driving module DRV1, a second drivingA module DRV2, a third driving module DRV3, a first potential translation module LS1, a second potential translation module LS2, a third potential translation module LS3, a first PMOS transistor MSP1, a second PMOS transistor MSP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NAND1, a second NAND2, a first DELAY module DELAY1, a second DELAY module DELAY2, a third DELAY module DELAY3 and a fourth DELAY module DELAY 4;
wherein, the source of the first NMOS transistor MN1, the drain of the second NMOS transistor MN2 and the flying capacitor CFA gate of the first NMOS transistor MN1 is connected to the first driving signal TG1 outputted by the first driving module DRV1, a drain of the first NMOS transistor MN1 is an output terminal of the boost converter, and is connected to the output capacitor COAnd a load resistance ROA first output capacitor COAnd a load resistance ROThe other ends of the two are grounded; the source of the second NMOS transistor MN2 is connected to the input voltage VINMeanwhile, the gate of the second NMOS transistor MN2 is connected to the second driving signal output by the second driving module DRV 2; the source of the third NMOS transistor MN3 is grounded, the gate is connected to the third driving signal outputted by the third driving module DRV3, and the drain of the third NMOS transistor MN3 is connected to the other end of the inductor L and the flying capacitor CFThe other end of (a);
the inverting input terminal of the operational amplifier is connected to a voltage source VREFThe non-inverting input end of the operational amplifier is connected with one end of a first resistor R1 and one end of a second resistor R2, and the output of the operational amplifier is connected to the grid electrode of the PMOS adjusting tube; the source of the PMOS adjusting tube is connected with the cathode of the diode, the drain of the PMOS adjusting tube is connected with the other end of the first resistor R1 and the second bootstrap capacitor CBoot2And to the power supply terminal of the second driver module DRV 2; the other end of the second resistor R2 and a second bootstrap capacitor CBoot2And the other end of (V) and a voltage source VREFNegative poles of the two-phase current transformer are connected with an input voltage VIN；
The power supply terminal of the first driving module DRV1 is connected to the first bootstrap capacitor CBoot1The ground end is connected with the first NMOS tubeAn MN1 source, an input terminal of the first driving module DRV1 is connected to an output of the first level shift module LS1, and an output of the first driving module DRV1 is connected to a gate of the first NMOS transistor MN 1;
the power supply of the second driving module DRV2 is connected with the second bootstrap capacitor CBoot2The ground terminal is connected to the input voltage VINThe input end of the second driving module DRV2 is connected to the output of the second level shift module LS2, and the output of the second driving module DRV2 is connected to the gate of the second NMOS transistor MN 2;
the power supply terminal of the third driving module DRV3 is connected to the voltage VDRThe ground terminal is grounded, wherein VDRIs the driving voltage of the switching tube, when VINWhen less than 5V, VDR＝VIN(ii) a When V isINWhen greater than 5V, VDR5V; the input end of the third driving module DRV3 is connected to the output end of the second inverter INV2, and the output of the third driving module DRV3 is connected to the gate of the third NMOS transistor MN 3;
the input supply terminal of the first level shift module LS1 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the first level shift module LS1 is connected with the source electrode of the first NMOS transistor MN1, the input end of the first level shift module LS1 is connected with the output end of the seventh inverter INV7, and the output end of the first level shift module LS1 is connected with the input end of the first driving module DRV 1;
the input supply terminal of the second level shift module LS2 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the second driving module DRV1, and the output ground end of the second level shift module LS2 is connected with the input voltage VINThe input end of the second level shift module LS2 is connected to the output end of the second inverter, and the output end of the second level shift module LS2 is connected to the input end of the second driving module DRV 2;
the input supply terminal of the third level shift module LS3 is connected to VDRThe input ground end is grounded, the output power end is connected with the power end of the first driving module DRV1, the output ground end of the third potential translation module LS3 is connected with the source electrode of the first NMOS transistor MN1, the input end of the third potential translation module LS3 is connected with the output end of the third inverter INV3, and the third potential translation module LS3 is connected with the output end of the third inverter INV3The output end of the translation module LS3 is connected to the gate of the first PMOS transistor MSP 1;
a first bootstrap capacitor CBoot1The upper polar plate is connected with a power supply end of the first driving module DRV1, and the lower polar plate is connected with a source electrode of a first NMOS transistor MN 1;
second bootstrap capacitor CBoot2The upper plate is connected to the power supply terminal of the second driving module DRV1, the lower plate and the input voltage VINConnecting;
the source electrode of the PMOS switching tube is connected with the power supply end of the first driving module DRV1, the grid electrode of the PMOS switching tube is connected to the output of the third potential translation module LS3, and the drain electrode of the PMOS switching tube is connected with the power supply end of the second driving module DRV 1;
the anode of the diode is connected with the source electrode of a first NMOS transistor MN1, and the cathode of the diode is connected with the source electrode of a second PMOS transistor MSP 2;
one input end of the first NAND gate NAND1 is connected with the PWM signal, the other input end thereof is connected with the output end of the first inverter INV1, the output end of the first NAND gate NAND1 is connected with the input end of the first DELAY module DELAY1, and the input end of the first inverter INV1 is connected with the output end of the seventh inverter INV 7; the output end of the first DELAY module DELAY1 is connected with one end of a first capacitor C1 and the input end of a second DELAY module DELAY2, and the other end of the first capacitor C1 is grounded; the output end of the second DELAY module DELAY2 is connected to one end of the second capacitor C2 and the input end of the second inverter INV2, and the other end of the second capacitor C2 is grounded; the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with one input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected with the output end of the fourth inverter INV4, and the input end of the fourth inverter INV4 is connected with the PWM signal; the output end of the second NAND gate NAND2 is connected with the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of the third DELAY module DELAY3, the output end of the third DELAY module DELAY3 is connected with one end of the third capacitor C2 and the input end of the fourth DELAY module DELAY4, and the other end of the third capacitor C3 is grounded; the output end of the fourth DELAY module DELAY4 is connected to one end of the fourth capacitor C4 and the input end of the sixth inverter INV6, and the other end of the fourth capacitor C4 is grounded; an output of the sixth inverter INV6 is connected to an input of the seventh inverter INV 7.
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