CN113792520B - Layout wiring method, device, synchronous circuit and integrated circuit chip - Google Patents
Layout wiring method, device, synchronous circuit and integrated circuit chip Download PDFInfo
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Abstract
The application discloses a layout wiring method, a device, a synchronous circuit and an integrated circuit chip, wherein the method distributes a clock gating unit and a corresponding second register into a preset area of a layout based on physical constraint configured on the clock gating unit and the corresponding second register in advance in a layout stage; and then, performing clock tree comprehensive processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the difference of the clock path lengths of the clock gating unit and the first register. Therefore, the time sequence from the first register to the clock gating unit in the synchronous circuit can be effectively improved, and the time sequence convergence is facilitated.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a method and apparatus for layout and routing, a synchronization circuit, and an integrated circuit chip.
Background
With the development of very large scale integrated circuits, a clock gating unit (INTEGRATED CLOCK GATING) is usually added into a synchronous circuit in the design of low power consumption of a digital circuit to dynamically turn off the clock path of a later stage register so as to reduce the power consumption. However, with the increasing frequency and complexity of circuit operation, the difficulty of timing convergence of synchronous circuits is increasing, and particularly, a larger clock delay deviation (Clock Skew) exists between the front-stage register and the clock of the clock gating unit, so that the timing convergence of the front-stage register and the clock gating unit is difficult.
Disclosure of Invention
The embodiment of the application provides a layout wiring method, a layout wiring device, a synchronous circuit and an integrated circuit chip, which can effectively solve the technical problem of difficult timing sequence convergence between a pre-stage register and a clock gating unit.
In a first aspect, an embodiment of the present application provides a method for laying out and wiring a chip, where the chip includes a synchronization circuit, and the synchronization circuit includes: the clock signal processing device comprises a first register, a clock gating unit and a second register, wherein the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end. The method comprises the following steps:
Distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
And performing clock tree comprehensive processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the difference of the clock path lengths of the clock gating unit and the first register.
Further, the physical constraints are configured as follows:
determining the number of second registers connected with the clock gating unit and the layout area of a single second register;
Determining a dimension of the physical constraint based on the number and the layout area;
Based on the determined dimensions, physical constraints are configured for the clock gating cell and the corresponding second register.
Further, the determining the dimension of the physical constraint based on the number and the layout area includes:
obtaining a reference layout area according to the number and the layout area;
Multiplying the reference layout area by a preset coefficient to obtain the area of the preset area, and distributing the dimension of the physical constraint based on the area of the preset area, wherein the preset coefficient is larger than 1 and smaller than or equal to 2.
Further, the preset area is a square area.
In a second aspect, an embodiment of the present application further provides a device for placing and routing a chip, where the chip includes a synchronization circuit. The synchronization circuit includes: the clock signal processing device comprises a first register, a clock gating unit and a second register, wherein the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end. The device comprises:
The constraint module is used for distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and the clock tree synthesis module is used for carrying out clock tree synthesis processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the difference of the clock path lengths of the clock gating unit and the first register.
In a third aspect, an embodiment of the present application further provides a synchronization circuit, including:
a first register, a clock end connected with a source clock end of the synchronous circuit,
The clock gating unit is connected with the source clock end, and the enabling end is connected with the output end of the first register;
A second register, the clock end is connected with the output end of the clock gating unit and integrated with the clock gating unit in a preset area of the integrated circuit chip, and
And the multistage buffers are respectively inserted into the clock path of the first register and the clock path of the clock gating unit and are used for compensating the difference of the clock path lengths of the clock gating unit and the first register.
Further, the area of the preset area is a preset multiple of a reference layout area, wherein the reference layout area is an area required for layout of all second registers connected by the clock gating unit, and the preset multiple is greater than 1 and less than or equal to 2.
Further, the number of the second registers connected by the clock gating unit is greater than or equal to 1 and less than or equal to 100.
Further, the preset area is a square area.
In a fourth aspect, an embodiment of the present application further provides an integrated circuit chip, including the synchronization circuit described in the third aspect.
According to the chip layout wiring method provided by the embodiment of the application, physical constraints are set on the clock gating unit and the second register of the later stage in the layout stage, so that the physical distance between the clock gating unit and the later stage register is reduced, the insertion position of the buffer when the clock tree synthesis step is executed is changed, and the buffer which is originally inserted between the clock gating unit and the later stage register due to overlong wiring of the clock gating unit and the later stage register is inserted into the clock path of the clock gating unit. Therefore, the clock path lengths of the clock gating unit and the first register are similar while the clock arrival time of the first register and the clock arrival time of the second register are kept consistent, clock delay deviation between the clocks of the clock gating unit and the first register is reduced, and therefore the time sequence from the first register to the clock gating unit is effectively improved, and time sequence convergence is facilitated.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 shows a schematic diagram of an exemplary synchronization circuit;
FIG. 2 shows a schematic diagram of another exemplary synchronization circuit;
FIG. 3 shows a flow chart of a place and route method provided by an embodiment of the present description;
FIG. 4 shows a schematic diagram of a synchronization circuit provided by an embodiment of the present disclosure;
fig. 5 shows a block diagram of a layout wiring device provided by the embodiment of the present specification;
fig. 6 shows a schematic structural diagram of an integrated circuit chip according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In integrated circuit (INTEGRATED CIRCUIT, IC) chips, synchronization circuits, i.e., synchronous sequential logic circuits, are often used. To achieve low power design, a clock gating unit GCLK is typically inserted into the synchronous circuit, as shown in fig. 1, to turn off its clocks when the later registers DFF1, DFF2, and DFF3 are in an idle state, so as to reduce power consumption. However, a larger clock delay deviation exists between the front stage register DFF0 and the clock gating unit GCLK in the synchronous circuit, which results in timing problems, especially in time-series establishment, so that the timing convergence between the front stage register DFF0 and the clock gating unit GCLK is difficult.
The inventors have made long-term studies on the above problems, and have found that the physical distance between a clock gating cell and its succeeding register is generally relatively long after the layout in the layout wiring stage of a synchronous circuit. After clock tree synthesis, because the registers and the post-stage registers typically belong to the same clock domain, an electronic design tool such as EDA (Electronic Design Automation ) performs clock delay balancing (Clock Latency Balance) processing with the clock terminals of the pre-stage registers and the post-stage registers as sinks. Since the output end of the clock gating unit is physically far from the clock input end of the later stage register, a multi-stage Buffer (Buffer) is inserted between the output end of the clock gating unit and the clock input end of the later stage register by a tool to avoid the problems of long wires, etc., as shown in fig. 1, so that the clock stability is ensured and the clock arrival time of the earlier stage register DFF0 and the later stage registers DFF1, DFF2 and DFF3 is balanced. However, this results in relatively long clock paths of the front stage register DFF0 and the rear stage registers DFF1, DFF2 and DFF3, and relatively short clock paths of the clock gating unit GCLK, thereby causing a large clock delay deviation of clocks of the front stage register DFF0 and the clock gating unit GCLK, making timing convergence of the front stage register DFF0 to the clock gating unit GCLK difficult.
In this regard, the inventors consider setting timing constraints on the paths of the pre-stage register DFF0 and the clock gating unit GCLK, such as adding additional timing margin, or deliberately adding a negative delay to the clock of the clock gating unit GCLK during the layout phase, to optimize the pre-stage register DFF0 to clock gating unit GCLK timing. However, these are all limited in the ability to actually optimize timing from the standpoint of optimizing the data path.
In addition, the inventors have considered to delay the clocks of the clock gating units GCLK after the clock tree synthesis to reduce clock skew. However, it is found that the clock of the clock gating unit GCLK is delayed after the clock tree is synthesized, as shown in fig. 2, a buffer is inserted on the clock path of the clock gating unit GCLK, the clock is pushed backward, the clock delay deviation between the clocks of the front stage register DFF0 and the clock gating unit GCLK can be reduced, the timing problem from the front stage register DFF0 to the clock gating unit GCLK is optimized, but the clocks of the rear stage registers DFF1, DFF2 and DFF3 are equal in length to the clocks of the front stage register DFF0, the buffer is inserted on the clock path of the clock gating unit GCLK, the clock delay of the rear stage registers DFF1, DFF2 and DFF3 is increased, and one clock gating unit GCLK is usually connected with a plurality of rear stage registers, which also causes a lot of timing problems of the rear stage registers.
In view of this, the inventor proposes the technical solution provided in the embodiments of the present disclosure, by setting physical constraints on the clock gating unit and the post-stage register in the layout stage, the physical distance between the clock gating unit and the post-stage register is reduced, so that the insertion position of the buffer when the clock tree synthesis step is performed can be changed, and the buffer that would otherwise be inserted between the clock gating unit and the post-stage register due to the overlong wiring between the clock gating unit and the post-stage register is inserted on the clock path of the clock gating unit. Therefore, the clock path lengths of the clock gating unit and the front-stage register are similar while the clock arrival time of the front-stage register and the clock arrival time of the rear-stage register are kept consistent, clock delay deviation between clocks of the clock gating unit and the front-stage register is reduced, and therefore time sequence from the front-stage register to the clock gating unit is improved, and time sequence convergence is achieved.
Specific embodiments provided in the embodiments of the present specification are described in detail below.
The chip layout and wiring method provided by the embodiment of the specification is applied to the design of the back end of the integrated circuit, and the physical implementation of the synchronous circuit contained in the chip. Specifically, the synchronization circuit includes: a first register, a clock gating unit and a second register. The output end of the first register is connected with the clock end of the corresponding second register through the clock gating unit, and the clock end of the first register and the clock end of the clock gating unit are connected with the same source clock end. The first register is a front-stage register of the clock gating unit and is used for outputting an enabling signal of the clock gating unit; the second register is a later-stage register of the clock gating unit and is used for storing data or controlling a next-stage circuit; the clock gating unit is used for controlling clock input of the corresponding second register, and when the second register is in an idle state, the clock of the second register can be closed, so that redundant logic overturn of the second register during clock overturn is reduced, and power consumption is reduced. It should be noted that, in this embodiment, the number of clock gating units, first registers, and second registers included in the synchronization circuit is not limited, and each clock gating unit and corresponding first registers and second registers in the synchronization circuit may be physically implemented according to the layout wiring method shown in fig. 3.
Fig. 3 shows a flowchart of a layout wiring method provided in the embodiment of the present specification. As shown in fig. 3, the method includes:
step S301, allocating the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured in advance for the clock gating unit and the corresponding second register.
It will be appreciated that in the back-end design of an integrated circuit, the implementation of the circuit physical design is often referred to simply as place-and-route (P & R), which in turn includes a preparation stage, a placement stage, a clock tree synthesis stage, and a routing stage, etc., to physically implement the front-end supplied gate level netlist into a layout (layout). The layout stage is to assign physical locations to devices on the layout.
By configuring physical constraints (Bound) to the clock gating unit and the controlled second register in advance, when the layout step is executed in the layout stage, the clock gating unit and the controlled second register are placed in a preset area with a specified area and a specified shape based on the physical constraints, so that the clock gating unit and the controlled second register are close to each other, and the situation that a buffer needs to be inserted between the clock gating unit and the controlled second register to ensure clock stability due to overlong connection in the subsequent clock tree synthesis stage is avoided.
The preset area is the area corresponding to the configured physical constraint. For example, when configuring physical constraints, the constraint area may be set to be a square area with dimensions (Dimention) { a, b }, then the clock gating cell and the controlled second register are placed in a square area with width a and height b when laying out.
As shown in fig. 4, it is assumed that the synchronization circuit includes: first registers 100a, 100b, and 100c; combinational logic circuits 140a, 140b, and 140c; clock gating cells 110a, 110b, and 110c; second registers 121a, 122a, and 123a controlled by the clock gating unit 110 a; second registers 121b, 122b, and 123b controlled by the clock gating unit 110b, and second registers 121c, 122c, and 123c controlled by the clock gating unit 110 c. Then in the layout stage clock gating cell 110a and second registers 121a, 122a and 123a may be laid out in constrained square area a, clock gating cell 110B and second registers 121B, 122B and 123B in constrained square area B, and clock gating cell 110C and second registers 121C, 122C and 123C in constrained square area C. The dashed box area in fig. 4 represents a preset area.
It should be noted that, 3 clock gating units are listed in fig. 4, and each clock gating unit has 3 post-stage registers, which are only examples, and not limiting, the specific number of clock gating units and post-stage registers in the synchronous circuit needs to be determined according to the actual application scenario. In addition, the preset area may be an area of other shape besides the square area, and is not limited thereto.
In the implementation process, the dimension of the physical constraint determines the size of the preset area, and can be determined according to the number of the second registers corresponding to the clock gating unit and the layout area of each second register, so that the clock gating unit and the corresponding second registers can be placed enough, and meanwhile, the buffer is prevented from being inserted due to the fact that the distance between the clock gating unit and the second registers controlled by the clock gating unit is too far. The dimension of physical constraint is reasonably set, so that the density of local units can be effectively controlled, and the problem of difficult subsequent winding is avoided.
In an alternative embodiment, the process of configuring physical constraints may include: firstly, determining the number of second registers connected with a clock gating unit and the layout area of a single second register; then, determining the dimension of the physical constraint to be configured based on the determined number and layout area; physical constraints may then be configured for the clock gating cell and the corresponding second register based on the determined dimensions.
In an alternative embodiment, the determining the dimension of the physical constraint based on the determined number and the layout area may include: firstly, obtaining a reference layout area according to the determined quantity and the layout area; multiplying the reference layout area by a preset coefficient to obtain the area of the preset area, and distributing the dimension of the physical constraint based on the area of the preset area. The preset coefficients and the specific dimension allocation rules can be predetermined according to the layout rules of the integrated circuit and multiple tests.
It will be appreciated that the area of the predetermined area needs to be large enough, but not too large, so that a certain degree of expansion is required as the layout space and the wiring space of the clock gating unit based on the layout areas required by all the second registers corresponding to the clock gating unit. For example, the preset coefficient may take a value greater than 1 and less than or equal to 2, such as 1.5 or 2. When the preset coefficient is 2, the area of the preset area is twice the layout area required by all the second registers corresponding to the clock gating unit.
For example, assuming that a single second register requires a layout area of 1 square micron, a clock gating unit corresponds to 32 second registers, then at least 32 square microns are required to lay down the 32 second registers; further, when the preset coefficient is 2, the reference area is 64 square micrometers, and at this time, the dimension of the corresponding physical constraint may be set to {8,8}, in micrometers.
Or in other embodiments of the present description, other ways of determining the dimensions of the physical constraints may be employed. For example, the mapping relationship among the chip process, the number of the second registers, and the layout area of the single second register and the dimension of the physical constraint can be obtained in advance according to multiple experiments; in the specific implementation, according to the mapping relation, the corresponding physical constraint dimension is determined according to the actually adopted chip technology, the number of the second registers controlled by the clock gating unit and the layout area of the single second register.
In addition, it should be noted that, considering that the number of registers in the synchronous circuit is generally large, in order to avoid that the physical constraints on the clock gating unit and the post-stage registers may cause excessive local cell density and affect the subsequent wiring, the number of post-stage registers of each clock gating unit in the synchronous circuit designed according to the layout wiring method provided in the embodiment of the present disclosure cannot be too large. For example, the number of second registers connected per clock gating unit may be greater than or equal to 1 and less than or equal to 100, for example, may be 32, 64, 100, or the like.
After the layout stage is completed, step S302 may be performed to perform clock tree synthesis, so as to implement clock delay balancing.
In step S302, clock tree synthesis is performed on the first register, the clock gating unit, and the second register, so that the multi-stage buffers are respectively inserted into the clock paths of the clock gating unit and the timing paths of the first register to compensate for the difference between the clock paths of the clock gating unit and the first register.
The first register and the second register belong to the same clock domain, and the clocks of the first register and the second register need to be processed with equal length. Because the physical distance between the clock gating unit and the second register is short, the time delay caused by the short clock path can be ignored, and the stability of the clock can be ensured. Therefore, when clock tree synthesis is performed, the clock gating unit and the second register are regarded as a whole, so that a buffer is not inserted between the clock gating unit and the second register, but a multi-stage buffer is inserted between the first register and the source clock terminal, and the clock gating unit and the source clock terminal, so that the clock tree is constructed, and the clock gating unit and the first register clock path length are similar. As shown in fig. 4, after clock tree synthesis, the first registers 100a, 100b and 100c and the clock paths of the clock gating units 110a, 110b and 110c are respectively inserted with multi-stage buffers 130, while no buffers are inserted between the clock gating units 110a, 110b and 110c and the controlled second registers.
Therefore, clock delay balance of the first register and the second register can be realized, clock delay deviation between the clock gating unit and the first register can be reduced, and the time sequence from the first register to the clock gating unit is optimized, so that the time sequence convergence of the synchronous circuit is facilitated.
In addition, since the clock gating unit is generally used for controlling the plurality of second registers which are arranged in parallel, compared with the clock gating unit and the buffer inserted between each second register to realize the clock delay balance of the first register and the second register, the buffer inserted in the clock path of the clock gating unit can reduce the use quantity of the buffer, thereby being beneficial to improving the utilization rate of the IC chip and effectively reducing the manufacturing cost.
It should be noted that, in addition to the above steps S301 and S302, the whole layout and wiring flow of the synchronization circuit further includes other steps, such as a preparation step and a wiring step, and specific reference may be made to the related implementation details of the layout and wiring, which will not be described in detail in this embodiment.
In order to verify the time sequence improving effect of the technical scheme provided by the embodiment of the specification, under the condition that other experimental conditions are the same, time sequence simulation experiments are respectively carried out on the synchronous circuit layout obtained by setting physical constraint and not setting physical constraint, so that the influence of setting physical constraint on the time sequence from the first register to the clock gating unit is verified by comparing experimental results. The results of comparing the experimentally measured first register to clock gating cell timing are shown in table 1. It can be seen from table 1 that the time series WNS (Worst NEGATIVE SLACK), i.e., the worst slack value, decreases from-0.76 ns to-0.24 ns after the physical constraint is set, the number of timing violations (Violation number) decreases from 980 to 370, and the time series is significantly improved, compared to the case where the physical constraint is not set.
TABLE 1
| WNS(ns) | Violation number | |
| Not provided with Bound | -0.76 | 980 |
| Setting Bound | -0.24 | 370 |
In summary, in the layout and routing method provided in the embodiments of the present disclosure, physical constraints are set on the clock gating unit and the second register at the later stage in the layout stage, so that the buffer which is originally inserted between the clock gating unit and the later stage register due to overlong wiring between the clock gating unit and the later stage register is inserted into the clock path of the clock gating unit, thereby reducing clock delay deviation between clocks of the clock gating unit and the earlier stage register, being beneficial to improving the timing sequence from the earlier stage register to the clock gating unit, so as to achieve timing convergence, and reducing the number of buffers, thereby improving the utilization rate of the IC chip and effectively reducing the manufacturing cost.
Based on the same inventive concept, the embodiments of the present disclosure also provide a layout and routing device of a chip, which is applied to the physical implementation of the above-mentioned synchronization circuit included in the chip. As shown in fig. 5, the place and route device 50 includes:
A constraint module 501, configured to allocate the clock gating unit and the corresponding second register to a preset area of the layout based on a physical constraint configured in advance for the clock gating unit and the corresponding second register;
and the clock tree synthesis module 502 is configured to perform clock tree synthesis on the first register, the clock gating unit, and the second register, so that a multi-stage buffer is inserted into a timing path of the first register and a clock path of the clock gating unit respectively, so as to compensate a difference between clock path lengths of the clock gating unit and the first register.
In an alternative embodiment, the above-mentioned place-and-route device 50 further includes: a constraint configuration module comprising:
a parameter determining submodule, configured to determine the number of second registers connected to the clock gating unit and a layout area of a single second register;
A dimension determination submodule for determining a dimension of the physical constraint based on the number and the layout area;
and a configuration sub-module for configuring physical constraints on the clock gating unit and the corresponding second register based on the determined dimension.
In an alternative embodiment, the dimension determination submodule is configured to:
obtaining a reference layout area according to the number and the layout area;
Multiplying the reference layout area by a preset coefficient to obtain the area of the preset area, and distributing the dimension of the physical constraint based on the area of the preset area, wherein the preset coefficient is larger than 1 and smaller than or equal to 2.
In an alternative embodiment, the preset area is a square area.
It should be noted that, in the layout wiring device 50 provided in the embodiment of the present disclosure, the specific manner in which each module performs the operation has been described in detail in the above method embodiment, and will not be described in detail herein.
Based on the same inventive concept, the present embodiment also provides a synchronous circuit obtained by the layout wiring method provided by the above method embodiment. As shown in fig. 4, the synchronization circuit includes: a first register (e.g., 100a, 100b, and 100c shown in fig. 4), a clock gating unit (e.g., 110a, 110b, and 110c shown in fig. 4), a second register (e.g., 121a, 122a, 123a, 121b, 122b, 123b, 121c, 122c, and 123c shown in fig. 4), and a multi-stage buffer 130 inserted in the clock path of the first register and the clock path of the clock gating unit, respectively.
The clock terminal of the first register is connected to the source clock terminal CLK0 of the synchronizing circuit. The source clock terminal CLK0 may be a clock output terminal of a clock generation circuit inside the IC chip, or a clock may be provided outside the IC chip, and in this case, the source clock terminal CLK0 may be a clock input terminal of the IC chip.
The clock end of the clock gating unit is connected with the source clock end CLK0, and the enabling end is connected with the output end of the first register. An enable signal is output by the first register, enabling the clock gating unit to turn off the clock signal transmitted to the second register.
The output end of the clock gating unit is connected with the clock end of the controlled second register to control the clock input of the second register. The clock gating unit and the connected second register are integrated in a preset area of the IC chip, so that the physical distance between the clock gating unit and the second register is close enough, and the stability of clock transmission is ensured. In a specific implementation, the area of the preset area may be a preset multiple of the reference layout area, where the reference layout area is an area required by all the second registers connected by the layout clock gating unit, and the preset multiple is greater than 1 and less than or equal to 2. See in particular the description of the method embodiments described above.
In an alternative embodiment, to avoid local cell densities that are too high, the number of second registers connected per clock gating cell may be greater than or equal to 1 and less than or equal to 100, for example, 32, 64, 100, etc.
The multistage buffer is inserted into the clock path of the first register and the clock path of the clock gating unit to form a clock tree, so that the difference of the lengths of the clock paths between the clock gating unit and the first register can be effectively compensated while the clock arrival time of the first register and the clock arrival time of the second register are consistent, the clock delay deviation of the clock gating unit and the first register is reduced, and the time sequence convergence from the first register to the clock gating unit is facilitated.
It should be noted that, the synchronization circuit provided in the embodiment of the present disclosure may further include other circuit structures besides the first register, the clock gating unit, the second register, and the buffer, and is specifically designed according to the needs of the actual application scenario, which is not limited in this embodiment. For example, as shown in fig. 4, the synchronization circuit may further include a combinational logic circuit (such as 140a, 140b, and 140c shown in fig. 4), and the output terminal of the first register is connected to the enable terminal of the clock gating cell through the combinational logic circuit. The specific circuit structure of the combinational logic circuit can be set according to the requirements of practical application scenes, for example, the combinational logic circuit can be an adder, the enabling signal output by the first register and the other control signal are added to obtain a final enabling signal which is output to the enabling end of the clock gating unit,
Based on the same inventive concept, the present embodiment also provides an IC chip, and as shown in fig. 6, the IC chip 60 includes the above-described synchronization circuit 601. Note that the IC chip 60 may be any chip including the above-described synchronization circuit 601, such as a memory chip, which is not limited in this embodiment.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The term "plurality" means two or more, including two or more.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.
Claims (10)
1. A method of placing and routing a chip, the chip comprising a synchronization circuit, the synchronization circuit comprising: the method comprises the steps of connecting an output end of a first register with a corresponding clock end of a second register through a clock gating unit, and connecting the clock ends of the first register and the clock gating unit with the same source clock end, wherein the first register comprises a first clock, a clock gating unit and a second register, and the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end, and the method comprises the following steps:
Distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
And performing clock tree comprehensive processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the difference of the clock path lengths of the clock gating unit and the first register.
2. The place and route method of claim 1, wherein the physical constraints are configured as follows:
determining the number of second registers connected with the clock gating unit and the layout area of a single second register;
Determining a dimension of the physical constraint based on the number and the layout area;
Based on the determined dimensions, physical constraints are configured for the clock gating cell and the corresponding second register.
3. The place and route method of claim 2, wherein the determining the dimension of the physical constraint based on the number and the place and route area comprises:
obtaining a reference layout area according to the number and the layout area;
Multiplying the reference layout area by a preset coefficient to obtain the area of the preset area, and distributing the dimension of the physical constraint based on the area of the preset area, wherein the preset coefficient is larger than 1 and smaller than or equal to 2.
4. The place and route method according to claim 1, wherein the preset area is a square area.
5. A layout wiring device of a chip, wherein the chip includes a synchronization circuit, the synchronization circuit comprising: the device comprises a first register, a clock gating unit and a second register, wherein the output end of the first register is connected with the corresponding clock end of the second register through the clock gating unit, and the clock ends of the first register and the clock gating unit are connected with the same source clock end, and the device comprises:
The constraint module is used for distributing the clock gating unit and the corresponding second register to a preset area of the layout based on physical constraints configured on the clock gating unit and the corresponding second register in advance;
and the clock tree synthesis module is used for carrying out clock tree synthesis processing on the first register, the clock gating unit and the second register, so that a multi-stage buffer is respectively inserted into a time sequence path of the first register and a clock path of the clock gating unit to compensate the difference of the clock path lengths of the clock gating unit and the first register.
6. A synchronization circuit, comprising:
a first register, a clock end connected with a source clock end of the synchronous circuit,
The clock gating unit is connected with the source clock end, and the enabling end is connected with the output end of the first register;
A second register, the clock end is connected with the output end of the clock gating unit and integrated with the clock gating unit in a preset area of the integrated circuit chip, and
And the multistage buffers are respectively inserted into the clock path of the first register and the clock path of the clock gating unit and are used for compensating the difference of the clock path lengths of the clock gating unit and the first register.
7. The synchronization circuit of claim 6, wherein the area of the predetermined area is a predetermined multiple of a reference layout area, wherein the reference layout area is an area required to layout all second registers connected by the clock gating unit, and the predetermined multiple is greater than 1 and less than or equal to 2.
8. The synchronization circuit of claim 6, wherein the number of the second registers connected by the clock gating cell is greater than or equal to 1 and less than or equal to 100.
9. The synchronization circuit of claim 6, wherein the predetermined area is a square area.
10. An integrated circuit chip comprising the synchronization circuit of any one of claims 6-9.
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