CN113783800B

CN113783800B - Data packet processing method and device, computer equipment and readable storage medium

Info

Publication number: CN113783800B
Application number: CN202111323397.4A
Authority: CN
Inventors: 王云翔; 吴凤雏; 朱哲科
Original assignee: Hundsun Technologies Inc
Current assignee: Hundsun Technologies Inc
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2022-03-01
Anticipated expiration: 2041-11-10
Also published as: CN113783800A

Abstract

The application provides a data packet processing method, a data packet processing device, computer equipment and a readable storage medium, wherein the method comprises the following steps: acquiring a sequence number and an effective load length of a currently received data packet; determining whether to output the received data packet according to an expected sequence number and a sequence number of the received data packet; if the received data packet is determined not to be output, storing the received data packet into a target storage segment in a memory according to the storage capacity of the memory, the sequence number of the received data packet and the length of a payload; and if the received data packet is determined to be output, outputting the received data packet, and updating the expected sequence number according to the sequence number and the effective load length of the received data packet. The method can realize the out-of-order recombination of the data packets without adding an additional out-of-order parameter table, and avoids the occurrence of processing delay and the occupation of storage resources.

Description

Data packet processing method and device, computer equipment and readable storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method and an apparatus for processing a data packet, a computer device, and a readable storage medium.

Background

As a Programmable device, a Field Programmable Gate Array (FPGA) can implement various functions through programming. For example, the FPGA may replace the network card to implement the function of ethernet communication. As another example, FPGAs can implement richer functionality through the editing and processing of network data. In ethernet communication, many data are transmitted through a Transmission Control Protocol (TCP), and TCP data packets (hereinafter referred to as data packets) are ordered, but due to packet loss and retransmission caused by network environment factors, the sequence of receiving the data packets is disordered, or duplicate data packets or overlapped data packets are received. Therefore, when the FPGA implements a function related to packet processing, the FPGA is required to reassemble the received out-of-order packets into normal-order packets before performing subsequent data editing and processing.

In the prior art, when the FPGA performs out-of-order reassembly, the out-of-order data packets are stored in an internal Random Access Memory (RAM) of the FPGA, and an additional out-of-order parameter table is used to determine a reading order. The disorder parameter table records information such as the sequence number and length of each disorder data packet, and the address mapping of the data packet in the RAM. The out-of-order parameter table may be in the form of a linked list, a hash table, or a Content Addressable Memory (CAM).

However, with the prior art method, additional out-of-order parameter tables are required for data packet reassembly, and access to the out-of-order parameter tables increases additional processing delay, and the out-of-order parameter tables occupy larger storage resources.

Disclosure of Invention

An objective of the present application is to provide a method, an apparatus, a computer device and a readable storage medium for processing a data packet, so as to solve the problems of long processing delay and large resource occupation caused by using an out-of-order parameter table in the prior art.

In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

in a first aspect, the present application provides a data packet processing method, including:

acquiring a sequence number and an effective load length of a currently received data packet;

determining whether to output the received data packet according to an expected sequence number and the sequence number of the received data packet, wherein the expected sequence number is used for indicating the sequence number of the data packet to be output currently;

if the received data packet is determined not to be output, storing the received data packet into a target storage segment in a memory according to the storage capacity of the memory, the sequence number of the received data packet and the payload length, and updating the storage mark of each storage address in the target storage segment to be stored, wherein the number of the storage addresses of the target storage segment is the payload length;

and if the received data packet is determined to be output, outputting the received data packet, and updating the expected sequence number according to the sequence number and the effective load length of the received data packet to obtain a new expected sequence number.

In one possible implementation, the determining whether to output the received data packet according to the expected sequence number and the sequence number of the received data packet includes:

determining an actual difference between the expected sequence number and a sequence number of the received data packet;

if the actual difference value is equal to zero, determining to output the received data packet;

and if the actual difference value is smaller than zero, determining not to output the received data packet.

In one possible implementation, the method further includes:

if the actual difference is greater than zero and the actual difference is smaller than the payload length of the received data packet, outputting the data which is not output in the received data packet, and updating the expected sequence number to the sum of the sequence number of the received data packet and the payload length to obtain a new expected sequence number.

In one possible implementation manner, the storing the received packet into a target storage segment in the memory according to a storage capacity of the memory, a sequence number of the received packet, and a payload length includes:

determining a modulus result of the sequence number of the received data packet and the storage capacity of the memory to obtain a target storage starting address of the received data packet in the memory;

storing the received data packet into the target storage segment in the memory starting from the target storage start address.

In one possible implementation, the method further includes:

determining a starting address to be output according to the expected sequence number and the storage capacity of the memory;

determining whether to output data according to the storage mark of the initial address to be output;

if so, reading and outputting data in a continuous address field which is started by the starting address to be output and has stored storage marks, updating the storage marks of all storage addresses in the continuous address field to be not stored, and calculating the sum of the expected sequence number and the length of the continuous address field to obtain a new expected sequence number.

In a possible implementation manner, the determining whether to output data according to the storage flag of the start address to be output includes:

and if the storage mark of the initial address to be output is stored, determining to output data.

In a possible implementation manner, the reading and outputting data in a continuous address segment that starts with the start address to be output and has storage flags stored, and updating the storage flag of each storage address in the continuous address segment to be not stored includes:

reading data in an optional address field according to a preset bit width, wherein the length of the optional address field is a multiple of the preset bit width, and the optional address field comprises the continuous address field;

updating the storage mark of each storage address in the selectable address field in the memory to be not stored;

and screening the continuous address field from the selectable address field according to the read storage marks of the storage addresses in the selectable address field, and outputting the data in the continuous address field.

In a possible implementation manner, the screening the consecutive address segment from the selectable address segment according to the read storage flag of each storage address in the selectable address segment includes:

sequentially traversing the selectable address segments by taking the initial address to be output as an initial address until the storage mark of the traversed current address is not stored;

and taking an address field formed by the starting address to be output and the previous address of the current address as the continuous address field.

In a possible implementation manner, after the updating of the storage flag of each storage address in the optional address segment in the memory to be not stored, the method further includes:

determining addresses to be written back in the selectable address field according to the read storage marks of the storage addresses in the selectable address field;

writing data of the address to be written back into the address to be written back in the memory.

In a possible implementation manner, the determining, according to the read storage tag of each storage address in the optional address field, an address to be written back in the optional address field includes:

and if the storage address marked as not-stored exists in the selectable address field and the storage address of the storage address behind the storage address marked as not-stored is marked as stored, taking the storage address behind the storage address marked as not-stored as the address to be written back.

In a second aspect, the present application provides a packet processing apparatus, comprising:

the acquisition module is used for acquiring the sequence number and the effective load length of the currently received data packet;

a determining module, configured to determine whether to output the received data packet according to an expected sequence number and a sequence number of the received data packet, where the expected sequence number is used to indicate a sequence number of a data packet to be currently output;

a storage module, configured to, when it is determined that the received data packet is not output, store the received data packet into a target storage segment in the memory according to a storage capacity of the memory, a sequence number of the received data packet, and a payload length, and update a storage flag of each storage address in the target storage segment to be stored, where the number of the storage addresses of the target storage segment is the payload length;

and the transmission module is used for outputting the received data packet when the received data packet is determined to be output, and updating the expected sequence number according to the sequence number and the effective load length of the received data packet to obtain a new expected sequence number.

In a possible implementation manner, the determining module is specifically configured to:

In one possible implementation, the transmission module is further configured to:

In a possible implementation manner, the saving module is specifically configured to:

In one possible implementation, the determining module is further configured to:

In a third aspect, the present application provides a computer device comprising: a processor and a memory, the memory storing machine-readable instructions executable by the processor, the processor executing the machine-readable instructions when executed by a computer device to perform the steps of the data packet processing method according to the first aspect.

In a fourth aspect, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the packet processing method according to the first aspect.

The beneficial effect of this application includes:

based on the inherent relationship of the sequence number of the packet and the payload, the expected sequence number to be output can be derived. When a data packet is received, whether the data packet is output or not can be identified based on the comparison of the expected sequence number and the sequence number of the received data packet, if the data packet is not the data packet which is expected to be output, the target storage section of the data packet in the memory can be determined by using the capacity of the memory and the sequence number and the payload length of the received data packet, so that the sequential data packet can be rapidly and accurately read and output when the data packet is sequentially output. Through the process, the out-of-order recombination of the data packets can be realized without adding an additional out-of-order parameter table, the occurrence of processing delay and the occupation of storage resources are avoided, and meanwhile, the out-of-order recombination of the data packets can be realized by utilizing the process even when a plurality of TCP out-of-order holes exist in the data stream.

In addition, the method obtains the target storage starting address of the data packet in the RAM by utilizing the modulus of the serial number of the data packet to the capacity of the memory, sequentially stores the payload data of the data packet into the continuous address from the target storage starting address, and updates the storage marks of the addresses to be stored, so that the data reading can be completed quickly and accurately when the data packet is read from the RAM subsequently.

In addition, the storage starting address of the data packet needing to be output currently in the RAM can be obtained through the operation of the expected serial number and the storage capacity of the RAM, whether the data packet needing to be output currently is stored in the RAM or not can be obtained according to the storage mark of the storage starting address, if yes, the data packet needing to be output currently can be read from the RAM and output, and therefore the sequential output of the data packets is achieved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

FIG. 1 is an exemplary diagram of a TCP out-of-order hole;

FIG. 2 is a schematic diagram of a scenario in which an FPGA performs packet out-of-order reassembly;

FIG. 3 is a schematic diagram of another scenario in which an FPGA performs out-of-order packet reassembly;

FIG. 4 is an exemplary diagram of a module architecture for an FPGA;

fig. 5 is a schematic flowchart of a data packet processing method according to an embodiment of the present application;

FIG. 6 is a schematic illustration of storage;

fig. 7 is another schematic flow chart of a data packet processing method according to an embodiment of the present application;

fig. 8 is a schematic flowchart of a data packet processing method according to an embodiment of the present application;

FIG. 9 is an exemplary diagram of reading data according to a predetermined bit width;

fig. 10 is a block diagram of a packet processing apparatus according to the present application;

fig. 11 is a schematic structural diagram of a computer device 110 according to an embodiment of the present application.

Detailed Description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

In order to enable those skilled in the art to use the present disclosure, the following embodiments are given in conjunction with a specific application scenario "TCP packet out-of-order reassembly for FPGAs". It will be apparent to those skilled in the art that the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Although the present application is described primarily in the context of out-of-order reassembly of TCP packets by an FPGA, it should be understood that this is merely one exemplary embodiment.

It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.

When the existing FPGA carries out TCP data packet out-of-order recombination, the data packet recombination needs to be carried out by depending on an additional out-of-order parameter table, the access to the out-of-order parameter table can increase additional processing time delay, and meanwhile, the out-of-order parameter table can occupy larger storage resources.

In addition, using existing TCP packet out-of-order reassembly methods, only one TCP out-of-order hole may be supported. The TCP out-of-order hole refers to a continuous missing part in a TCP data stream. Fig. 1 is an exemplary diagram of TCP out-of-order holes, and as shown in the figure, the FPGA has currently received the 1 st, 2 nd, 4 th, 8 th, 9 th and 12 th TCP packets, and has lost the 3 rd, 5 th, 6 th, 7 th, 10 th and 11 th TCP packets, it indicates that three TCP out-of-order holes, which are 3, 5-7 and 10-11 respectively, currently exist.

Based on the above problems, embodiments of the present application provide a data packet processing method, which may determine whether to directly output a data packet or to temporarily store the data packet in a corresponding address of a memory by using an inherent relationship between sequence numbers of sequential data packets, and read and output the data packet from the corresponding address by using a relationship between a storage address and a sequence number, so that out-of-order reassembly of the data packet may be achieved without adding an additional out-of-order parameter table, occurrence of processing delay and occupation of storage resources are avoided, and meanwhile, the method may further support multiple TCP out-of-order holes.

The embodiment of the application can be applied to a scene of the disordered recombination of the TCP data packets of the FPGA, however, the application is not limited to this, the application can also be applied to other devices or equipment, and the processed data packets can also be other data packets besides the TCP data packets. For convenience of description, the following embodiments of the present application all explain the TCP packet out-of-order reassembly of the FPGA as an example, and in the following embodiments, the TCP packet out-of-order reassembly of the FPGA is simply referred to as the data packet out-of-order reassembly of the FPGA.

First, a scenario in which the FPGA reassembles packets out of order will be described below.

Fig. 2 is a schematic view of a scenario in which an FPGA performs packet out-of-order reassembly, and as shown in fig. 2, the FPGA may serve as a TCP endpoint, establish a TCP connection with a previous TCP endpoint, receive a data packet from the previous TCP endpoint, reassemble the received out-of-order data packet into a data packet in a normal order, and send the data packet in the normal order to subsequent other modules or other devices.

Fig. 3 is another schematic view of a scenario in which the FPGA performs packet out-of-order reassembly, and as shown in fig. 3, a TCP connection is established between a TCP endpoint a and a TCP endpoint B and data packet transmission is performed. The FPGA can be used as an interception device for intercepting uplink data and downlink data between the TCP endpoint A and the TCP endpoint B. In this scenario, the FPGA may not establish a connection with the TCP endpoint a and the TCP endpoint B, but only reassemble the received out-of-order data packets into normal-order data packets, and send the normal-order data packets to other modules or other devices for subsequent processing.

It should be noted that fig. 2 and fig. 3 are only examples, and in an implementation, the FPGA may establish a connection with multiple TCP endpoints at the same time, or listen to data of multiple links at the same time.

Optionally, a plurality of modules may be arranged in the FPGA, and the modules cooperate with each other to complete out-of-order reassembly of the data packets. Fig. 4 is an exemplary diagram of a module architecture of an FPGA, and as shown in fig. 4, the FPGA may include: the device comprises a preprocessing module, an output module, a storage module and a loading module. Optionally, the preprocessing module, the output module, the storage module and the loading module may be software modules, and each module may be executed independently and in parallel. Optionally, the preprocessing module is configured to receive the data packet, and determine that the data packet needs to be directly output by the output module or stored in the RAM of the FPGA by the storage module. The storage module is used for determining the storage position of the data packet in the RAM and storing the data packet to the storage position. The loading module is used for confirming whether a data packet needing to be output exists in the current RAM, and reading the data packet needing to be output from the RAM and sending the data packet to the output module when the data packet needing to be output exists. The output module is used for sending the data packet which is judged by the preprocessing module and needs to be directly output and the data packet read by the loading module from the RAM to the output port of the FPGA for output.

It should be understood that the above module division is only an example, and the following embodiments correspondingly explain the technical solution of the present application in the above module manner, however, this is not a limitation to the present application, and the present application may also use other module division manners or implement the technical solution of the present application uniformly by one process or module in the FPGA without module division.

Fig. 5 is a schematic flow chart of a data packet processing method according to an embodiment of the present disclosure, and an execution subject of the method may be the FPGA described above, but is not limited thereto. As shown in fig. 5, the method includes:

s501, acquiring a sequence number and a payload length of a currently received data packet.

Illustratively, the pre-processing module receives a data packet from a previous TCP endpoint, and accordingly, the pre-processing module parses the data packet to parse a sequence number and a payload (payload) length of the data packet. When data packets are communicated between devices or modules based on a particular communication protocol, the format of the data packets follows the specifications of the communication protocol. Thus, the pre-processing module can parse out the sequence number and payload length in the packet based on the specification of the protocol.

The payload length may refer to a byte length occupied by a payload in a data packet.

S502, determining whether to output the received data packet according to an expected sequence number and the sequence number of the received data packet, wherein the expected sequence number is used for indicating the sequence number of the data packet to be output currently.

Optionally, there is an inherent relationship between the sequence number of the packet and the payload. For example, taking TCP packets as an example, the sequence numbers of the packets have continuity with respect to the payload. Specifically, in two adjacent data packets, the sequence number of the next data packet is equal to the sum of the sequence number of the previous data packet and the payload length of the previous data packet. Based on this feature of the data packet, the FPGA can calculate the sequence number of the next data packet to be output, i.e. the expected sequence number mentioned above, every time one data packet is output. Furthermore, when a data packet is received, based on the expected sequence number and the sequence number of the received data packet, it is determined that the received data packet is a sequential data packet and needs to be directly output, or the received data packet is an out-of-order data packet and needs to be stored in the RAM to be sequentially output.

Illustratively, the pre-processing module determines that a first data packet needs to be directly output by the data module after receiving the first data packet, and initializes the expected sequence number to the sum of the sequence number and the payload length of the first data packet. Meanwhile, the preprocessing module may set the direct _ output _ flag of the direct output flag to 1, which indicates that the current data packet needs to be directly output. It should be noted that, each module in the FPGA may run in parallel according to the same clock cycle, and in each clock cycle, each module may respectively read or set the flag including the direct _ output _ flag to perform a corresponding operation. Specifically, after the preprocessing module sets the direct _ output _ flag as 1, the output module reads that the value of the direct _ output _ flag is 1, and the output module is triggered to directly send the first data packet to the output port of the FPGA for output.

After the first data packet is sent, the expected sequence number has an initial value, and after that, each time a data packet is received, the preprocessing module may determine that the currently received data packet needs to be directly output or temporarily stored in the RAM based on the current expected sequence number and the sequence number of the received data packet.

And S503, if the received data packet is determined not to be output, storing the received data packet into a target storage segment in the memory according to the storage capacity of the memory, the sequence number of the received data packet and the payload length, and updating the storage mark of each storage address in the target storage segment to be stored, wherein the number of the storage addresses of the target storage segment is the payload length.

The memory may be referred to as a RAM, and the storage capacity of the memory may be read in advance.

If it is determined that the received data packet is not output, indicating that the received data packet needs to be temporarily stored in the RAM, the storage module may store the received data packet in the target storage segment based on the storage capacity of the memory and the sequence number and payload length of the received data packet. That is, the target storage segment is determined by the capacity of the memory, the sequence number of the received data packet and the length of the payload, so that the FPGA can quickly and accurately read and output the sequential data packets when sequentially outputting the data packets.

In addition, each memory address in the RAM may have a storage flag, and the value of the storage flag may be stored or not stored, when a certain memory address stores data, the storage flag of the memory address is updated to be stored, and when the data of the certain memory address does not store data or after the data is read, the storage flag of the memory address is updated to be not stored.

For example, a memory address in the present application may include a byte, where the byte includes 9 bits, 8 bits of the byte are data, and 1 bit is a memory tag.

S504, if the received data packet is determined to be output, the received data packet is output, and the expected sequence number is updated according to the sequence number and the effective load length of the received data packet to obtain a new expected sequence number.

Taking TCP packets as an example, the sum of the sequence number of the received packet and the payload length may be used as a new expected sequence number.

If the received data packet is determined to be output, the output module is required to directly output the received data packet. Illustratively, the preprocessing module sets a direct _ output _ flag as 1, and the output module reads that the value of the direct _ output _ flag is 1, and triggers the output module to directly send the received data packet to the output port of the FPGA for output.

In addition, when the received packet is output and then becomes the currently output packet, the result of adding the sequence number of the packet and the payload length is used as a new expected sequence number, that is, the sequence number of the next output packet should be the expected sequence number, and when the packet is received again, it is determined whether the received packet is a packet expected to need to be output based on the judgment in the step S502, and based on this, the reassembly and the sequential transmission of the out-of-order packet can be realized.

In this embodiment, the expected sequence number to be output may be obtained based on the inherent relationship between the sequence number of the packet and the payload. When a data packet is received, whether the data packet is output or not can be identified based on the comparison of the expected sequence number and the sequence number of the received data packet, if the data packet is not the data packet which is expected to be output, the target storage section of the data packet in the memory can be determined by using the capacity of the memory and the sequence number and the payload length of the received data packet, so that the sequential data packet can be rapidly and accurately read and output when the data packet is sequentially output. Through the process, the out-of-order recombination of the data packets can be realized without adding an additional out-of-order parameter table, the occurrence of processing delay and the occupation of storage resources are avoided, and meanwhile, the out-of-order recombination of the data packets can be realized by utilizing the process even when a plurality of TCP out-of-order holes exist in the data stream.

As an alternative implementation, the step S501 may include:

determining an actual difference between the expected sequence number and the sequence number of the received packet; if the actual difference value is equal to zero, determining to output the received data packet; and if the actual difference value is smaller than zero, determining not to output the received data packet.

For example, assuming that the expected sequence number is e _ seq, the sequence number of the received packet is r _ seq, the payload length is r _ len, and the difference between the e _ seq and the r _ seq is diff, the preprocessing module may first convert the diff into a 32-bit signed integer s _ diff, and may make the following determination.

If s _ diff is equal to 0, it indicates that the sequence number of the received packet is an expected sequence number, and therefore, the received packet is a packet that needs to be currently output, so the preprocessing module may set the direct _ output _ flag of the direct output flag to 1, when the output module reads that the direct _ output _ flag is 1, the received packet is sent to an output port of the FPGA to be output, and the output module updates the value of the expected sequence number to e _ seq = r _ seq + r _ len.

If s _ diff is less than 0, it indicates that the sequence number of the received packet is after the expected sequence number, i.e. the received packet is an out-of-order packet, and therefore, it is determined that the received packet is not to be output but needs to be temporarily stored in the RAM. The preprocessing module may set a RAM save flag RAM _ save to 1, indicating that the received data packet needs to be temporarily stored in the RAM. Accordingly, the storage module reads that RAM _ save is 1, and may store the received data packet in the target address field of the RAM according to the foregoing process of step S503.

In addition to the above two cases, the following two cases may be included:

in the first case, the actual difference is greater than zero, and the actual difference is greater than or equal to the payload length of the received packet, i.e., s _ diff > 0, and r _ len < = s _ diff, in which case it indicates that the payloads of the received packets have all been output, i.e., the received packets are duplicate packets, and therefore, the received packets can be directly discarded.

In the second case, the above actual difference is larger than zero, and the actual difference is smaller than the payload length of the received packet, i.e., s _ diff > 0, and r _ len > s _ diff, in this case, it indicates that a part of the payload of the received packet has been output and another part of the payload has not been output, and the received packet is a sequential packet, and thus, the non-output part of the received packet can be directly output. Optionally, the data that is not output in the received data packet may be output, and the expected sequence number is updated to the sum of the sequence number of the received data packet and the payload length, so as to obtain a new expected sequence number.

For example, the preprocessing module may set the direct _ output _ flag to 1 and set the partial output flag direct _ output _ part to 1, indicating that an un-output part in the received packet needs to be output, and the output module reads that the direct _ output _ flag is 1 and the direct _ output _ part is 1, outputs the un-output part in the received packet, and updates the value of the expected sequence number to e _ seq = r _ seq + r _ len by the output module.

As an alternative implementation, the step S503 includes:

determining a modulus result of the sequence number of the received data packet and the storage capacity of the memory to obtain a target storage starting address of the received data packet in the memory; and storing the received data packet into the target storage segment which takes the target storage starting address as the start in the memory.

For example, it is assumed that the sequence number of the received packet is r _ seq, the payload length is r _ len, the storage capacity of the memory is M, and the target storage start address is s _ index. When reading that ram _ save is 1, the storage module first calculates a modulo result of r _ seq on M to obtain s _ index, specifically, s _ index = r _ req% M. After s _ index is calculated, payload data of the length of r _ len is sequentially stored in consecutive addresses of addresses s _ index to s _ index + r _ len, and the storage flags of addresses s _ index to s _ index + r _ len are updated to be stored.

For example, assuming that M =1024, e _ seq = 4108, s _ seq = 4121, s _ len =10, s _ index =% M = 25, that is, the target storage start address of the packet in the RAM is 25, and the stored address length is 10. Fig. 6 is a schematic diagram of storage, and as shown in fig. 6, the data packet is stored in the RAM at the shaded portion of the address, i.e. the addresses from 25 to 34.

In this embodiment, the serial number of the data packet is used to modulo the capacity of the memory to obtain the target storage start address of the data packet in the RAM, the payload data of the data packet is sequentially stored into the continuous address from the target storage start address, and the storage marks of the addresses are updated to be stored.

In parallel with the above processing procedure, the FPGA may also monitor e _ seq in real time to determine whether there is a data packet in the RAM that needs to be output sequentially, so that the data packet buffered in the RAM can be output sequentially. This process is explained in detail below.

Fig. 7 is another schematic flow chart of a data packet processing method according to an embodiment of the present application, and as shown in fig. 7, the method further includes:

s701, determining a starting address to be output according to the expected sequence number and the storage capacity of the memory.

It is worth noting that the present embodiment may be executed in parallel with the foregoing embodiments. Illustratively, the process of the present embodiment is performed by the load module every clock cycle so that the data packets in the RAM can be sequentially output.

As described above, when the storage module stores the data packet, the storage module may obtain the target storage start address of the data packet in the RAM by taking the module between the sequence number of the data packet and the storage capacity of the memory, and therefore, for each data packet stored in the RAM, the storage start address is determined by the sequence number and the storage capacity of the memory. Based on this, in this step, the loading module may obtain a to-be-output start address of the data packet that should be currently output in the RAM based on the expected sequence number and the storage capacity of the memory.

Specifically, the expected sequence number is modulo with the storage capacity, and the obtained value is the to-be-output start address of the data packet which should be output currently in the RAM.

The expected sequence number represents the sequence number of the data packet which should be output currently, and since the storage start address is obtained by calculation based on the sequence number and the storage capacity of the RAM when the data packet is stored in the RAM, the storage start address in the RAM, that is, the to-be-output start address, can be obtained by calculation based on the sequence number, that is, the expected sequence number, and the storage capacity of the RAM for the data packet which needs to be output currently.

S702, determining whether to output data according to the storage mark of the initial address to be output.

In one case, if the storage flag of the start address to be output is stored, the output data may be determined.

Specifically, if the storage flag of the start address to be output is stored, it indicates that the packet to be output currently is already stored in the RAM, and therefore, the packet can be output through the following step S703.

In another case, if the storage flag of the start address to be output is not stored, no processing is performed.

Specifically, if the storage flag of the start address to be output is not stored, it indicates that the data packet to be output is not stored in the RAM, and needs to continue to wait until the next clock cycle, and recalculate according to the new expected sequence number.

And S703, if yes, reading and outputting the data in the continuous address field which takes the initial address to be output as the initial address and the storage marks of which are all stored, updating the storage marks of the storage addresses in the continuous address field to be not stored, and calculating the sum of the expected sequence number and the length of the continuous address field to obtain a new expected sequence number.

For example, the loading module sequentially reads data in subsequent addresses from the start address to be output until the storage flag of a certain address is not stored, and then takes an address segment between the previous address of the address and the start address to be output as a continuous address segment, and updates the storage flag of each storage address in the continuous address segment to be not stored, wherein the storage flag of each storage address in the continuous address segment is updated to be not stored, so that the memory can be recycled. After the loading module reads the data of the continuous address field, setting an RAM output flag RAM _ output _ flag to 1, which indicates that the data packet in the RAM needs to be output. And when the output module reads that RAM _ output _ flag is 1, correspondingly sending the data of the continuous address field read from the RAM to an output port of the FPGA for outputting.

In this embodiment, the storage start address of the data packet that needs to be output currently in the RAM can be obtained through the operation of the expected sequence number and the storage capacity of the RAM, whether the data packet that needs to be output currently is stored in the RAM can be obtained according to the storage flag of the storage start address, and if yes, the data packet that needs to be output currently can be read from the RAM and output, so that the sequential output of the data packets is realized.

Fig. 8 is a schematic flowchart of another flow of the data packet processing method according to the embodiment of the present application, and as shown in fig. 8, as an optional implementation manner, an optional manner of the step S703 includes:

s801, reading data in an optional address section according to a preset bit width, wherein the length of the optional address section is a multiple of the preset bit width, and the optional address section comprises the continuous address section.

In a specific implementation, when reading a data packet from the RAM, the data packet may not be read individually, but read in batches according to a certain bit width. For example, the bit width of the FPGA may be set to 4 bytes, in which case the load module will read 4 addresses of data at a time.

The data read according to the preset bit width may only include the data of the continuous address field, and may also include data other than the continuous address field.

S802, the storage mark of each storage address in the selectable address field in the memory is updated to be not stored.

Since the RAM needs to be recycled, the address of the read data needs to be cleared after the data is read in the RAM. If the technical scheme of the application is applied to equipment such as a CPU (central processing unit), the operation method is very clear and simple. For example, the CPU may perform a read operation on an address, then perform a flush operation, and then read data of a next address. For the FPGA, the CPU cannot be operated without doubling the operating frequency, or else, the pipeline processing cannot be realized. However, in order to implement the pipelined processing, it is necessary to clear the flag bit corresponding to the data while reading the data, that is, to update the storage flag of the address where the data is located to be not stored.

And S803, screening the continuous address field from the selectable address field according to the read storage marks of the storage addresses in the selectable address field, and outputting the data in the continuous address field.

In one case, if the data read according to the preset bit width only includes the data of the consecutive address field, the data can be directly output by the output module.

In another case, the data read according to the preset bit width may include data other than the above-mentioned consecutive address field, and the processing may be performed according to the following procedure.

Optionally, with the initial address to be output as a start, sequentially traversing the selectable address segments until the storage mark of the traversed current address is not stored; and taking an address field formed by the initial address to be output and the previous address of the current address as the continuous address field.

By using the storage mark, the data of the continuous address field can be screened from the selectable address field and output, so that the output of data except the data packet which needs to be output currently can be avoided.

As described above, in order to implement pipelining, the FPGA needs to update the storage flag of the address where the data is located to be not stored while reading the data, however, the FPGA may read the data in batches according to a preset bit width, that is, the data read at a certain time may include data outside the consecutive address segment, that is, data that does not need to be output, in this case, the storage flag of the address where some data that does not need to be output may be updated incorrectly, and the FPGA cannot know whether there is such an error within one clock cycle, which may cause a subsequent data reading error.

For example, fig. 9 is an exemplary diagram of reading data according to a preset bit width, as shown in fig. 9, data in the RAM has a hole 33-34, and when reading the data of 28-31, the storage flag can be updated normally, but when reading the data of 32-35 and updating the storage flag, the data of 35 is read out and the storage flag is updated to be not stored, and the data of 35 should not be output at this time, which results in data loss and subsequent data reading error.

In order to solve the problem, the application provides a write-back mechanism, which judges that the addresses of the storage marks are updated by errors in the subsequent cycle of the current cycle, and writes back the storage data and the storage marks of the addresses, so that the storage data and the storage marks of the addresses can be recovered, thereby avoiding the occurrence of data reading errors. The specific scheme is as follows.

Optionally, after step S802, the method further includes:

determining addresses to be written back in the selectable address field according to the read storage marks of the storage addresses in the selectable address field; and writing the data of the address to be written back into the address to be written back in the memory. And the storage mark of the address to be written back can be updated to be stored.

Optionally, this embodiment may be executed in a target clock cycle after the clock cycle when the step S802 is executed, where the target clock cycle may be, for example, a second clock cycle after the clock cycle when the step S802 is executed later. In the target clock cycle, the FPGA may write back the storage tag and the data that are originally updated by error through the processing procedure of this embodiment.

Optionally, if a storage address marked as not-stored exists in the optional address field, and a storage address of a storage address behind the storage address marked as not-stored is marked as stored, taking the storage address behind the storage address marked as not-stored as the address to be written back.

It should be understood that the data to be judged in this embodiment refers to data read from the foregoing storage address, and the storage flag corresponding to these data is not updated, so that the judgment can be performed by using the storage flag therein.

Specifically, if a storage address marked as not stored exists in the optional address field, and a storage mark of a storage address subsequent to the storage address marked as not stored is marked as stored, it is indicated that a hole exists in the optional address field, and the storage mark of the storage address subsequent to the hole is updated by an error, so that the address subsequent to the hole can be used as an address to be written back, data of the address to be written back is written into the address to be written back in the memory, and the storage mark is updated to be stored, so that the data of the address in which the data is updated by the error can be recovered.

Continuing with the example of fig. 2, after the data of the segments 32-35 is read according to the preset bit width and the storage flag is modified to be not stored, the data on the segment 35 can be known as the address to be written back by the judgment processing. Further, the data read from 35 may be written back to 35, and the storage flag of 35 may be updated to be stored, thereby achieving recovery of the data.

Based on the same inventive concept, the embodiment of the present application further provides a data packet processing apparatus corresponding to the data packet processing method, and since the principle of the apparatus in the embodiment of the present application for solving the problem is similar to the data packet processing method in the embodiment of the present application, the implementation of the apparatus may refer to the implementation of the method, and repeated details are not described again.

Fig. 10 is a block diagram of a packet processing apparatus according to the present application, and as shown in fig. 10, the apparatus includes:

an obtaining module 1001 is configured to obtain a sequence number and a payload length of a currently received data packet.

A determining module 1002, configured to determine whether to output the received data packet according to an expected sequence number and a sequence number of the received data packet, where the expected sequence number is used to indicate a sequence number of a data packet to be currently output.

A saving module 1003, configured to, when it is determined that the received data packet is not output, store the received data packet into a target storage segment in the memory according to a storage capacity of the memory, a sequence number of the received data packet, and a payload length, and update a storage flag of each storage address in the target storage segment to be stored, where the number of the storage addresses of the target storage segment is the payload length.

A transmission module 1004, configured to output the received data packet if it is determined that the received data packet is output, and update the expected sequence number according to the sequence number and the payload length of the received data packet, so as to obtain a new expected sequence number.

As an optional implementation manner, the determining module 1002 is specifically configured to:

and if the actual difference value is equal to zero, determining to output the received data packet.

As an optional implementation, the transmission module 1004 is further configured to:

As an optional implementation manner, the saving module 1003 is specifically configured to:

and determining a modulus result of the sequence number of the received data packet and the storage capacity of the memory to obtain a target storage starting address of the received data packet in the memory.

As an optional implementation, the determining module 1002 is further configured to:

and determining a starting address to be output according to the expected sequence number and the storage capacity of the memory.

And determining whether to output data or not according to the storage mark of the initial address to be output.

and reading data in an optional address field according to a preset bit width, wherein the length of the optional address field is a multiple of the preset bit width, and the optional address field comprises the continuous address field.

And updating the storage mark of each storage address in the selectable address section in the memory to be not stored.

and sequentially traversing the selectable address segments by taking the initial address to be output as the initial address until the storage mark of the traversed current address is not stored.

and determining the address to be written back in the selectable address field according to the read storage marks of the storage addresses in the selectable address field.

The description of the processing flow of each module in the device and the interaction flow between the modules may refer to the related description in the above method embodiments, and will not be described in detail here.

An embodiment of the present application further provides a computer device 110, as shown in fig. 11, which is a schematic structural diagram of the computer device 110 provided in the embodiment of the present application, and includes: a processor 111, a memory 112, and optionally a bus 113. The memory 112 stores machine-readable instructions (e.g., corresponding execution instructions of the obtaining module, the determining module, the saving module, and the transmitting module in the apparatus in fig. 10, etc.) executable by the processor 111, when the computer device 110 runs, the processor 111 communicates with the memory 112 through the bus 113, and the machine-readable instructions are executed by the processor 111 to perform the method steps in the foregoing method embodiments.

The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program executes the steps of the data packet processing method.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to corresponding processes in the method embodiments, and are not described in detail in this application. In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and there may be other divisions in actual implementation, and for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.

Claims

1. A data packet processing method is applied to the field of transmission control protocol data packets, and comprises the following steps:

if the received data packet is determined to be output, outputting the received data packet, and updating the expected sequence number according to the sequence number and the effective load length of the received data packet to obtain a new expected sequence number;

wherein the storing the received packet into a target memory segment in the memory according to a storage capacity of the memory, a sequence number of the received packet, and a payload length comprises:

storing the received data packet into the target storage segment in the memory starting from the target storage starting address;

wherein the method further comprises:

2. The method of claim 1, wherein determining whether to output the received packet based on the expected sequence number and the sequence number of the received packet comprises:

3. The method of claim 2, further comprising:

4. The method of claim 1, wherein the determining whether to output data according to the storage flag of the start address to be output comprises:

5. The method of claim 1, wherein reading and outputting data in a continuous address segment starting from the start address to be output and having storage tags stored, and updating the storage tag of each storage address in the continuous address segment to be not stored comprises:

6. The method as claimed in claim 5, wherein the step of screening the consecutive address segments from the selectable address segment according to the read storage marks of the storage addresses in the selectable address segment comprises:

7. The method of claim 5, wherein after the updating the storage flag of each storage address in the selectable address segment in the memory to be not stored, further comprising:

8. The method according to claim 7, wherein the determining the address to be written back in the optional address field according to the read storage tag of each storage address in the optional address field comprises:

9. A data packet processing device is applied to the field of transmission control protocol data packets, and comprises:

a transmission module, configured to output the received data packet if it is determined that the received data packet is output, and update the expected sequence number according to a sequence number and a payload length of the received data packet to obtain a new expected sequence number;

the storage module is specifically configured to determine a modulo result of a sequence number of the received data packet and a storage capacity of the memory, and obtain a target storage start address of the received data packet in the memory; storing the received data packet into the target storage segment in the memory starting from the target storage starting address;

the determining module is further configured to determine a start address to be output according to the expected sequence number and the storage capacity of the memory; determining whether to output data according to the storage mark of the initial address to be output; if so, reading and outputting data in a continuous address field which is started by the starting address to be output and has stored storage marks, updating the storage marks of all storage addresses in the continuous address field to be not stored, and calculating the sum of the expected sequence number and the length of the continuous address field to obtain a new expected sequence number.

10. A computer device, comprising: a processor and a memory, the memory storing machine-readable instructions executable by the processor, the processor executing the machine-readable instructions when the computer apparatus is running to perform the steps of the data packet processing method according to any one of claims 1 to 8.

11. A computer-readable storage medium, having stored thereon a computer program for performing, when executed by a processor, the steps of the data packet processing method according to any one of claims 1 to 8.