CN113745158A - Trench sidewall gate with extraction structure and method of making same - Google Patents

Trench sidewall gate with extraction structure and method of making same Download PDF

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Publication number
CN113745158A
CN113745158A CN202010477502.9A CN202010477502A CN113745158A CN 113745158 A CN113745158 A CN 113745158A CN 202010477502 A CN202010477502 A CN 202010477502A CN 113745158 A CN113745158 A CN 113745158A
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Prior art keywords
trench
groove
gate
silicon oxide
etching
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许超奇
陈淑娴
罗泽煌
马春霞
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CSMC Technologies Fab2 Co Ltd
CSMC Technologies Corp
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CSMC Technologies Fab2 Co Ltd
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Priority to PCT/CN2020/140502 priority patent/WO2021238197A1/en
Publication of CN113745158A publication Critical patent/CN113745158A/en
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/8232—Field-effect technology
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

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Abstract

The invention relates to a groove side wall grid with a lead-out structure and a manufacturing method thereof, wherein the method comprises the following steps: etching on the substrate to form a first groove and a second groove; filling grid materials into the first and second grooves; forming an etching barrier layer exposing the first groove and partially exposing the second groove on the substrate; etching the gate material in the first trench; removing the etching barrier layer, and then performing chemical vapor deposition to form silicon oxide covering the first and second trenches; removing silicon oxide on the gate material in the first trench by ordinary etching; and etching the gate material in the first trench by taking the silicon oxide retained on the side wall of the first trench as a barrier layer, forming a trench side wall gate on the side wall of the bottom of the first trench, and taking the gate material in a second trench communicated with the trench side wall gate into a whole as a gate lead-out structure. The top of the gate material in the second trench of the present invention can stay on the surface of the substrate, and the gate material can be led out through the conventional via process to form an electrical connection to the gate.

Description

Trench sidewall gate with extraction structure and method of making same
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a groove side wall grid with an extraction structure and a manufacturing method of the groove side wall grid with the extraction structure.
Background
The contradiction between the breakdown voltage of the high-voltage device (the device with higher breakdown voltage BV) and the device area is a problem which is always faced by the industry. It is desirable to make the breakdown voltage (breakdown voltage) of the device as high as possible and to make the on-resistance Rdson as small as possible (the small area of the device can make Rdson small). When the drift region length of LDMOS (lateral double diffused metal oxide semiconductor field effect transistor) is reduced to a certain length, the drift region length cannot be reduced any more since a sufficiently long drift region is required to maintain BV. Small device area and large BV can be achieved by changing the drift region from lateral to vertical.
One common vertical drift region device is a VDMOS (vertical double diffused metal oxide semiconductor field effect transistor). However, the exemplary VDMOS drain is back-side extracted, and there are compatibility issues with BCD process (BCD process is an integrated process technology that can fabricate BJT, CMOS and DMOS devices on the same chip).
Disclosure of Invention
In view of the above, it is desirable to provide a trench sidewall gate with an extraction structure and a method for manufacturing the same, which have good compatibility with the BCD process.
A method for manufacturing a trench sidewall gate with an extraction structure comprises the following steps: etching a substrate to form a groove structure, wherein the groove structure comprises a first groove and a second groove, the first groove is used for forming a groove side wall grid, the second groove is used for forming a leading-out structure, and the first groove is communicated with the second groove; filling grid electrode materials into the first groove and the second groove, wherein the grid electrode materials in the first groove and the second groove are communicated into a whole; forming an etching barrier layer on the substrate, wherein the etching barrier layer exposes the first groove and partially exposes the second groove, and the exposed width of the second groove is smaller than that of the second groove; anisotropic etching is carried out on the grid electrode material in the first groove to reach a required height, and the grid electrode material in the second groove is etched to form a gap due to partial exposure of the second groove; removing the etching barrier layer, and then carrying out chemical vapor deposition to form silicon oxide covering the first groove and the second groove, wherein the silicon oxide on the second groove is influenced by the notch, so that the thickness of the silicon oxide is larger than that of the silicon oxide on the grid material in the first groove; removing silicon oxide on the gate material in the first trench through ordinary etching so that the gate material in the first trench is exposed, wherein the silicon oxide on the second trench is still partially remained on the second trench, the ordinary etching adopts an anisotropic etching process, and the silicon oxide is still remained on the side wall of the first trench after the ordinary etching; and etching the gate material in the first trench by taking the silicon oxide remained on the side wall of the first trench as a barrier layer, forming a gate on the side wall of the trench on the side wall of the bottom of the first trench, and taking the gate material in the second trench communicated with the gate on the side wall of the trench as a gate lead-out structure.
In one embodiment, the cross-section of the second groove is a circle surrounding the first groove.
In one embodiment, the cross section of the second groove is a rectangular frame surrounding the first groove, and the cross section of the first groove is a strip shape parallel to a set of opposite sides of the rectangular frame.
In one embodiment, the groove width of the first groove is 0.8-1.4 microns, and the groove width of the second groove is 0.6-1 micron.
In one embodiment, the depth of the first groove and the second groove is 2-5 microns.
In one embodiment, an etching barrier layer is formed on the substrate, and in the step of exposing the second trench, the exposed width is 0.1-0.5 micrometers.
In one embodiment, before the step of filling the gate material into the first trench and the second trench, a step of forming a gate oxide layer on an inner surface of the first trench and an inner surface of the second trench is further included.
In one embodiment, the thickness of the gate oxide layer formed in the step of forming the gate oxide layer in the first trench and the second trench is as follows
Figure BDA0002516302700000021
In one embodiment, before the step of forming the gate oxide layer in the first trench and the second trench, a step of growing silicon oxide on the surface of the substrate and the inner surface of the trench structure by using a furnace tube and then removing the silicon oxide by using a wet method is further included.
In one embodiment, the thickness of the silicon oxide grown in the step of growing the silicon oxide on the surface of the substrate and the inner surface of the trench structure by using the furnace tube is as follows
Figure BDA0002516302700000022
In one embodiment, the step of forming the etch stop layer on the substrate includes coating a photoresist and using the photoresist as the etch stop layer after the photoresist is subjected to photolithography.
In one embodiment, the gas source used in the step of performing the chemical vapor deposition after removing the etching barrier layer is tetraethoxysilane, and the thickness of the deposited silicon oxide is
Figure BDA0002516302700000031
In one embodiment, after the step of removing the silicon oxide on the gate material in the first trench by ordinary etching, silicon oxide still remains on the second trench
Figure BDA0002516302700000032
Thick silicon oxide.
In the manufacturing method of the trench sidewall gate with the extraction structure, the gate is formed on the sidewall of the bottom of the first trench, so that the active region can be extracted from the bottom of the first trench, and each end of the DMOS is extracted from the front surface of the device, thereby having good compatibility with the BCD process. And when the gate material in the first trench is etched by taking the silicon oxide remained on the side wall of the first trench as the etching barrier layer, the gate material in the second trench cannot be etched because the silicon oxide still remains on the second trench, so that the gate material in the second trench has the height before the silicon oxide is deposited, the top of the gate material can stay on the surface of the substrate, and the gate material can be led out through a conventional through hole process to form electrical connection to the gate.
The utility model provides a slot lateral wall grid with extraction structure, is including locating the grid of the first slot bottom lateral wall of basement and locating the grid extraction structure in the second slot that basement and first slot communicate, the grid extraction structure with the grid intercommunication is as an organic whole and the material is the same with the grid, the height at grid extraction structure top approaches the surface of basement.
In one embodiment, the gate is a polysilicon gate.
In one embodiment, the cross section of the second groove is a rectangular frame surrounding the first groove, and the cross section of the first groove is a strip shape parallel to a set of opposite sides of the rectangular frame.
In one embodiment, the gate lead-out structure is formed with a notch at the top of one side close to the gate.
The groove side wall grid with the leading-out structure has good compatibility with a BCD process because the grid is formed on the side wall of the bottom of the first groove, so that the active region can be led out from the bottom of the first groove, and each end of the DMOS is led out from the front surface of the device. The top of the grid lead-out structure is close to the surface of the substrate in height, so that a through hole electrically connected to the top of the grid lead-out structure can be formed through a conventional through hole process and is used as a lead-out of the grid for electrical connection.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIG. 1 is a flow chart of a method of fabricating a trench sidewall gate with an extraction structure in one embodiment;
FIG. 2 is a schematic top view of a trench structure in one embodiment;
FIG. 3 is a cross-sectional view of the trench structure shown in FIG. 2;
FIG. 4 is a schematic diagram illustrating a position of the etching stop layer formed in step S130 according to an embodiment;
FIG. 5 is a cross-sectional view of the wafer after step S140 is completed according to an embodiment;
FIG. 6 is a cross-sectional view of the wafer after step S150 is completed in one embodiment;
FIG. 7 is a cross-sectional view of the wafer after step S160 is completed according to an embodiment;
FIG. 8 is a cross-sectional view of the wafer after step S170 is completed in one embodiment;
FIG. 9 is a cross-sectional view of the wafer after filling the first trench with silicon oxide and removing the silicon oxide from the substrate surface after step S170 is completed in one embodiment;
FIG. 10 is a cross-sectional view of a trench sidewall gate with a lead-out structure in one embodiment;
fig. 11 is a schematic top view of a trench structure of an embodiment having a plurality of first trenches in a ring of second trenches.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only. When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
When the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
A novel Trench DMOS (Double-diffused metal oxide semiconductor) device needs to form a grid (Gate) on the bottom side wall of a Trench (Trench), so that an active region below the Trench can be led out upwards from the bottom of the Trench. Taking the example that the grid electrode on the side wall of the groove is a polysilicon (Poly) grid electrode, the grid electrode on the side wall of the groove cannot lead out the polysilicon in a mode of directly punching a through hole. Therefore, the novel trench sidewall gate faces the technical problem of how to lead out electrical connection.
For the trench sidewall gate, an exemplary (for example, the gate is made of polysilicon) lead-out manner is to lead out polysilicon in the trench to the surface of the wafer (wafer), so that the potential can be applied to the trench sidewall gate through the conductive material in the via.
In an exemplary split gate (split gate) process, photoresist may be used to cover the other end of the stripe-shaped split gate trench during the split gate etch, and polysilicon is etched only at one end, polysilicon (poly1) not covered by the photoresist in the trench is etched to a specified depth during the split gate etch, and polysilicon covered by the photoresist remains on the wafer surface and the bottom is connected to etched poly1 in the trench. Poly1 etched into the trench can still be connected to the wafer surface through the polysilicon at the other end.
However, if the trench sidewall gate is to be led out by the above-mentioned split gate process, after the polysilicon in the trench is etched to a specified depth, the sidewall gate needs to be formed on the sidewall of the bottom of the trench by self-aligned etching. The photoresist is removed during the self-aligned etching, so that the polysilicon at the other end is etched together, and therefore, the polysilicon cannot stay on the surface of the wafer and is convenient to be led out through the conventional through hole process. If the photoresist is used as the etching barrier layer for etching the side wall grid, the yield of the device cannot be guaranteed because the process of filling the photoresist in the groove and exposing is unstable.
Fig. 1 is a flow chart of a method for manufacturing a trench sidewall gate with an extraction structure in one embodiment, including the following steps:
s110, etching on the substrate to form a first groove and a second groove.
And etching the substrate to form a groove structure. The substrate includes a semiconductor substrate, and the material of the substrate may be undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. The substrate may also be formed with other structures that are common in integrated circuit fabrication, such as Shallow Trench Isolation (STI) structures.
Referring to fig. 2, the trench structure includes a first trench 21 for forming a trench sidewall gate and a second trench 23 for forming a lead-out structure, and the first trench 21 communicates with the second trench 23. Fig. 2 shows mainly the shape and distribution of the trench structure in plan view, so that the base structure outside the second trenches 23 is not depicted. In one embodiment, the cross-section of the second groove 23 is one turn surrounding the first groove 21. In the embodiment shown in fig. 2, the cross section of the second groove 23 is a rectangular frame surrounding the first groove 21, and the cross section of the first groove 21 is a bar shape parallel to a set of opposite sides of the rectangular frame. For the embodiment where there is only one first groove 21 in the circle of second grooves 23, the groove structure is "zigzag"; for the embodiment where there are two first grooves 21 in one turn of the second groove 23, the groove structure is "mu" shaped.
In one embodiment, the first trench 21 has a trench width a of 0.8 to 1.4 microns and the second trench 23 has a trench width b of 0.6 to 1 micron. In one embodiment, the first trench and the second trench have a depth of 2 to 5 μm.
Fig. 3 is a cross-sectional view of the trench structure shown in fig. 2, in the embodiment shown in fig. 3, the etching in step S110 uses the hard mask 12 as an etching stop layer, and the material of the hard mask 12 may be silicon dioxide.
And S120, filling the gate material into the first trench and the second trench.
In one embodiment, the gate material is polysilicon. In other embodiments, the gate material may also use a metal, metal nitride, metal silicide, or similar compounds. In one embodiment, the first trench 21 and the second trench 23 may be filled with a gate material by a deposition process.
In one embodiment, step S120 is preceded by a step of forming a gate dielectric layer 29 on the first trench inner surface and the second trench inner surface. In one embodiment, gate dielectric layer 29 is a gate oxide layer. The gate dielectric layer 29 may also comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 29 may comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).
In one embodiment, forming the gate dielectric layer 29 is growing a gate oxide layer using a furnace. In one embodiment, the gate oxide layer is grown to a thickness of
Figure BDA0002516302700000071
In one embodiment, the step of growing silicon oxide on the substrate surface and the inner surface of the trench structure by using a furnace tube and then removing the silicon oxide by using a wet method is further included before forming the gate dielectric layer 29. In particular, canThe furnace tube is used for growing the thickness of the silicon nitride on the surface of the substrate and the inner surface of the groove structure
Figure BDA0002516302700000072
The silicon oxide layer is then rinsed off by a wet process. The step can reduce the surface damage caused by etching the trench structure (deep trench etching) in the step S110, improve the problem of corner cut at the top of the trench, and improve the Gate Oxide Integrity (GOI) capability of the sidewall of the trench.
In one embodiment, the step S120 of filling the gate material is to etch back the filled gate material to a height below the substrate surface under the premise of ensuring that the first trench and the second trench are filled up
Figure BDA0002516302700000081
And S130, forming an etching barrier layer exposing the first trench and partially exposing the second trench for a certain width.
An etch stop layer is formed on the substrate. Referring to fig. 4, in an embodiment, the etching blocking layer in step S130 is a photoresist, and fig. 4 shows an inner contour and an outer contour of the photoresist by dashed line frames, respectively, it can be understood that fig. 4 is mainly for showing a position where the etching blocking layer exposes the second trench 23, so that an emphasis is placed on the inner contour of the photoresist, and the outer contour of the photoresist in fig. 4 is difficult to identify so as not to coincide with other lines, so that the outer expansion process is performed. After the photoresist is developed, the first trench 21 is exposed, and the second trench 23 is partially exposed, and the exposed width of the second trench 23 is smaller than that of the second trench 23. In one embodiment, the width of the second trench 23 exposed by the photoresist is 0.1 to 0.5 μm. In the embodiment shown in FIG. 4, the photoresist exposes the inner side of the second trench 23, and the distance c between the inner side of the photoresist and the inner side of the second trench 23 is 0.1 to 0.5 μm.
S140, etching the gate material in the first trench to a required height, and etching the gate material in the second trench to form a gap.
Referring to fig. 5, the gate material 22 in the first trench 21 is anisotropically etched toThe required height. In one embodiment, the dry etch is performed using an anisotropic etch gas. Since the photoresist 14 partially exposes the second trench 23, etching gas may also enter from the exposed position, so that the gate material 22 in the second trench 23 is partially etched to form a gap. However, since the exposed width is smaller, the etching depth is shallower, and a step-like structure is formed at the gap (the gate material 22 is partially etched away to form a step difference). The height of the gate material 22 remaining in the first trench 21 after the etching in step S140 is the height of the gate to be formed subsequently, so that the thickness of the etched gate material 22 can be set according to the height required by the gate. In one embodiment, the height of the gate material 22 remaining in the first trench 21 after etching is
Figure BDA0002516302700000082
And S150, removing the etching barrier layer, and then performing chemical vapor deposition to form silicon oxide covering the first groove and the second groove.
Referring to fig. 6, after the Chemical Vapor Deposition (CVD) is completed in step S150, the silicon oxide 16 on the second trench 23 is affected by the gap, and the deposition thickness may be greater than the deposition thickness d of the silicon oxide 16 on the gate material 22 in the first trench 21 (because the CVD may be deposited thicker where there is a step difference).
S160, by commonly exposing the gate material in the first trench, a portion of the silicon oxide on the second trench remains.
Without using a photolithography mask, the silicon oxide 16 on the gate material 22 in the first trench 21 is removed by ordinary etching, so that the gate material 22 in the first trench 21 is exposed (the ordinary etching employs an anisotropic etching process, and the silicon oxide 16 remains on the sidewall of the first trench 21 after the ordinary etching), and the thickness of the silicon oxide 16 on the second trench 23 is greater than that of the silicon oxide 16 on the gate material 22 in the first trench 21, so as to ensure that a part of the silicon oxide 16 remains on the second trench 23 after the silicon oxide 16 on the gate material 22 in the first trench 21 is removed (similar to the formation of a MOS polysilicon gate sidewall), see fig. 7.
In one embodiment, step S160 has a certain amount of over-etching in order to ensure that the gate material 22 in the first trench 21 is exposed after etching.
In one embodiment, the thickness of the silicon oxide 16 remaining on the second trench 23 after step S160 is completed is
Figure BDA0002516302700000091
And S170, forming a groove side wall grid by self-aligned etching, wherein the grid material in the second groove is used as a grid leading-out structure.
The gate material 22 in the first trench 21 is etched with the silicon oxide 16 remaining on the sidewalls of the first trench 21 as a barrier layer, forming a trench sidewall gate 24 on the sidewalls of the bottom of the first trench 21, see fig. 8. Since the gate material 22 in the second trench 23 is communicated with the trench sidewall gate 24 as a whole, the gate material 22 in the second trench 23 can be used as a gate lead-out structure, and after the silicon oxide 16 on the second trench 23 is removed in the subsequent steps, a through hole electrically connected to the top of the gate lead-out structure is formed through a conventional through hole process and is used as a lead-out of the gate for electrical connection.
If the second trench 23 is completely covered by the etching stop layer in step S130, the gate material 22 in the second trench 23 will not be partially etched to form a gap, and the thickness of the silicon oxide deposited in step S150 on the second trench 23 will be the same as the thickness of the silicon oxide on the gate material 22 in the first trench 21. Therefore, the silicon oxide in the second trench 23 is completely etched in step S160, and the gate material 22 in the second trench 23 is not protected by the silicon oxide in the etching of step S170, and is etched downward, so that the top of the gate material cannot stay on the substrate surface.
Step S170 may employ an anisotropic etch Recipe (Recipe) having a high selection ratio for silicon/silicon oxide to form the trench sidewall gate 24 on the bottom sidewall of the first trench 21. In one embodiment, the main etch gas comprises Cl2And HBr (carrier gas may also be added). In one embodiment, the flow rate of the etching gas is Cl2 30sccm～50sccm，HBr 60sccm～80sccm，O2 5sccm～15sccm，Helium gas is 5sccm to 15 sccm. In one embodiment, the etching pressure is controlled to be 30-70 millitorr, the Source Power is controlled to be 250-450W, and the BIAS Power is controlled to be-180V-240V.
It will be appreciated that the thickness e of the trench sidewall gate 24 is determined by the deposition thickness d of the silicon oxide 16 in step S150. In one embodiment, the gas source for the chemical vapor deposition in step S150 is tetraethylorthosilicate and the deposited silicon oxide (silicon dioxide) has a thickness of
Figure BDA0002516302700000101
In the method for manufacturing the trench sidewall gate with the extraction structure, the gate is formed on the sidewall of the bottom of the first trench 21, so that the active region can be extracted from the bottom of the first trench 21, and each end of the DMOS is extracted from the front surface of the device, thereby having good compatibility with the BCD process. When the gate material 22 in the first trench 21 is etched by taking the silicon oxide 16 remained on the sidewall of the first trench 21 as an etching barrier layer, the gate material 22 in the second trench 23 is not etched because the silicon oxide 16 still remains on the second trench 23, so that the gate material 22 in the second trench 23 has a height before the deposition of the silicon oxide 16, and thus the top of the gate material 22 in the second trench 23 can stay on the surface of the substrate, and the gate material 22 can be led out by a conventional through hole process to form an electrical connection to the gate. In addition, the method only has one photoetching process in the step S130 after the groove structure is formed, and the required photoetching processes are fewer, so the overall cost is lower.
In one embodiment, step S170 is completed and further includes a step of filling the first trench 21 with silicon oxide 26 and removing the silicon oxide on the substrate surface. After the above steps are completed, the wafer surface (substrate surface) is restored to the state before step S110, i.e. the flat surface is restored, see fig. 9. Thus, the manufacturing process of the CMOS (complementary metal oxide semiconductor) process can be continued, and thus the method for manufacturing the trench sidewall gate with the extraction structure can be compatible with the CMOS process. In one embodiment, the filling of the silicon oxide 26 into the first trench 21 may employ a high density plasma thermal chemical vapor deposition (HDPCVD) process. In one embodiment, the silicon oxide on the surface of the substrate can be removed by wet grinding.
In one embodiment, step S120 is deposition
Figure BDA0002516302700000102
Of polycrystalline silicon. Because the polysilicon in the trench structure grows from the trench sidewall to the trench center, the trench can be completely filled as long as the thickness of the deposited polysilicon is greater than twice the trench width, and thus the polysilicon is deposited
Figure BDA0002516302700000103
The first trenches 21 may be completely filled with 0.8-1.4 microns wide polysilicon.
In one embodiment, an active region and an STI (shallow trench isolation) region are formed on a substrate, and step S110 is to etch down the STI region to form a trench structure. Specifically, the STI structure may be formed by the following process: depositing a layer of silicon nitride on the surface of a substrate, photoetching and etching the silicon nitride to form a shallow groove in an STI region, then filling silicon dioxide in the shallow groove, performing Chemical Mechanical Polishing (CMP) by using the silicon nitride as a polishing stop layer, and finally removing the silicon nitride by wet etching to obtain the STI structure. The silicon dioxide in the STI structure may be directly used as the hard mask 12 in step S110.
The application correspondingly provides a trench sidewall gate with a lead-out structure. Fig. 10 is a cross-sectional view of a trench sidewall gate with a lead-out structure in an embodiment, which includes a gate 124 disposed on the bottom sidewall of a first trench 121 in a substrate, and a gate lead-out structure 126 disposed in a second trench 123 in the substrate and communicated with the first trench 121. The gate lead-out structure 126 is communicated with the gate 124 into a whole and has the same material as the gate 124, and the height of the top of the gate lead-out structure 126 is close to the surface of the substrate. In the embodiment shown in fig. 10, an interlayer dielectric (ILD)128 is further formed on the first trench 121 and the second trench 123, and a gate dielectric layer 129 is further formed on the inner surface of the first trench 121 and the inner surface of the second trench 123.
The trench sidewall gate with the extraction structure has good compatibility with the BCD process because the gate 124 is formed on the sidewall of the bottom of the first trench 121, so that the active region can be extracted from the bottom of the first trench 121, and each end of the DMOS can be extracted from the front surface of the device. The top of the gate lead-out structure 126 is highly close to the surface of the substrate and thus a via 132 electrically connected to the top of the gate lead-out structure 126 may be formed by a conventional via process to make an electrical connection as a lead-out of the gate 124.
In the embodiment shown in fig. 10, the gate lead-out structure 126 is formed with a notch at the top of a side close to the gate 124. The material filled in the gap may be silicon oxide, such as silicon dioxide.
In the embodiment shown in fig. 10, via 134 is a via that serves as the drain, and via 136 is a via that serves as the source. Vias 132, 134, and 136 are filled with a conductive material, wherein the conductive material can be any suitable conductive material known to those skilled in the art, including but not limited to a metal material; wherein, the metal material can comprise one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al. The conductive material in via 134 is electrically connected to a doped region in the substrate surface (the doped region is not shown in fig. 10) and the conductive material in via 136 is electrically connected to a doped region in the substrate under the first trench 121 (the doped region is not shown in fig. 10).
In the embodiment shown in fig. 10, the positions within the first trench 121 except for the conductive material filled in the via 136 and the gate electrode 124 are filled with silicon oxide.
In one embodiment, the material of the gate 124 and the pole extension structure 126 is polysilicon. In other embodiments, the material of the gate 124 and the pole extension structure 126 may also use metal, metal nitride, metal silicide or similar compounds.
In one embodiment, the cross-section of the second groove 123 is one turn surrounding the first groove 121. In another embodiment, the cross section of the second groove 123 is a rectangular frame surrounding the first groove 121, and the cross section of the first groove 121 is a bar shape parallel to a set of opposite sides of the rectangular frame. For the embodiment where there is only one first groove 121 in the circle of second grooves 123, the first grooves 121 and the second grooves 123 form a "zigzag" structure; for the embodiment where there are two first grooves 121 in one turn of the second grooves 123, the first grooves 121 and the second grooves 123 form a "mu" shaped structure. Fig. 11 is a schematic top view of a trench structure of an embodiment having a plurality of first trenches 21 in a ring of second trenches 23.
In one embodiment, the first trench 121 and the second trench 123 are formed in an STI region.
In one embodiment, the substrate includes a semiconductor substrate, which may be undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. The substrate may also be formed with other structures that are common in integrated circuit fabrication, such as Shallow Trench Isolation (STI) structures.
In one embodiment, the interlayer dielectric 128 may be a silicon oxide layer, such as a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a high density plasma thermal chemical vapor deposition (HDPCVD) process, and may be Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric 128 may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.
In one embodiment, gate dielectric layer 129 is a gate oxide layer. The gate dielectric layer 129 may also comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 129 may comprise generally higher dielectric constant dielectric materials having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, Barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (13)

1. A method for manufacturing a trench sidewall gate with an extraction structure comprises the following steps:
etching a substrate to form a groove structure, wherein the groove structure comprises a first groove and a second groove, the first groove is used for forming a groove side wall grid, the second groove is used for forming a leading-out structure, and the first groove is communicated with the second groove;
filling grid electrode materials into the first groove and the second groove, wherein the grid electrode materials in the first groove and the second groove are communicated into a whole;
forming an etching barrier layer on the substrate, wherein the etching barrier layer exposes the first groove and partially exposes the second groove, and the exposed width of the second groove is smaller than that of the second groove;
anisotropic etching is carried out on the grid electrode material in the first groove to reach a required height, and the grid electrode material in the second groove is etched to form a gap due to partial exposure of the second groove;
removing the etching barrier layer, and then carrying out chemical vapor deposition to form silicon oxide covering the first groove and the second groove, wherein the silicon oxide on the second groove is influenced by the notch, so that the thickness of the silicon oxide is larger than that of the silicon oxide on the grid material in the first groove;
removing silicon oxide on the gate material in the first trench through ordinary etching so that the gate material in the first trench is exposed, wherein the silicon oxide on the second trench is still partially remained on the second trench, the ordinary etching adopts an anisotropic etching process, and the silicon oxide is still remained on the side wall of the first trench after the ordinary etching;
and etching the gate material in the first trench by taking the silicon oxide remained on the side wall of the first trench as a barrier layer, forming a gate on the side wall of the trench on the side wall of the bottom of the first trench, and taking the gate material in the second trench communicated with the gate on the side wall of the trench as a gate lead-out structure.
2. The method of manufacturing a trench sidewall gate with an extraction structure as claimed in claim 1, wherein the cross section of the second trench is a circle surrounding the first trench.
3. The method according to claim 2, wherein a cross section of the second trench is a rectangular frame surrounding the first trench, and a cross section of the first trench is a stripe shape parallel to a set of opposite sides of the rectangular frame.
4. The method for manufacturing a trench sidewall gate with a lead-out structure according to any one of claims 1 to 3, wherein a groove width of the first trench is 0.8 to 1.4 μm, and a groove width of the second trench is 0.6 to 1 μm.
5. The method for manufacturing a trench sidewall gate with a lead-out structure according to claim 4, wherein the depth of the first trench and the second trench is 2 to 5 μm.
6. The method according to claim 4, wherein an etching barrier layer is formed on the substrate, and the width of the etching barrier layer exposed in the step of exposing the second trench is 0.1-0.5 μm.
7. The method according to claim 1, further comprising a step of forming a gate oxide layer on an inner surface of the first trench and an inner surface of the second trench, wherein a thickness of the gate oxide layer is set to be a thickness of the gate oxide layer
Figure FDA0002516302690000021
8. The method of claim 1, wherein the step of forming an etch stop layer on the substrate comprises coating a photoresist and using the photoresist as an etch stop layer after the photoresist is etched.
9. The method of claim 1, wherein the step of removing the etch stop layer followed by chemical vapor deposition uses tetraethoxysilane as a gas source and deposits silicon oxide to a thickness of
Figure FDA0002516302690000022
10. The method of claim 1 wherein silicon oxide is removed from the gate material in the first trench by a conventional etch process, leaving silicon oxide on the second trench
Figure FDA0002516302690000023
Thick silicon oxide.
11. The groove side wall grid with the lead-out structure is characterized by comprising a grid arranged on the side wall of the bottom of a first groove of a substrate and a grid lead-out structure arranged in a second groove, wherein the substrate is communicated with the first groove, the grid lead-out structure is communicated with the grid into a whole and is made of the same material as the grid, and the height of the top of the grid lead-out structure approaches to the surface of the substrate.
12. The trench sidewall gate with the extraction structure of claim 11, wherein a cross section of the second trench is a rectangular frame surrounding the first trench, and a cross section of the first trench is a stripe shape parallel to a set of opposite sides of the rectangular frame.
13. The trench sidewall gate with the extraction structure of claim 11 or 12, wherein the gate extraction structure is notched at the top of one side close to the gate.
CN202010477502.9A 2020-05-29 2020-05-29 Trench sidewall gate with extraction structure and method of making same Pending CN113745158A (en)

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