CN113744776A

CN113744776A - Memory circuit, data writing and reading method thereof, memory and electronic equipment

Info

Publication number: CN113744776A
Application number: CN202110864849.3A
Authority: CN
Inventors: 杨美音; 李文静; 叶力; 向清懿; 罗军; 高建峰
Original assignee: Institute of Microelectronics of CAS; HiSilicon Technologies Co Ltd
Current assignee: Institute of Microelectronics of CAS; HiSilicon Technologies Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2021-12-03
Anticipated expiration: 2041-07-29
Also published as: CN113744776B

Abstract

The invention can provide a memory circuit, a data writing and reading method thereof, a memory and an electronic device. The writing method comprises the following steps: introducing unidirectional current within a first preset range into a bottom electrode connected with the tunnel junction so as to write first data into the tunnel junction; or the unidirectional current in a second preset range is introduced into the bottom electrode connected with the tunnel junction so as to write second data into the tunnel junction. The absolute value of the current in the second preset range is larger than the first preset range, and the first data and the second data are opposite. The reading method comprises the following steps: a preset read voltage is applied to the tunnel junction to read out the data written to the tunnel junction. The memory circuit includes a bottom electrode, a tunnel junction, a first switching device, a second switching device, a bit line, a source line, and a read line. The invention changes the written data content by controlling the magnitude of the absolute value of the unidirectional current so as to effectively solve at least one problem in the prior memory technology.

Description

Memory circuit, data writing and reading method thereof, memory and electronic equipment

Technical Field

The invention relates to the technical field of memories, in particular to a memory circuit, a data writing and reading method thereof, a memory and an electronic device.

Background

Spin-Orbit torque magnetic Random Access Memory (SOT-MRAM) refers to a Random Access Memory capable of storing data by changing a magnetization state, and has advantages of non-volatility, low power consumption, radiation resistance, and the like. The most basic memory unit of the spin-orbit torque Magnetic random access memory is a Magnetic Tunnel Junction (MTJ), and generally, the spin-orbit torque Magnetic random access memory needs an external Magnetic field to assist writing, and two opposite currents need to be passed through a bottom electrode to write different information. Since the read-write channel separation of the SOT-MRAM needs two transistors to control the read-write operation of the MTJ, the area of the memory array is greatly increased, and the memory density is reduced. In addition, how to increase the reliability of information writing is also a big difficulty.

Disclosure of Invention

In order to meet the requirements of high reliability and high integration of the magnetic random access memory, the invention can provide the memory circuit, the data writing and reading method thereof, the memory and the electronic equipment, and the aim of writing data into the memory through a reliable control strategy is fulfilled on the premise of meeting the requirement of high integration.

To achieve the above technical objects, the present invention can provide a data writing method of a memory circuit, the data writing method including, but not limited to, one or more of the following steps. Introducing unidirectional current within a first preset range into a bottom electrode connected with the tunnel junction so as to write first data into the tunnel junction; or, the invention leads the unidirectional current in a second preset range to the bottom electrode connected with the tunnel junction so as to write the second data into the tunnel junction. The current absolute value in the second preset range is larger than the current absolute value in the first preset range, and the first data and the second data are opposite.

To achieve the above technical objects, the present invention can provide a data reading method of a memory circuit, which includes, but is not limited to, the following steps. A predetermined read voltage is applied to a tunnel junction connected to the bottom electrode to read out the first data or the second data stored in the tunnel junction.

To achieve the above technical objects, the present invention can also provide a memory circuit that may include, but is not limited to, a bottom electrode, a tunnel junction, a first switching device, a second switching device, a bit line, a source line, and a read line. The bottom electrode is used for leading in unidirectional current in the data writing process, and the tunnel junction is arranged on the bottom electrode, connected with the bottom electrode and used for storing written data. The first switch device is connected with the tunnel junction, the second switch device is connected with one end of the bottom electrode, the bit line is connected with the other end of the bottom electrode, the source line is connected with the second switch device, and the read line is connected with the first switch device.

To achieve the above technical objects, the present invention can also specifically provide a memory, which can include, but is not limited to, a memory circuit in any embodiment of the present invention.

To achieve the above technical objects, the present invention can also specifically provide an electronic device, which may include, but is not limited to, a memory in any embodiment of the present invention.

The invention has the beneficial effects that: compared with the prior art, the method changes the written data content through the magnitude of the absolute value of the unidirectional current. By passing a current in the horizontal direction through the bottom electrode of the SOT, the current writing mode of the invention is determined by the magnitude of the current, namely, a small current (absolute value) is written into '0' (or '1'), and a large current (absolute value) is written into '1' (or '0'). The method can effectively avoid the problems of complex control circuit, poor data writing reliability or increased structural complexity of devices and the like caused by repeatedly adjusting the current direction. The invention reduces the requirements on the complexity of the circuit structure and the complexity of the control logic of the memory, and can be beneficial to realizing the miniaturization and the micromation of the SOT-MRAM memory device, thereby meeting the requirements on manufacturing the SOT-MRAM memory device with high density.

Drawings

FIG. 1 shows a schematic of a tunnel junction write curve in one or more embodiments of the invention (with the abscissa representing voltage used to form a unidirectional current and the ordinate representing tunnel junction resistance).

FIG. 2 illustrates a schematic diagram of a memory circuit in some embodiments of the inventions.

FIG. 3 illustrates a schematic diagram of a memory circuit including a plurality of memory cells in some embodiments of the invention.

FIG. 4 is a schematic diagram of a memory circuit according to another embodiment of the invention.

FIG. 5 is a schematic diagram of a memory circuit including a plurality of memory cells according to further embodiments of the present invention.

FIG. 6 shows a schematic diagram of a memory circuit in further embodiments of the present invention.

FIG. 7 shows a schematic diagram of a memory circuit including a plurality of memory cells in further embodiments of the present invention.

Fig. 8 shows a schematic diagram of a tunnel junction in one or more embodiments of the invention.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

The invention can provide a data writing method of a memory circuit, in particular to a method for writing different data into a memory by using current. The Memory involved in the present invention is specifically an SOT-MRAM (spin-Magnetic Random Access Memory), i.e., a spin-orbit coupling-Magnetic Random Access Memory cell, and it can be seen that the embodiments of the present invention can provide a method for writing data to the SOT-MRAM by using the magnitude of current.

As shown in fig. 1, and in conjunction with fig. 2-8, the data writing method of the memory circuit may include, but is not limited to, the following steps: introducing unidirectional current within a first preset range into a bottom electrode connected with the tunnel junction so as to write first data into the tunnel junction; or, a unidirectional current in a second preset range is introduced into the bottom electrode connected with the tunnel junction so as to write second data different from the first data into the tunnel junction. In this embodiment, the absolute value of the current in the second predetermined range is greater than the absolute value of the current in the first predetermined range, and the first data is opposite to the second data. The first data is "1", and the second data is "0"; alternatively, the first data is "0" and the second data is "1". The unidirectional current is a unidirectional current parallel to the extending direction of the bottom electrode, and the extending direction of the bottom electrode in this embodiment is a horizontal direction. The tunnel junction in one or more embodiments of the present invention may include, but is not limited to, a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer, and a top electrode, disposed in that order; wherein the free layer is disposed on the bottom electrode.

In combination with the tunnel junction write curve in fig. 1, the unit of voltage may be V, the unit of resistance may be Ω, the magnitude and direction of the unidirectional current of the present invention both correspond to the applied voltage, and the current increases with the increase of the voltage; the written data corresponds to the resistance of the tunnel junction, for example, the written data "1" corresponds to the high resistance state, the written data "0" corresponds to the low resistance state, or the written data "0" corresponds to the high resistance state, and the written data "1" corresponds to the low resistance state; it will be appreciated that the resistance of the tunnel junction in the present invention increases with increasing absolute value of the unidirectional current. For the first preset range, the second preset range and the specific values of the corresponding voltages, the invention can carry out corresponding setting according to the actual component composition, for example, the voltage corresponding to the first preset range is minus 1.5V to plus 1.5V; in the example, the current value corresponding to the voltage boundary value (-1.5V or + 1.5V) may be referred to as the flip current, and the present invention can write "1" when the write current is greater than the flip current and write "0" when the write current is less than the flip current, or write "1" when the write current is less than the flip current and write "0" when the write current is greater than the flip current.

Specifically, the step of applying a unidirectional current in a first preset range to the bottom electrode connected to the tunnel junction includes: passing a unidirectional current through the diode and a bottom electrode connected to the tunnel junction; the on direction of the diode is the direction of a unidirectional current, such as from a source line to a bottom electrode or from a bottom electrode to a source line. The embodiment of the invention can utilize the bit line to be connected with the other end of the bottom electrode and is connected with the first switch device through the read line, and the first switch device is connected with the tunnel junction.

The antiferromagnetic layer in the embodiment of the present invention is, for example, an artificial antiferromagnetic layer. The free layer and the reference layer in the invention realize ferromagnetic coupling (anti-ferromagnetic) through the tunneling layer, and the magnetic moment direction of the sum of the reference layer and the artificial anti-ferromagnetic layer is antiparallel (parallel) to the reference layer. The free layer is subjected to the coupling field of the reference layer, the direction of the magnetic field of the sum of the reference layer and the artificial antiferromagnetic layer being opposite. When current is conducted in the SOT bottom electrode, under the condition of current (small current) in a first preset range, the Joule heat is small, and the free layer is overturned to the direction of a coupling magnetic field of the reference layer and the free layer; under the current (large current) in a second preset range, the joule heat is increased due to the increase of the current, the temperature is increased along with the increase of the current, the coupling field of the reference layer to the free layer is reduced, and at the moment, the direction of the free layer is determined by the leakage magnetic field of the artificial antiferromagnetic layer and the reference layer. Because the leakage magnetic field and the coupling field are opposite in direction, the invention can enable the overturning direction of the free layer to be reversed under the action of currents with different magnitudes, namely, the conversion between a high resistance state and a low resistance state of the tunnel junction under different currents is realized, namely, the writing of data of '0' or '1' is realized.

On the basis of the same technical concept, the data writing method of the memory circuit of the invention correspondingly comprises the following steps:

a preset read voltage (Vread) is applied to the tunnel junction connected to the bottom electrode to read out the first data or the second data written to the tunnel junction stored by the data writing method as above. The data reading process in the invention comprises the following steps: a preset read voltage is applied to the tunnel junction, and then the tunnel junction is determined to be in a high resistance state or a low resistance state through a feedback signal (the feedback signal may be a read current or a charge amount, etc.) received by the sense amplifier.

As shown in FIG. 3, and in conjunction with FIG. 2, the present embodiment provides a process for writing data "1" or "0" to a memory array.

	UL(Up Left)	UR(Up Right)	DL(Down Left)	DR(Down Right)
					RL	GND	GND	GND	GND
WL	GND	GND	GND	GND
					SL	Vdd	Vdd	GND	GND
BL	GND	Vdd	GND	Vdd

As shown in the above table, data is written into the memory cell at the Upper Left (UL), for example, "1" is written in the high resistance state, "0" is written in the low resistance state, or "0" is written in the high resistance state, "1" is written in the low resistance state. In the present embodiment, the Source Line (SL)610 is turned on at the level Vdd, and the Bit Line (BL)510 is turned on at the level GND to form a unidirectional current in the horizontal direction through the bottom electrode 100; the Read Line (RL)710 is asserted to GND, the Word Line (WL)810 is asserted to GND, and the transistor 300 is turned off. The invention can write "1" or "0" into the memory cell by changing the magnitude of the Vdd value, i.e., the data written into the tunnel junction is changed by adjusting the magnitude of the unidirectional current in the horizontal direction. Meanwhile, according to the fact that a plurality of memory cells in the x direction in the memory array share a source line 610, a source line 620, a read line 710, a read line 720, a word line 810 and a word line 820, a plurality of memory cells in the y direction share a bit line 510 and a bit line 520, in order to avoid writing data in the memory cells of the right upper side (UR), the left lower side (DL) and the right lower side (DR), the Source Line (SL)610 of the memory cell of the right upper side (UR) is connected to a level Vdd, the Bit Line (BL)520 is connected to the level Vdd, the Read Line (RL)710 is connected to a level GND, and the Word Line (WL)810 is connected to the level GND; a Source Line (SL)620 of a memory cell towards the lower left (DL) is switched to a level GND, a Bit Line (BL)510 is switched to the level GND, a Read Line (RL)720 is switched to the level GND, and a Word Line (WL)820 is switched to the level GND; the Source Line (SL)620 of the memory cell at the lower right (DR) is brought into the level GND, the Bit Line (BL)520 is brought into the level Vdd, the Read Line (RL)720 is brought into the level GND, and the Word Line (WL)820 is brought into the level GND.

Similarly, when reading data from the memory cell, the present embodiment will be described by taking the example of reading the data of the Upper Left (UL) memory cell.

	UL	UR	DL	DR
					RL	Vread	Vread	GND	GND
WL	Vg	Vg	GND	GND
					SL	GND	GND	GND	GND
BL	GND	Vread	GND	Vread

As shown in the above table, in the present embodiment, the Source Line (SL)610 is connected to the level GND, the Bit Line (BL)510 is also connected to the level GND, the Read Line (RL)710 is connected to the level Vread, and the Word Line (WL)810 is connected to the level Vg; vread represents a preset read voltage, Vg represents a gate voltage, and is used to turn on the mosfet 300 (transistor), a read current is generated in the MTJ to be read by applying the preset read voltage Vread, and the sense amplifier receives a corresponding feedback signal to determine whether the current tunnel junction is in a low resistance state or a high resistance state, thereby determining data stored in the tunnel junction. At this time, according to the memory array, a plurality of memory cells along the x direction share the source line 610, the source line 620, the read line 710, the read line 720, the word line 810 and the word line 820, a plurality of memory cells along the y direction share the bit line 510 and the bit line 520, in order to avoid reading data in memory cells of Upper Right (UR), lower left (DL) and lower right (DR), the Source Line (SL)610 of the memory cell of the Upper Right (UR) is switched into the level GND, the Bit Line (BL)520 is switched into the level Vread, the Read Line (RL)710 is switched into the level Vread, and the Word Line (WL)810 is switched into the level Vg; a Source Line (SL)620 of a memory cell towards the lower left (DL) is switched to a level GND, a Bit Line (BL)510 is switched to the level GND, a Read Line (RL)720 is switched to the level GND, and a Word Line (WL)820 is switched to the level GND; the Source Line (SL)620 of the memory cell in the lower right (DR) is turned on to the level GND, the Bit Line (BL)520 is turned on to the level Vread, the Read Line (RL)720 is turned on to the level GND, and the Word Line (WL)820 is turned on to the level GND.

As shown in FIG. 5, and as may be combined with FIG. 4, other embodiments of the present invention can also provide a process for writing a data "1" or "0" to a memory array.

	UL	UR	DL	DR
					RL	GND	GND	GND	GND
SL	Vdd	Vdd	GND	GND
					BL	GND	Vdd	GND	Vdd

As shown in the above table, data is written into the memory cell at the Upper Left (UL), for example, "1" is written in the high resistance state, "0" is written in the low resistance state, or "0" is written in the high resistance state, "1" is written in the low resistance state. In the embodiment, a Source Line (SL)610 is connected to a level Vdd, a Bit Line (BL)510 is connected to a level GND to form a unidirectional current in a horizontal direction, and the direction of the unidirectional current is consistent with the conducting direction of a diode; the Read Line (RL)710 is brought into the level GND. The present invention writes a "1" or a "0" into the memory cell by changing the magnitude of the Vdd value. At this time, according to the memory array, a plurality of memory cells along the x direction share the source line 610, the source line 620, the read line 710 and the read line 720, and a plurality of memory cells along the y direction share the bit line 510 and the bit line 520, in order to avoid writing data in the memory cells of the Upper Right (UR), the lower left (DL) and the lower right (DR), the Source Line (SL)610 of the memory cell of the Upper Right (UR) is connected to the level Vdd, the Bit Line (BL)520 is connected to the level Vdd, and the Read Line (RL)710 is connected to the level GND; a Source Line (SL)620 of a memory cell towards the lower left (DL) is switched into a level GND, a Bit Line (BL)510 is switched into the level GND, and a Read Line (RL)720 is switched into the level GND; the Source Line (SL)620 of the memory cell at the lower right (DR) is brought into the level GND, the Bit Line (BL)520 is brought into the level Vdd, and the Read Line (RL)720 is brought into the level GND.

Similarly, when reading data from the memory cells in the memory array, the Upper Left (UL) memory cell is still used as an example.

	UL	UR	DL	DR
					RL	Vread	Vread	GND	GND
SL	GND	GND	GND	GND
					BL	GND	Vread	GND	Vread

As shown in the above table, in the present embodiment, the Source Line (SL)610 is connected to the level GND, the Bit Line (BL)510 is also connected to the level GND, and the Read Line (RL)710 is connected to the level Vread, where Vread represents a preset read voltage, and the current tunnel junction is determined to be in a low resistance state or a high resistance state by a feedback signal received by the sense amplifier after the preset read voltage is applied, so as to determine that the stored data is "1" or "0". At this time, according to the memory array, a plurality of memory cells along the x direction share a source line 610, a source line 620, a read line 710 and a read line 720, and a plurality of memory cells along the y direction share a bit line 510 and a bit line 520, in order to avoid reading data in memory cells of an Upper Right (UR), a lower left (DL) and a lower right (DR), the Source Line (SL)610 of the memory cell of the Upper Right (UR) is switched to a level GND, the Bit Line (BL)520 is also switched to a level Vread, and the Read Line (RL)710 is switched to the level Vread; a Source Line (SL)620 of a memory cell towards the lower left (DL) is switched into a level GND, a Bit Line (BL)510 is also switched into the level GND, and a Read Line (RL)720 is switched into the level GND; the Source Line (SL)620 of the memory cell at the lower right (DR) is turned on to the level GND, the Bit Line (BL)520 is turned on to the level Vread, and the Read Line (RL)720 is turned on to the level GND.

As shown in FIG. 7, and as may be combined with FIG. 6, still other embodiments of the invention can provide a process for writing a data "1" or "0" to a memory array.

As shown in the above table, data is written into the memory cell at the Upper Left (UL), for example, "1" is written in the high resistance state, "0" is written in the low resistance state, or "0" is written in the high resistance state, "1" is written in the low resistance state. In the embodiment, a Source Line (SL)610 is connected to a level GND, and a Bit Line (BL)510 is connected to a level Vdd so as to form a unidirectional current in a horizontal direction; the Read Line (RL)710 is brought into a level Vdd. The present invention writes a "1" or a "0" into the memory cell by changing the magnitude of the Vdd value. At this time, according to the memory array, a plurality of memory cells along the x direction share a source line 610, a source line 620, a read line 710 and a read line 720, and a plurality of memory cells along the y direction share a bit line 510 and a bit line 520, in order to avoid writing data in the memory cells to the Upper Right (UR), the lower left (DL) and the lower right (DR), the Source Line (SL)610 of the memory cell to the Upper Right (UR) is switched to a level GND, the Bit Line (BL)520 is switched to the level GND, and the Read Line (RL)710 is switched to the level Vdd; the Source Line (SL)620 of the memory cell towards the lower left (DL) is switched to the level Vdd, the Bit Line (BL)510 is switched to the level Vdd, and the Read Line (RL)720 is switched to the level Vdd; the Source Line (SL)620 of the memory cell at the lower right (DR) is brought into the level Vdd, the Bit Line (BL)520 is brought into the level GND, and the Read Line (RL)720 is brought into the level Vdd.

	UL	UR	DL	DR
					RL	GND	GND	Vread	Vread
SL	Vread	Vread	Vread	Vread
					BL	Vread	GND	Vread	GND

As shown in the above table, in the present embodiment, the Source Line (SL)610 is connected to the level Vread, the Bit Line (BL)510 is also connected to the level Vread, and the Read Line (RL)710 is connected to the level GND, where Vread represents a preset read voltage, and the current tunnel junction is determined to be in a low resistance state or a high resistance state according to a feedback signal received by the sense amplifier after the preset read voltage, so as to determine that the stored data is "1" or "0". At this time, according to the memory array, a plurality of memory cells along the x direction share a source line 610, a source line 620, a read line 710 and a read line 720, and a plurality of memory cells along the y direction share a bit line 510 and a bit line 520, in order to avoid reading data in memory cells of the Upper Right (UR), the lower left (DL) and the lower right (DR), the Source Line (SL)610 of the memory cell of the Upper Right (UR) is switched to a level Vread, the Bit Line (BL)520 is also switched to a level GND, and the Read Line (RL)710 is switched to the level GND; a Source Line (SL)620 of a memory cell in a lower left (DL) is turned on to a level Vread, a Bit Line (BL)510 is also turned on to the level Vread, and a Read Line (RL)720 is turned on to the level Vread; the Source Line (SL)620 of the memory cell at the lower right (DR) is turned on at the level Vread, the Bit Line (BL)520 is turned on at the level GND, and the Read Line (RL)720 is turned on at the level Vread.

As shown in fig. 2 to 3, the present invention can provide a memory circuit based on the same inventive concept as the data writing method or the data reading method of the memory circuit. The memory circuit in one or more embodiments of the invention includes, but is not limited to, a bottom electrode 100, a tunnel junction 200, a first switching device 300, a second switching device 400, a bit line BL (500,510,520), a source line SL (600,610,620), a read line RL (700,710,720), a word line (800,810,820), and the like.

The bottom electrode 100 is used for introducing a unidirectional current in the data writing process so as to write data into the tunnel junction 200 above the bottom electrode 100; the bottom electrode 100 of this embodiment is specifically a thin film electrode material having an SOT (spin-orbit coupling) effect.

The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100, the tunnel junction 200 according to the embodiment of the present invention is used for storing written data, and a predetermined read voltage Vread is applied to the tunnel junction 200 to generate a read current in a data reading process, so as to read data stored in the tunnel junction.

As shown in fig. 8, the tunnel junction 200 of the present embodiment is a multi-layer thin film structure, and the tunnel junction 200 may include, but is not limited to, a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode sequentially disposed. The antiferromagnetic layer in this embodiment is an artificial antiferromagnetic layer. In the embodiment of the present invention, the bottom electrode 100, the free Layer, the tunneling Layer, the reference Layer, the intermediate Layer, the antiferromagnetic Layer, and the top electrode may be sequentially formed through a thin film growth process such as PVD (Physical Vapor Deposition) or ALD (Atomic Layer Deposition), for example, the SOT bottom electrode 100 may be formed by growing Ta (tantalum), Pt (platinum), W (tungsten), and the like, and the free Layer may be formed by growing Co (cobalt), CoFeB (a magnetic material), and the like.

As shown in fig. 2 and 3, the present invention can form a memory circuit by a memory array structure. Wherein a first switching device 300 is connected to the tunnel junction 200 and a second switching device 400 is connected to one end of the bottom electrode 100. Alternatively, the first switching device 300 of the present invention is a metal oxide semiconductor field effect transistor (transistor), the second switching device 400 is a diode, and the conduction direction is a direction from the source line (600,610,620) to the bottom electrode 100. The bit line (500,510,520) BL in the present invention is connected to the other end of the bottom electrode 100 corresponding to the source line. Also, a source line (600,610,620) SL is connected to the second switching device 400. The read line (700,710,720) RL in the present invention is connected to the first switching device 300 and the word line (800,810,820) WL is connected to the gate of the MOSFET.

The bottom electrode 100 and the tunnel junction 200 form a memory cell, and a plurality of memory cells may form a memory array. In the memory array according to the embodiment of the present invention, the source line 610, the source line 620, the read line 710, the read line 720, the word line 810, and the word line 820 are shared by a plurality of memory cells along the x direction, and the bit line 510 and the bit line 520 are shared by a plurality of memory cells along the y direction. The tunnel junction 200 comprises a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode which are sequentially arranged; wherein the free layer is disposed on the bottom electrode 100.

As shown in fig. 4 to 5, the present invention can also provide a memory circuit in another structure form based on the same technical concept as the data writing method or the data reading method of the memory circuit. The memory circuit in one or more embodiments of the invention may include, but is not limited to, a bottom electrode 100, a tunnel junction 200, a first switching device 300, a second switching device 400, a bit line BL (500,510,520), a source line SL (600,610,620), and a read line RL (700,710, 720). The bottom electrode 100 is also used for applying a unidirectional current thereto during data writing, so as to write information into the tunnel junction 200 above the bottom electrode 100, and may be formed of an electrode material having a spin-orbit coupling effect. The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100, and data can be read from the tunnel junction 200 by applying a predetermined read voltage to the read line RL above the tunnel junction. In the memory array of this embodiment, a plurality of memory cells in the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and a plurality of memory cells in the y direction share the bit line 510 and the bit line 520. The tunnel junction 200 includes a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer, and a top electrode, which are sequentially disposed; wherein the free layer of the present invention is disposed on the bottom electrode 100.

As shown in fig. 4 and 5, the first switching device 300 of this embodiment is a diode, and the conduction direction is from the read line (700,710,720) to the tunnel junction 200, which is different from the memory circuit structure shown in fig. 2 and 3. The second switching device 400 of this embodiment is a diode, and the conducting direction is specifically the direction of the unidirectional current, illustrated as the direction from the source line (600,610,620) to the bottom electrode 100. The bottom electrode 100 and the tunnel junction 200 form a memory cell, and a plurality of memory cells form a memory array.

As shown in fig. 6 and 7, the data writing method or the data reading method of the memory circuit is based on the same technical concept, and the invention can also provide memory circuits with other structural forms. The memory circuit in one or more embodiments of the invention may include, but is not limited to, a bottom electrode 100, a tunnel junction 200, a first switching device 300, a second switching device 400, a bit line BL (500,510,520), a source line SL (600,610,620), and a read line RL (700,710, 720). The bottom electrode 100 is also used for passing a unidirectional current thereto during data writing to write data into the tunnel junction 200 above the bottom electrode 100, and may be made of a material having a spin-orbit coupling effect. The tunnel junction 200 is disposed on the bottom electrode 100 and connected to the bottom electrode 100, and data can be read from the tunnel junction 200 according to a feedback signal received by the sense amplifier after a preset read voltage is applied to the tunnel junction. In the memory array of this embodiment, a plurality of memory cells in the x direction share the source line 610, the source line 620, the read line 710, and the read line 720, and a plurality of memory cells in the y direction share the bit line 510 and the bit line 520. The tunnel junction 200 includes a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer, and a top electrode, which are sequentially disposed; the free layer is disposed on the bottom electrode 100.

As shown in fig. 6 and 7, the first switching device 300 of this embodiment is a diode, and the conduction direction is from the tunnel junction 200 to the read line (700,710,720), which is different from the memory circuit structure of fig. 2 and 3. The second switching device 400 of this embodiment is a diode, and the conducting direction is specifically the direction of the unidirectional current, illustrated as the direction from the bottom electrode 100 to the source line (600,610,620). The bottom electrode 100 and the tunnel junction 200 form a memory cell, and a plurality of memory cells form a memory array.

The present invention can also provide a memory, which can include, but is not limited to, a memory circuit in any embodiment of the present invention, based on the same inventive technical concept as the data writing or reading method of the memory circuit.

The invention can also provide an electronic device which can include, but is not limited to, the memory in any embodiment of the invention based on the same inventive technical concept as the data writing or reading method of the memory circuit.

It should be understood that electronic devices to which the present invention relates may include, but are not limited to, smart phones, computers, tablets, wearable smart devices, artificial smart devices, mobile power sources, and the like.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A method of writing data to a memory circuit, comprising:

introducing unidirectional current within a first preset range into a bottom electrode connected with the tunnel junction so as to write first data into the tunnel junction;

or, a unidirectional current in a second preset range is introduced into the bottom electrode connected with the tunnel junction so as to write second data into the tunnel junction;

and the current absolute value in the second preset range is larger than the current absolute value in the first preset range, and the first data is opposite to the second data.

2. The method of claim 1, wherein passing a unidirectional current in a first predetermined range to the bottom electrode coupled to the tunnel junction comprises:

and enabling the direction of the unidirectional current to be the same as the conduction direction of a diode, wherein the diode is connected with the bottom electrode.

3. The data writing method of the memory circuit according to claim 1 or 2,

the first data is "1", and the second data is "0";

alternatively, the first data is "0" and the second data is "1".

4. The data writing method of the memory circuit according to claim 1 or 2,

the unidirectional current is parallel to the extending direction of the bottom electrode.

5. A method for reading data from a memory circuit, comprising:

and applying a preset reading voltage to the tunnel junction connected with the bottom electrode so as to read out the first data or the second data which are written into the tunnel junction and stored in the tunnel junction.

6. A memory circuit, comprising:

the bottom electrode is used for introducing unidirectional current in the data writing process;

the tunnel junction is arranged on the bottom electrode, is connected with the bottom electrode and is used for storing written data;

a first switching device connected to the tunnel junction;

a second switching device connected to one end of the bottom electrode;

a bit line connected to the other end of the bottom electrode;

a source line connected to the second switching device;

a read line connected with the first switching device.

7. The memory circuit of claim 6,

the first switching device is a metal oxide semiconductor field effect transistor;

the second switching device is a diode, and the conduction direction is the same as the direction of the unidirectional current;

the memory circuit further includes a word line;

the word line is connected with the grid electrode of the metal oxide semiconductor field effect transistor.

8. The memory circuit of claim 6,

the first switch device is a diode, and the conduction direction is from the reading line to the tunnel junction or from the tunnel junction to the reading line;

the second switching device is a diode, and the conduction direction is the same as the direction of the unidirectional current.

9. The memory circuit of any one of claims 6 to 8,

the bottom electrode and the tunnel junction form a storage unit;

a plurality of the memory cells form a memory array.

10. The memory circuit of any one of claims 6 to 8,

the tunnel junction comprises a free layer, a tunneling layer, a reference layer, an intermediate layer, an antiferromagnetic layer and a top electrode which are sequentially arranged;

wherein the free layer is disposed on the bottom electrode.

11. A memory comprising the memory circuit of any one of claims 6 to 10.

12. An electronic device, characterized in that the electronic device comprises the memory of claim 11.